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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_wishbone.v] - Blame information for rev 86

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1 16 csantifort
//////////////////////////////////////////////////////////////////
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//                                                              //
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//  Wishbone master interface for the Amber 25 core             //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Turns memory access requests from the execute stage and     //
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//  instruction and data caches into wishbone bus cycles.       //
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//  For 4-word read requests from either cache and swap         //
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//  accesses ( read followed by write to the same address)      //
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//  from the execute stage, a block transfer is done.           //
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//  All other requests result in single word transfers.         //
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//                                                              //
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//  Write accesses can be done in a single clock cycle on       //
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//  the wishbone bus, is the destination allows it. The         //
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//  next transfer will begin immediately on the                 //
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//  next cycle on the bus. This looks like a block transfer     //
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//  and does hold ownership of the wishbone bus, preventing     //
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//  the other master ( the ethernet MAC) from gaining           //
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//  ownership between those two cycles. But otherwise it would  //
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//  be necessary to insert a wait cycle after every write,      //
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//  slowing down the performance of the core by around 5 to     //
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//  10%.                                                        //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2011 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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58 35 csantifort
// TODO add support for exclusive accesses
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module a25_wishbone
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(
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input                       i_clk,
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// Port 0 - dcache uncached
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input                       i_port0_req,
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output                      o_port0_ack,
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input                       i_port0_write,
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input       [127:0]         i_port0_wdata,
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input       [15:0]          i_port0_be,
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input       [31:0]          i_port0_addr,
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output      [127:0]         o_port0_rdata,
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// Port 1 - dcache cached
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input                       i_port1_req,
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output                      o_port1_ack,
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input                       i_port1_write,
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input       [127:0]         i_port1_wdata,
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input       [15:0]          i_port1_be,
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input       [31:0]          i_port1_addr,
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output      [127:0]         o_port1_rdata,
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// Port 2 - instruction cache accesses, read only
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input                       i_port2_req,
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output                      o_port2_ack,
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input                       i_port2_write,
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input       [127:0]         i_port2_wdata,
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input       [15:0]          i_port2_be,
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input       [31:0]          i_port2_addr,
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output      [127:0]         o_port2_rdata,
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// 128-bit Wishbone Bus
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output reg  [31:0]          o_wb_adr = 'd0,
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output reg  [15:0]          o_wb_sel = 'd0,
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output reg                  o_wb_we  = 'd0,
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output reg  [127:0]         o_wb_dat = 'd0,
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output reg                  o_wb_cyc = 'd0,
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output reg                  o_wb_stb = 'd0,
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input       [127:0]         i_wb_dat,
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input                       i_wb_ack,
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input                       i_wb_err
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);
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// ----------------------------------------------------
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// Parameters
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// ----------------------------------------------------
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localparam WBUF = 3;
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// ----------------------------------------------------
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// Signals
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// ----------------------------------------------------
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wire [0:0]                  wbuf_valid          [WBUF-1:0];
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wire [0:0]                  wbuf_accepted       [WBUF-1:0];
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wire [0:0]                  wbuf_write          [WBUF-1:0];
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wire [127:0]                wbuf_wdata          [WBUF-1:0];
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wire [15:0]                 wbuf_be             [WBUF-1:0];
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wire [31:0]                 wbuf_addr           [WBUF-1:0];
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wire [0:0]                  wbuf_rdata_valid    [WBUF-1:0];
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wire                        new_access;
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reg  [WBUF-1:0]             serving_port = 'd0;
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126 35 csantifort
// ----------------------------------------------------
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// Instantiate the write buffers
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// ----------------------------------------------------
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a25_wishbone_buf u_a25_wishbone_buf_p0 (
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    .i_clk          ( i_clk                 ),
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    .i_req          ( i_port0_req           ),
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    .o_ack          ( o_port0_ack           ),
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    .i_write        ( i_port0_write         ),
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    .i_wdata        ( i_port0_wdata         ),
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    .i_be           ( i_port0_be            ),
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    .i_addr         ( i_port0_addr          ),
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    .o_rdata        ( o_port0_rdata         ),
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    .o_valid        ( wbuf_valid       [0]  ),
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    .i_accepted     ( wbuf_accepted    [0]  ),
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    .o_write        ( wbuf_write       [0]  ),
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    .o_wdata        ( wbuf_wdata       [0]  ),
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    .o_be           ( wbuf_be          [0]  ),
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    .o_addr         ( wbuf_addr        [0]  ),
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    .i_rdata        ( i_wb_dat              ),
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    .i_rdata_valid  ( wbuf_rdata_valid [0]  )
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    );
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a25_wishbone_buf u_a25_wishbone_buf_p1 (
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    .i_clk          ( i_clk                 ),
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    .i_req          ( i_port1_req           ),
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    .o_ack          ( o_port1_ack           ),
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    .i_write        ( i_port1_write         ),
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    .i_wdata        ( i_port1_wdata         ),
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    .i_be           ( i_port1_be            ),
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    .i_addr         ( i_port1_addr          ),
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    .o_rdata        ( o_port1_rdata         ),
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    .o_valid        ( wbuf_valid        [1] ),
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    .i_accepted     ( wbuf_accepted     [1] ),
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    .o_write        ( wbuf_write        [1] ),
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    .o_wdata        ( wbuf_wdata        [1] ),
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    .o_be           ( wbuf_be           [1] ),
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    .o_addr         ( wbuf_addr         [1] ),
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    .i_rdata        ( i_wb_dat              ),
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    .i_rdata_valid  ( wbuf_rdata_valid  [1] )
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    );
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173 35 csantifort
a25_wishbone_buf u_a25_wishbone_buf_p2 (
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    .i_clk          ( i_clk                 ),
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    .i_req          ( i_port2_req           ),
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    .o_ack          ( o_port2_ack           ),
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    .i_write        ( i_port2_write         ),
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    .i_wdata        ( i_port2_wdata         ),
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    .i_be           ( i_port2_be            ),
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    .i_addr         ( i_port2_addr          ),
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    .o_rdata        ( o_port2_rdata         ),
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    .o_valid        ( wbuf_valid        [2] ),
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    .i_accepted     ( wbuf_accepted     [2] ),
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    .o_write        ( wbuf_write        [2] ),
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    .o_wdata        ( wbuf_wdata        [2] ),
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    .o_be           ( wbuf_be           [2] ),
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    .o_addr         ( wbuf_addr         [2] ),
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    .i_rdata        ( i_wb_dat              ),
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    .i_rdata_valid  ( wbuf_rdata_valid  [2] )
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    );
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assign new_access       = !o_wb_stb || i_wb_ack;
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assign wbuf_accepted[0] = new_access &&  wbuf_valid[0];
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assign wbuf_accepted[1] = new_access && !wbuf_valid[0] &&  wbuf_valid[1];
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assign wbuf_accepted[2] = new_access && !wbuf_valid[0] && !wbuf_valid[1] && wbuf_valid[2];
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always @(posedge i_clk)
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    begin
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    if (new_access)
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        begin
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        if (wbuf_valid[0])
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            begin
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            o_wb_adr        <= wbuf_addr [0];
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            o_wb_sel        <= wbuf_be   [0];
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            o_wb_we         <= wbuf_write[0];
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            o_wb_dat        <= wbuf_wdata[0];
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            o_wb_cyc        <= 1'd1;
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            o_wb_stb        <= 1'd1;
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            serving_port    <= 3'b001;
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            end
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        else if (wbuf_valid[1])
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            begin
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            o_wb_adr        <= wbuf_addr [1];
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            o_wb_sel        <= wbuf_be   [1];
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            o_wb_we         <= wbuf_write[1];
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            o_wb_dat        <= wbuf_wdata[1];
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            o_wb_cyc        <= 1'd1;
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            o_wb_stb        <= 1'd1;
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            serving_port    <= 3'b010;
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            end
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        else if (wbuf_valid[2])
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            begin
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            o_wb_adr        <= wbuf_addr [2];
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            o_wb_sel        <= wbuf_be   [2];
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            o_wb_we         <= wbuf_write[2];
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            o_wb_dat        <= wbuf_wdata[2];
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            o_wb_cyc        <= 1'd1;
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            o_wb_stb        <= 1'd1;
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            serving_port    <= 3'b100;
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            end
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        else
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            begin
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            o_wb_cyc        <= 1'd0;
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            o_wb_stb        <= 1'd0;
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            // Don't need to change these values because they are ignored
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            // when stb is low, but it makes for a cleaner waveform, at the expense of a few gates
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            o_wb_we         <= 1'd0;
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            o_wb_adr        <= 'd0;
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            o_wb_dat        <= 'd0;
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            serving_port    <= 3'b000;
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            end
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        end
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    end
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assign {wbuf_rdata_valid[2], wbuf_rdata_valid[1], wbuf_rdata_valid[0]} = {3{i_wb_ack & ~ o_wb_we}} & serving_port;
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endmodule
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