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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_wishbone_buf.v] - Blame information for rev 47

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//////////////////////////////////////////////////////////////////
//                                                              //
//  Wishbone master interface port buffer                       //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  This is a sub-module of the Amber wishbone master           //
//  interface. The wishbone master interface connects a number  //
//  of internal amber ports to the wishbone bus. The ports      //
//  are;                                                        //
//       instruction cache read accesses                        //
//       data cache read and write accesses (cached)            //
//       data cache read and write accesses (uncached)          //
//                                                              //
//  The buffer module buffers a single port. For write          //
//  requests, this allows the processor core to continue        //
//  executing withont having to wait for the wishbone write     //
//  operation to complete.                                      //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2011 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
module a25_wishbone_buf (
input                       i_clk,
 
// Core side
input                       i_req,
input                       i_write,
input       [127:0]         i_wdata,
input       [15:0]          i_be,
input       [31:0]          i_addr,
output      [127:0]         o_rdata,
output                      o_ack,
 
// Wishbone side
output                      o_valid,
input                       i_accepted,
output                      o_write,
output      [127:0]         o_wdata,
output      [15:0]          o_be,
output      [31:0]          o_addr,
input       [127:0]         i_rdata,
input                       i_rdata_valid
);
 
 
// ----------------------------------------------------
// Signals
// ----------------------------------------------------
reg  [1:0]                  wbuf_used_r     = 'd0;
reg  [127:0]                wbuf_wdata_r    [1:0];
reg  [31:0]                 wbuf_addr_r     [1:0];
reg  [15:0]                 wbuf_be_r       [1:0];
reg  [1:0]                  wbuf_write_r    = 'd0;
reg                         wbuf_wp_r       = 'd0;        // write buf write pointer
reg                         wbuf_rp_r       = 'd0;        // write buf read pointer
reg                         busy_reading_r  = 'd0;
reg                         wait_rdata_valid_r = 'd0;
wire                        in_wreq;
reg                         ack_owed_r      = 'd0;
 
// ----------------------------------------------------
// Access Buffer
// ----------------------------------------------------
assign in_wreq = i_req && i_write;
assign push    = i_req && !busy_reading_r && (wbuf_used_r == 2'd1 || (wbuf_used_r == 2'd0 && !i_accepted));
assign pop     = o_valid && i_accepted && wbuf_used_r != 2'd0;
 
always @(posedge i_clk)
    if (push && pop)
        wbuf_used_r     <= wbuf_used_r;
    else if (push)
        wbuf_used_r     <= wbuf_used_r + 1'd1;
    else if (pop)
        wbuf_used_r     <= wbuf_used_r - 1'd1;
 
always @(posedge i_clk)
    if (push && in_wreq && !o_ack)
        ack_owed_r = 1'd1;
    else if (!i_req && o_ack)
        ack_owed_r = 1'd0;
 
always @(posedge i_clk)
    if (push)
        begin
        wbuf_wdata_r [wbuf_wp_r]   <= i_wdata;
        wbuf_addr_r  [wbuf_wp_r]   <= i_addr;
        wbuf_be_r    [wbuf_wp_r]   <= i_write ? i_be : 16'hffff;
        wbuf_write_r [wbuf_wp_r]   <= i_write;
        wbuf_wp_r                  <= !wbuf_wp_r;
        end
 
always @(posedge i_clk)
    if (pop)
        wbuf_rp_r                  <= !wbuf_rp_r;
 
 
// ----------------------------------------------------
// Output logic
// ----------------------------------------------------
assign o_wdata = wbuf_used_r != 2'd0 ? wbuf_wdata_r[wbuf_rp_r] : i_wdata;
assign o_write = wbuf_used_r != 2'd0 ? wbuf_write_r[wbuf_rp_r] : i_write;
assign o_addr  = wbuf_used_r != 2'd0 ? wbuf_addr_r [wbuf_rp_r] : i_addr;
assign o_be    = wbuf_used_r != 2'd0 ? wbuf_be_r   [wbuf_rp_r] : i_write ? i_be : 16'hffff;
 
assign o_ack   = (in_wreq ? (wbuf_used_r == 2'd0) : i_rdata_valid) || (ack_owed_r && pop);
assign o_valid = (wbuf_used_r != 2'd0 || i_req) && !wait_rdata_valid_r;
 
assign o_rdata = i_rdata;
 
 
always@(posedge i_clk)
    if (o_valid && !o_write)
        busy_reading_r <= 1'd1;
    else if (i_rdata_valid)
        busy_reading_r <= 1'd0;
 
always@(posedge i_clk)
    if (o_valid && !o_write && i_accepted)
        wait_rdata_valid_r <= 1'd1;
    else if (i_rdata_valid)
        wait_rdata_valid_r <= 1'd0;
endmodule
 
 
 
 

Line No.	Rev	Author	Line
1	35	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Wishbone master interface port buffer //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// This is a sub-module of the Amber wishbone master //`
10			`// interface. The wishbone master interface connects a number //`
11			`// of internal amber ports to the wishbone bus. The ports //`
12			`// are; //`
13			`// instruction cache read accesses //`
14			`// data cache read and write accesses (cached) //`
15			`// data cache read and write accesses (uncached) //`
16			`// //`
17			`// The buffer module buffers a single port. For write //`
18			`// requests, this allows the processor core to continue //`
19			`// executing withont having to wait for the wishbone write //`
20			`// operation to complete. //`
21			`// //`
22			`// Author(s): //`
23			`// - Conor Santifort, csantifort.amber@gmail.com //`
24			`// //`
25			`//////////////////////////////////////////////////////////////////`
26			`// //`
27			`// Copyright (C) 2011 Authors and OPENCORES.ORG //`
28			`// //`
29			`// This source file may be used and distributed without //`
30			`// restriction provided that this copyright statement is not //`
31			`// removed from the file and that any derivative work contains //`
32			`// the original copyright notice and the associated disclaimer. //`
33			`// //`
34			`// This source file is free software; you can redistribute it //`
35			`// and/or modify it under the terms of the GNU Lesser General //`
36			`// Public License as published by the Free Software Foundation; //`
37			`// either version 2.1 of the License, or (at your option) any //`
38			`// later version. //`
39			`// //`
40			`// This source is distributed in the hope that it will be //`
41			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
42			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
43			`// PURPOSE. See the GNU Lesser General Public License for more //`
44			`// details. //`
45			`// //`
46			`// You should have received a copy of the GNU Lesser General //`
47			`// Public License along with this source; if not, download it //`
48			`// from http://www.opencores.org/lgpl.shtml //`
49			`// //`
50			`//////////////////////////////////////////////////////////////////`
51
52			`module a25_wishbone_buf (`
53			`input i_clk,`
54
55			`// Core side`
56			`input i_req,`
57			`input i_write,`
58			`input [127:0] i_wdata,`
59			`input [15:0] i_be,`
60			`input [31:0] i_addr,`
61			`output [127:0] o_rdata,`
62	39	csantifort	`output o_ack,`
63	35	csantifort
64			`// Wishbone side`
65			`output o_valid,`
66			`input i_accepted,`
67			`output o_write,`
68			`output [127:0] o_wdata,`
69			`output [15:0] o_be,`
70			`output [31:0] o_addr,`
71			`input [127:0] i_rdata,`
72			`input i_rdata_valid`
73			`);`
74
75
76			`// ----------------------------------------------------`
77			`// Signals`
78			`// ----------------------------------------------------`
79	39	csantifort	`reg [1:0] wbuf_used_r = 'd0;`
80			`reg [127:0] wbuf_wdata_r [1:0];`
81			`reg [31:0] wbuf_addr_r [1:0];`
82			`reg [15:0] wbuf_be_r [1:0];`
83			`reg [1:0] wbuf_write_r = 'd0;`
84			`reg wbuf_wp_r = 'd0; // write buf write pointer`
85			`reg wbuf_rp_r = 'd0; // write buf read pointer`
86			`reg busy_reading_r = 'd0;`
87			`reg wait_rdata_valid_r = 'd0;`
88			`wire in_wreq;`
89			`reg ack_owed_r = 'd0;`
90	35	csantifort
91			`// ----------------------------------------------------`
92			`// Access Buffer`
93			`// ----------------------------------------------------`
94	39	csantifort	`assign in_wreq = i_req && i_write;`
95			`assign push = i_req && !busy_reading_r && (wbuf_used_r == 2'd1 \|\| (wbuf_used_r == 2'd0 && !i_accepted));`
96			`assign pop = o_valid && i_accepted && wbuf_used_r != 2'd0;`
97
98	35	csantifort	`always @(posedge i_clk)`
99	39	csantifort	`if (push && pop)`
100			`wbuf_used_r <= wbuf_used_r;`
101			`else if (push)`
102			`wbuf_used_r <= wbuf_used_r + 1'd1;`
103			`else if (pop)`
104			`wbuf_used_r <= wbuf_used_r - 1'd1;`
105
106			`always @(posedge i_clk)`
107			`if (push && in_wreq && !o_ack)`
108			`ack_owed_r = 1'd1;`
109			`else if (!i_req && o_ack)`
110			`ack_owed_r = 1'd0;`
111
112			`always @(posedge i_clk)`
113			`if (push)`
114	35	csantifort	`begin`
115	39	csantifort	`wbuf_wdata_r [wbuf_wp_r] <= i_wdata;`
116			`wbuf_addr_r [wbuf_wp_r] <= i_addr;`
117			`wbuf_be_r [wbuf_wp_r] <= i_write ? i_be : 16'hffff;`
118			`wbuf_write_r [wbuf_wp_r] <= i_write;`
119			`wbuf_wp_r <= !wbuf_wp_r;`
120	35	csantifort	`end`
121
122	39	csantifort	`always @(posedge i_clk)`
123			`if (pop)`
124			`wbuf_rp_r <= !wbuf_rp_r;`
125
126	35	csantifort
127			`// ----------------------------------------------------`
128			`// Output logic`
129			`// ----------------------------------------------------`
130	39	csantifort	`assign o_wdata = wbuf_used_r != 2'd0 ? wbuf_wdata_r[wbuf_rp_r] : i_wdata;`
131			`assign o_write = wbuf_used_r != 2'd0 ? wbuf_write_r[wbuf_rp_r] : i_write;`
132			`assign o_addr = wbuf_used_r != 2'd0 ? wbuf_addr_r [wbuf_rp_r] : i_addr;`
133			`assign o_be = wbuf_used_r != 2'd0 ? wbuf_be_r [wbuf_rp_r] : i_write ? i_be : 16'hffff;`
134	35	csantifort
135	39	csantifort	`assign o_ack = (in_wreq ? (wbuf_used_r == 2'd0) : i_rdata_valid) \|\| (ack_owed_r && pop);`
136			`assign o_valid = (wbuf_used_r != 2'd0 \|\| i_req) && !wait_rdata_valid_r;`
137	35	csantifort
138			`assign o_rdata = i_rdata;`
139
140
141			`always@(posedge i_clk)`
142	39	csantifort	`if (o_valid && !o_write)`
143	35	csantifort	`busy_reading_r <= 1'd1;`
144			`else if (i_rdata_valid)`
145			`busy_reading_r <= 1'd0;`
146
147	39	csantifort	`always@(posedge i_clk)`
148			`if (o_valid && !o_write && i_accepted)`
149			`wait_rdata_valid_r <= 1'd1;`
150			`else if (i_rdata_valid)`
151			`wait_rdata_valid_r <= 1'd0;`
152	35	csantifort	`endmodule`
153
154
155
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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_wishbone_buf.v] - Blame information for rev 47