| 1 |
16 |
csantifort |
//////////////////////////////////////////////////////////////////
|
| 2 |
|
|
// //
|
| 3 |
|
|
// Write Back - Instantiates the write back stage //
|
| 4 |
|
|
// sub-modules of the Amber 25 Core //
|
| 5 |
|
|
// //
|
| 6 |
|
|
// This file is part of the Amber project //
|
| 7 |
|
|
// http://www.opencores.org/project,amber //
|
| 8 |
|
|
// //
|
| 9 |
|
|
// Description //
|
| 10 |
|
|
// //
|
| 11 |
|
|
// Author(s): //
|
| 12 |
|
|
// - Conor Santifort, csantifort.amber@gmail.com //
|
| 13 |
|
|
// //
|
| 14 |
|
|
//////////////////////////////////////////////////////////////////
|
| 15 |
|
|
// //
|
| 16 |
|
|
// Copyright (C) 2011 Authors and OPENCORES.ORG //
|
| 17 |
|
|
// //
|
| 18 |
|
|
// This source file may be used and distributed without //
|
| 19 |
|
|
// restriction provided that this copyright statement is not //
|
| 20 |
|
|
// removed from the file and that any derivative work contains //
|
| 21 |
|
|
// the original copyright notice and the associated disclaimer. //
|
| 22 |
|
|
// //
|
| 23 |
|
|
// This source file is free software; you can redistribute it //
|
| 24 |
|
|
// and/or modify it under the terms of the GNU Lesser General //
|
| 25 |
|
|
// Public License as published by the Free Software Foundation; //
|
| 26 |
|
|
// either version 2.1 of the License, or (at your option) any //
|
| 27 |
|
|
// later version. //
|
| 28 |
|
|
// //
|
| 29 |
|
|
// This source is distributed in the hope that it will be //
|
| 30 |
|
|
// useful, but WITHOUT ANY WARRANTY; without even the implied //
|
| 31 |
|
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
|
| 32 |
|
|
// PURPOSE. See the GNU Lesser General Public License for more //
|
| 33 |
|
|
// details. //
|
| 34 |
|
|
// //
|
| 35 |
|
|
// You should have received a copy of the GNU Lesser General //
|
| 36 |
|
|
// Public License along with this source; if not, download it //
|
| 37 |
|
|
// from http://www.opencores.org/lgpl.shtml //
|
| 38 |
|
|
// //
|
| 39 |
|
|
//////////////////////////////////////////////////////////////////
|
| 40 |
|
|
|
| 41 |
|
|
|
| 42 |
|
|
module a25_write_back
|
| 43 |
|
|
(
|
| 44 |
|
|
input i_clk,
|
| 45 |
|
|
input i_mem_stall, // Mem stage asserting stall
|
| 46 |
|
|
|
| 47 |
|
|
input [31:0] i_mem_read_data, // data reads
|
| 48 |
|
|
input i_mem_read_data_valid, // read data is valid
|
| 49 |
|
|
input [9:0] i_mem_load_rd, // Rd for data reads
|
| 50 |
|
|
|
| 51 |
|
|
output [31:0] o_wb_read_data, // data reads
|
| 52 |
|
|
output o_wb_read_data_valid, // read data is valid
|
| 53 |
|
|
output [9:0] o_wb_load_rd, // Rd for data reads
|
| 54 |
|
|
|
| 55 |
|
|
input [31:0] i_daddress,
|
| 56 |
|
|
input i_daddress_valid
|
| 57 |
|
|
);
|
| 58 |
|
|
|
| 59 |
|
|
reg [31:0] mem_read_data_r = 'd0; // Register read data from Data Cache
|
| 60 |
|
|
reg mem_read_data_valid_r = 'd0; // Register read data from Data Cache
|
| 61 |
|
|
reg [9:0] mem_load_rd_r = 'd0; // Register the Rd value for loads
|
| 62 |
|
|
reg [31:0] daddress_r = 'd0; // Register read data from Data Cache
|
| 63 |
|
|
|
| 64 |
|
|
assign o_wb_read_data = mem_read_data_r;
|
| 65 |
|
|
assign o_wb_read_data_valid = mem_read_data_valid_r;
|
| 66 |
|
|
assign o_wb_load_rd = mem_load_rd_r;
|
| 67 |
|
|
|
| 68 |
|
|
|
| 69 |
|
|
always @( posedge i_clk )
|
| 70 |
|
|
if ( !i_mem_stall )
|
| 71 |
|
|
begin
|
| 72 |
|
|
mem_read_data_r <= i_mem_read_data;
|
| 73 |
|
|
mem_read_data_valid_r <= i_mem_read_data_valid;
|
| 74 |
|
|
mem_load_rd_r <= i_mem_load_rd;
|
| 75 |
|
|
daddress_r <= i_daddress;
|
| 76 |
|
|
end
|
| 77 |
|
|
|
| 78 |
|
|
|
| 79 |
|
|
endmodule
|
| 80 |
|
|
|
