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csantifort |
//////////////////////////////////////////////////////////////////
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// //
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// Write Back - Instantiates the write back stage //
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// sub-modules of the Amber 25 Core //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2011 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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module a25_write_back
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(
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input i_clk,
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input i_mem_stall, // Mem stage asserting stall
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input [31:0] i_mem_read_data, // data reads
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input i_mem_read_data_valid, // read data is valid
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csantifort |
input [10:0] i_mem_load_rd, // Rd for data reads
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csantifort |
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output [31:0] o_wb_read_data, // data reads
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output o_wb_read_data_valid, // read data is valid
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output [10:0] o_wb_load_rd, // Rd for data reads
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input [31:0] i_daddress,
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input i_daddress_valid
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);
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reg [31:0] mem_read_data_r = 'd0; // Register read data from Data Cache
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reg mem_read_data_valid_r = 'd0; // Register read data from Data Cache
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reg [10:0] mem_load_rd_r = 'd0; // Register the Rd value for loads
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reg [31:0] daddress_r = 'd0; // Register read data from Data Cache
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assign o_wb_read_data = mem_read_data_r;
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assign o_wb_read_data_valid = mem_read_data_valid_r;
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assign o_wb_load_rd = mem_load_rd_r;
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always @( posedge i_clk )
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if ( !i_mem_stall )
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begin
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mem_read_data_r <= i_mem_read_data;
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mem_read_data_valid_r <= i_mem_read_data_valid;
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mem_load_rd_r <= i_mem_load_rd;
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daddress_r <= i_daddress;
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end
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endmodule
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