| 1 |
2 |
csantifort |
//////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//// ////
|
| 3 |
|
|
//// eth_register.v ////
|
| 4 |
|
|
//// ////
|
| 5 |
|
|
//// This file is part of the Ethernet IP core project ////
|
| 6 |
|
|
//// http://www.opencores.org/projects/ethmac/ ////
|
| 7 |
|
|
//// ////
|
| 8 |
|
|
//// Author(s): ////
|
| 9 |
|
|
//// - Igor Mohor (igorM@opencores.org) ////
|
| 10 |
|
|
//// ////
|
| 11 |
|
|
//// All additional information is avaliable in the Readme.txt ////
|
| 12 |
|
|
//// file. ////
|
| 13 |
|
|
//// ////
|
| 14 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 15 |
|
|
//// ////
|
| 16 |
|
|
//// Copyright (C) 2001, 2002 Authors ////
|
| 17 |
|
|
//// ////
|
| 18 |
|
|
//// This source file may be used and distributed without ////
|
| 19 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 20 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 21 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 22 |
|
|
//// ////
|
| 23 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 24 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 25 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 26 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 27 |
|
|
//// later version. ////
|
| 28 |
|
|
//// ////
|
| 29 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 30 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 31 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 32 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 33 |
|
|
//// details. ////
|
| 34 |
|
|
//// ////
|
| 35 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 36 |
|
|
//// Public License along with this source; if not, download it ////
|
| 37 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 38 |
|
|
//// ////
|
| 39 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 40 |
|
|
//
|
| 41 |
|
|
// CVS Revision History
|
| 42 |
|
|
//
|
| 43 |
|
|
// $Log: not supported by cvs2svn $
|
| 44 |
|
|
// Revision 1.5 2002/08/16 12:33:27 mohor
|
| 45 |
|
|
// Parameter ResetValue changed to capital letters.
|
| 46 |
|
|
//
|
| 47 |
|
|
// Revision 1.4 2002/02/26 16:18:08 mohor
|
| 48 |
|
|
// Reset values are passed to registers through parameters
|
| 49 |
|
|
//
|
| 50 |
|
|
// Revision 1.3 2002/01/23 10:28:16 mohor
|
| 51 |
|
|
// Link in the header changed.
|
| 52 |
|
|
//
|
| 53 |
|
|
// Revision 1.2 2001/10/19 08:43:51 mohor
|
| 54 |
|
|
// eth_timescale.v changed to timescale.v This is done because of the
|
| 55 |
|
|
// simulation of the few cores in a one joined project.
|
| 56 |
|
|
//
|
| 57 |
|
|
// Revision 1.1 2001/08/06 14:44:29 mohor
|
| 58 |
|
|
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
|
| 59 |
|
|
// Include files fixed to contain no path.
|
| 60 |
|
|
// File names and module names changed ta have a eth_ prologue in the name.
|
| 61 |
|
|
// File eth_timescale.v is used to define timescale
|
| 62 |
|
|
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
|
| 63 |
|
|
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
|
| 64 |
|
|
// and Mdo_OE. The bidirectional signal must be created on the top level. This
|
| 65 |
|
|
// is done due to the ASIC tools.
|
| 66 |
|
|
//
|
| 67 |
|
|
//
|
| 68 |
|
|
//
|
| 69 |
|
|
//
|
| 70 |
|
|
//
|
| 71 |
|
|
//
|
| 72 |
|
|
//
|
| 73 |
|
|
|
| 74 |
|
|
`include "timescale.v"
|
| 75 |
|
|
|
| 76 |
|
|
|
| 77 |
|
|
module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset);
|
| 78 |
|
|
|
| 79 |
|
|
parameter WIDTH = 8; // default parameter of the register width
|
| 80 |
|
|
parameter RESET_VALUE = 0;
|
| 81 |
|
|
|
| 82 |
|
|
input [WIDTH-1:0] DataIn;
|
| 83 |
|
|
|
| 84 |
|
|
input Write;
|
| 85 |
|
|
input Clk;
|
| 86 |
|
|
input Reset;
|
| 87 |
|
|
input SyncReset;
|
| 88 |
|
|
|
| 89 |
|
|
output [WIDTH-1:0] DataOut;
|
| 90 |
|
|
reg [WIDTH-1:0] DataOut;
|
| 91 |
|
|
|
| 92 |
|
|
|
| 93 |
|
|
|
| 94 |
|
|
always @ (posedge Clk or posedge Reset)
|
| 95 |
|
|
begin
|
| 96 |
|
|
if(Reset)
|
| 97 |
|
|
DataOut<=#1 RESET_VALUE;
|
| 98 |
|
|
else
|
| 99 |
|
|
if(SyncReset)
|
| 100 |
|
|
DataOut<=#1 RESET_VALUE;
|
| 101 |
|
|
else
|
| 102 |
|
|
if(Write) // write
|
| 103 |
|
|
DataOut<=#1 DataIn;
|
| 104 |
|
|
end
|
| 105 |
|
|
|
| 106 |
|
|
|
| 107 |
|
|
|
| 108 |
|
|
endmodule // Register
|
