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csantifort |
//////////////////////////////////////////////////////////////////
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// //
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// Wrapper for SRAM buffer module //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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`include "timescale.v"
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module eth_spram_256x32(
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//
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// Generic synchronous single-port RAM interface
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//
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input clk, // Clock, rising edge
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input rst, // Reset, active high
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input ce, // Chip enable input, active high
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input [3:0] we, // Write enable input, active high
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input oe, // Output enable input, active high
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input [7:0] addr, // address bus inputs
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input [31:0] di, // input data bus
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output [31:0] do // output data bus
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);
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wire write_enable;
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assign write_enable = ce & (|we);
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`ifdef XILINX_SPARTAN6_FPGA
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xs6_sram_256x32_byte_en
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`endif
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`ifdef XILINX_VIRTEX6_FPGA
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xv6_sram_256x32_byte_en
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`endif
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`ifndef XILINX_FPGA
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generic_sram_byte_en
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`endif
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#(
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.DATA_WIDTH ( 32 ) ,
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.ADDRESS_WIDTH ( 8 )
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) u_ram (
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.i_clk ( clk ),
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.i_write_data ( di ),
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.i_write_enable ( write_enable ),
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.i_address ( addr ),
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.i_byte_enable ( we ),
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.o_read_data ( do )
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);
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endmodule
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