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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  eth_wishbone.v                                              ////

////                                                              ////

////  This file is part of the Ethernet IP core project           ////

////  http://www.opencores.org/projects/ethmac/                   ////

////                                                              ////

////  Author(s):                                                  ////

////      - Igor Mohor (igorM@opencores.org)                      ////

////                                                              ////

////  All additional information is available in the Readme.txt   ////

////  file.                                                       ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2001, 2002 Authors                             ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.57  2005/02/21 11:35:33  igorm

// Defer indication fixed.

//

// Revision 1.56  2004/04/30 10:30:00  igorm

// Accidently deleted line put back.

//

// Revision 1.55  2004/04/26 15:26:23  igorm

// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the

//   previous update of the core.

// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.

// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER

//   register. (thanks to Mathias and Torbjorn)

// - Multicast reception was fixed. Thanks to Ulrich Gries

//

// Revision 1.54  2003/11/12 18:24:59  tadejm

// WISHBONE slave changed and tested from only 32-bit accesss to byte access.

//

// Revision 1.53  2003/10/17 07:46:17  markom

// mbist signals updated according to newest convention

//

// Revision 1.52  2003/01/30 14:51:31  mohor

// Reset has priority in some flipflops.

//

// Revision 1.51  2003/01/30 13:36:22  mohor

// A new bug (entered with previous update) fixed. When abort occured sometimes

// data transmission was blocked.

//

// Revision 1.50  2003/01/22 13:49:26  tadejm

// When control packets were received, they were ignored in some cases.

//

// Revision 1.49  2003/01/21 12:09:40  mohor

// When receiving normal data frame and RxFlow control was switched on, RXB

// interrupt was not set.

//

// Revision 1.48  2003/01/20 12:05:26  mohor

// When in full duplex, transmit was sometimes blocked. Fixed.

//

// Revision 1.47  2002/11/22 13:26:21  mohor

// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used

// anywhere. Removed.

//

// Revision 1.46  2002/11/22 01:57:06  mohor

// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort

// synchronized.

//

// Revision 1.45  2002/11/19 17:33:34  mohor

// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying

// that a frame was received because of the promiscous mode.

//

// Revision 1.44  2002/11/13 22:21:40  tadejm

// RxError is not generated when small frame reception is enabled and small

// frames are received.

//

// Revision 1.43  2002/10/18 20:53:34  mohor

// case changed to casex.

//

// Revision 1.42  2002/10/18 17:04:20  tadejm

// Changed BIST scan signals.

//

// Revision 1.41  2002/10/18 15:42:09  tadejm

// Igor added WB burst support and repaired BUG when handling TX under-run and retry.

//

// Revision 1.40  2002/10/14 16:07:02  mohor

// TxStatus is written after last access to the TX fifo is finished (in case of abort

// or retry). TxDone is fixed.

//

// Revision 1.39  2002/10/11 15:35:20  mohor

// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,

// TxDone and TxRetry are generated after the current WISHBONE access is

// finished.

//

// Revision 1.38  2002/10/10 16:29:30  mohor

// BIST added.

//

// Revision 1.37  2002/09/11 14:18:46  mohor

// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.

//

// Revision 1.36  2002/09/10 13:48:46  mohor

// Reception is possible after RxPointer is read and not after BD is read. For

// that reason RxBDReady is changed to RxReady.

// Busy_IRQ interrupt connected. When there is no RxBD ready and frame

// comes, interrupt is generated.

//

// Revision 1.35  2002/09/10 10:35:23  mohor

// Ethernet debug registers removed.

//

// Revision 1.34  2002/09/08 16:31:49  mohor

// Async reset for WB_ACK_O removed (when core was in reset, it was

// impossible to access BDs).

// RxPointers and TxPointers names changed to be more descriptive.

// TxUnderRun synchronized.

//

// Revision 1.33  2002/09/04 18:47:57  mohor

// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals

// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal

// was not used OK.

//

// Revision 1.32  2002/08/14 19:31:48  mohor

// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No

// need to multiply or devide any more.

//

// Revision 1.31  2002/07/25 18:29:01  mohor

// WriteRxDataToMemory signal changed so end of frame (when last word is

// written to fifo) is changed.

//

// Revision 1.30  2002/07/23 15:28:31  mohor

// Ram , used for BDs changed from generic_spram to eth_spram_256x32.

//

// Revision 1.29  2002/07/20 00:41:32  mohor

// ShiftEnded synchronization changed.

//

// Revision 1.28  2002/07/18 16:11:46  mohor

// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.

//

// Revision 1.27  2002/07/11 02:53:20  mohor

// RxPointer bug fixed.

//

// Revision 1.26  2002/07/10 13:12:38  mohor

// Previous bug wasn't succesfully removed. Now fixed.

//

// Revision 1.25  2002/07/09 23:53:24  mohor

// Master state machine had a bug when switching from master write to

// master read.

//

// Revision 1.24  2002/07/09 20:44:41  mohor

// m_wb_cyc_o signal released after every single transfer.

//

// Revision 1.23  2002/05/03 10:15:50  mohor

// Outputs registered. Reset changed for eth_wishbone module.

//

// Revision 1.22  2002/04/24 08:52:19  mohor

// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"

// bug fixed.

//

// Revision 1.21  2002/03/29 16:18:11  lampret

// Small typo fixed.

//

// Revision 1.20  2002/03/25 16:19:12  mohor

// Any address can be used for Tx and Rx BD pointers. Address does not need

// to be aligned.

//

// Revision 1.19  2002/03/19 12:51:50  mohor

// Comments in Slovene language removed.

//

// Revision 1.18  2002/03/19 12:46:52  mohor

// casex changed with case, fifo reset changed.

//

// Revision 1.17  2002/03/09 16:08:45  mohor

// rx_fifo was not always cleared ok. Fixed.

//

// Revision 1.16  2002/03/09 13:51:20  mohor

// Status was not latched correctly sometimes. Fixed.

//

// Revision 1.15  2002/03/08 06:56:46  mohor

// Big Endian problem when sending frames fixed.

//

// Revision 1.14  2002/03/02 19:12:40  mohor

// Byte ordering changed (Big Endian used). casex changed with case because

// Xilinx Foundation had problems. Tested in HW. It WORKS.

//

// Revision 1.13  2002/02/26 16:59:55  mohor

// Small fixes for external/internal DMA missmatches.

//

// Revision 1.12  2002/02/26 16:22:07  mohor

// Interrupts changed

//

// Revision 1.11  2002/02/15 17:07:39  mohor

// Status was not written correctly when frames were discarted because of

// address mismatch.

//

// Revision 1.10  2002/02/15 12:17:39  mohor

// RxStartFrm cleared when abort or retry comes.

//

// Revision 1.9  2002/02/15 11:59:10  mohor

// Changes that were lost when updating from 1.5 to 1.8 fixed.

//

// Revision 1.8  2002/02/14 20:54:33  billditt

// Addition  of new module eth_addrcheck.v

//

// Revision 1.7  2002/02/12 17:03:47  mohor

// RxOverRun added to statuses.

//

// Revision 1.6  2002/02/11 09:18:22  mohor

// Tx status is written back to the BD.

//

// Revision 1.5  2002/02/08 16:21:54  mohor

// Rx status is written back to the BD.

//

// Revision 1.4  2002/02/06 14:10:21  mohor

// non-DMA host interface added. Select the right configutation in eth_defines.

//

// Revision 1.3  2002/02/05 16:44:39  mohor

// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200

// MHz. Statuses, overrun, control frame transmission and reception still  need

// to be fixed.

//

// Revision 1.2  2002/02/01 12:46:51  mohor

// Tx part finished. TxStatus needs to be fixed. Pause request needs to be

// added.

//

// Revision 1.1  2002/01/23 10:47:59  mohor

// Initial version. Equals to eth_wishbonedma.v at this moment.

//

//

//

`include "eth_defines.v"

`include "timescale.v"

module eth_wishbone

   (

    // WISHBONE common

    WB_CLK_I, WB_DAT_I, WB_DAT_O,

    // WISHBONE slave

                WB_ADR_I, WB_WE_I, WB_ACK_O,

    BDCs,

    Reset,

    // WISHBONE master

    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,

    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,

    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,

`ifdef ETH_WISHBONE_B3

    m_wb_cti_o, m_wb_bte_o,

`endif

    //TX

    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,

    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,

    PerPacketPad,

    //RX

    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,

    // Register

    r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,

    // Interrupts

    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,

    // Rx Status

    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,

    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,

    ReceivedPauseFrm,

    // Tx Status

    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost

    // Bist

`ifdef ETH_BIST

    ,

    // debug chain signals

    mbist_si_i,       // bist scan serial in

    mbist_so_o,       // bist scan serial out

    mbist_ctrl_i        // bist chain shift control

`endif

                );

parameter Tp = 1;

// WISHBONE common

input           WB_CLK_I;       // WISHBONE clock

input  [31:0]   WB_DAT_I;       // WISHBONE data input

output [31:0]   WB_DAT_O;       // WISHBONE data output

// WISHBONE slave

input   [9:2]   WB_ADR_I;       // WISHBONE address input

input           WB_WE_I;        // WISHBONE write enable input

input   [3:0]   BDCs;           // Buffer descriptors are selected

output          WB_ACK_O;       // WISHBONE acknowledge output

// WISHBONE master

output  [29:0]  m_wb_adr_o;     // 

output   [3:0]  m_wb_sel_o;     // 

output          m_wb_we_o;      // 

output  [31:0]  m_wb_dat_o;     // 

output          m_wb_cyc_o;     // 

output          m_wb_stb_o;     // 

input   [31:0]  m_wb_dat_i;     // 

input           m_wb_ack_i;     // 

input           m_wb_err_i;     // 

`ifdef ETH_WISHBONE_B3

output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier

output   [1:0]  m_wb_bte_o;     // Burst Type Extension

reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier

`endif

input           Reset;       // Reset signal

// Rx Status signals

input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode

input           LatchedCrcError;  // CRC error

input           RxLateCollision;  // Late collision occured while receiving frame

input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)

input           DribbleNibble;    // Extra nibble received

input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL

input    [15:0] RxLength;         // Length of the incoming frame

input           LoadRxStatus;     // Rx status was loaded

input           ReceivedPacketGood;// Received packet's length and CRC are good

input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD

input           r_RxFlow;

input           r_PassAll;

input           ReceivedPauseFrm;

// Tx Status signals

input     [3:0] RetryCntLatched;  // Latched Retry Counter

input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)

input           LateCollLatched;  // Late collision occured

input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)

output          RstDeferLatched;

input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission

// Tx

input           MTxClk;         // Transmit clock (from PHY)

input           TxUsedData;     // Transmit packet used data

input           TxRetry;        // Transmit packet retry

input           TxAbort;        // Transmit packet abort

input           TxDone;         // Transmission ended

output          TxStartFrm;     // Transmit packet start frame

output          TxEndFrm;       // Transmit packet end frame

output  [7:0]   TxData;         // Transmit packet data byte

output          TxUnderRun;     // Transmit packet under-run

output          PerPacketCrcEn; // Per packet crc enable

output          PerPacketPad;   // Per packet pading

// Rx

input           MRxClk;         // Receive clock (from PHY)

input   [7:0]   RxData;         // Received data byte (from PHY)

input           RxValid;        // 

input           RxStartFrm;     // 

input           RxEndFrm;       // 

input           RxAbort;        // This signal is set when address doesn't match.

output          RxStatusWriteLatched_sync2;

//Register

input           r_TxEn;         // Transmit enable

input           r_RxEn;         // Receive enable

input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number

// Interrupts

output TxB_IRQ;

output TxE_IRQ;

output RxB_IRQ;

output RxE_IRQ;

output Busy_IRQ;

// Bist

`ifdef ETH_BIST

input   mbist_si_i;       // bist scan serial in

output  mbist_so_o;       // bist scan serial out

input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control

`endif

reg TxB_IRQ;

reg TxE_IRQ;

reg RxB_IRQ;

reg RxE_IRQ;

reg             TxStartFrm;

reg             TxEndFrm;

reg     [7:0]   TxData;

reg             TxUnderRun;

reg             TxUnderRun_wb;

reg             TxBDRead;

wire            TxStatusWrite;

reg     [1:0]   TxValidBytesLatched;

reg    [15:0]   TxLength;

reg    [15:0]   LatchedTxLength;

reg   [14:11]   TxStatus;

reg   [14:13]   RxStatus;

reg             TxStartFrm_wb;

reg             TxRetry_wb;

reg             TxAbort_wb;

reg             TxDone_wb;

reg             TxDone_wb_q;

reg             TxAbort_wb_q;

reg             TxRetry_wb_q;

reg             TxRetryPacket;

reg             TxRetryPacket_NotCleared;

reg             TxDonePacket;

reg             TxDonePacket_NotCleared;

reg             TxAbortPacket;

reg             TxAbortPacket_NotCleared;

reg             RxBDReady;

reg             RxReady;

reg             TxBDReady;

reg             RxBDRead;

reg    [31:0]   TxDataLatched;

reg     [1:0]   TxByteCnt;

reg             LastWord;

reg             ReadTxDataFromFifo_tck;

reg             BlockingTxStatusWrite;

reg             BlockingTxBDRead;

reg             Flop;

reg     [7:1]   TxBDAddress;

reg     [7:1]   RxBDAddress;

reg             TxRetrySync1;

reg             TxAbortSync1;

reg             TxDoneSync1;

reg             TxAbort_q;

reg             TxRetry_q;

reg             TxUsedData_q;

reg    [31:0]   RxDataLatched2;

reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering

reg     [1:0]   RxValidBytes;

reg     [1:0]   RxByteCnt;

reg             LastByteIn;

reg             ShiftWillEnd;

reg             WriteRxDataToFifo;

reg    [15:0]   LatchedRxLength;

reg             RxAbortLatched;

reg             ShiftEnded;

reg             RxOverrun;

reg     [3:0]   BDWrite;                    // BD Write Enable for access from WISHBONE side

reg             BDRead;                     // BD Read access from WISHBONE side

wire   [31:0]   RxBDDataIn;                 // Rx BD data in

wire   [31:0]   TxBDDataIn;                 // Tx BD data in

reg             TxEndFrm_wb;

wire            TxRetryPulse;

wire            TxDonePulse;

wire            TxAbortPulse;

wire            StartRxBDRead;

wire            StartTxBDRead;

wire            TxIRQEn;

wire            WrapTxStatusBit;

wire            RxIRQEn;

wire            WrapRxStatusBit;

wire    [1:0]   TxValidBytes;

wire    [7:1]   TempTxBDAddress;

wire    [7:1]   TempRxBDAddress;

wire            RxStatusWrite;

wire            RxBufferFull;

wire            RxBufferAlmostEmpty;

wire            RxBufferEmpty;

reg             WB_ACK_O;

wire    [8:0]   RxStatusIn;

reg     [8:0]   RxStatusInLatched;

reg WbEn, WbEn_q;

reg RxEn, RxEn_q;

reg TxEn, TxEn_q;

reg r_TxEn_q;

reg r_RxEn_q;

wire ram_ce;

wire [3:0]  ram_we;

wire ram_oe;

reg [7:0]   ram_addr;

reg [31:0]  ram_di;

wire [31:0] ram_do;

wire StartTxPointerRead;

reg  TxPointerRead;

reg TxEn_needed;

reg RxEn_needed;

wire StartRxPointerRead;

reg RxPointerRead;

`ifdef ETH_WISHBONE_B3

assign m_wb_bte_o = 2'b00;    // Linear burst

`endif

assign m_wb_stb_o = m_wb_cyc_o;

always @ (posedge WB_CLK_I)

begin

  WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;

end

assign WB_DAT_O = ram_do;

// Generic synchronous single-port RAM interface

eth_spram_256x32 bd_ram (

        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)

`ifdef ETH_BIST

  ,

  .mbist_si_i       (mbist_si_i),

  .mbist_so_o       (mbist_so_o),

  .mbist_ctrl_i       (mbist_ctrl_i)

`endif

);

assign ram_ce = 1'b1;

assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | {4{(TxStatusWrite | RxStatusWrite)}};

assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);

always @ (posedge WB_CLK_I or posedge Reset)

begin

  if(Reset)

    TxEn_needed <=#Tp 1'b0;

  else

  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)

    TxEn_needed <=#Tp 1'b1;

  else

  if(TxPointerRead & TxEn & TxEn_q)

    TxEn_needed <=#Tp 1'b0;

end

// Enabling access to the RAM for three devices.

always @ (posedge WB_CLK_I or posedge Reset)

begin

  if(Reset)

    begin

      WbEn <=#Tp 1'b1;

      RxEn <=#Tp 1'b0;

      TxEn <=#Tp 1'b0;

      ram_addr <=#Tp 8'h0;

      ram_di <=#Tp 32'h0;

      BDRead <=#Tp 1'b0;

      BDWrite <=#Tp 1'b0;

    end

  else

    begin

      // Switching between three stages depends on enable signals

      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case

        5'b100_10, 5'b100_11 :

          begin

            WbEn <=#Tp 1'b0;

            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled

            TxEn <=#Tp 1'b0;

            ram_addr <=#Tp {RxBDAddress, RxPointerRead};

            ram_di <=#Tp RxBDDataIn;

          end

        5'b100_01 :

          begin

            WbEn <=#Tp 1'b0;

            RxEn <=#Tp 1'b0;

            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled

            ram_addr <=#Tp {TxBDAddress, TxPointerRead};

            ram_di <=#Tp TxBDDataIn;

          end

        5'b010_00, 5'b010_10 :

          begin

            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled

            RxEn <=#Tp 1'b0;

            TxEn <=#Tp 1'b0;

            ram_addr <=#Tp WB_ADR_I[9:2];

            ram_di <=#Tp WB_DAT_I;

            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};

            BDRead <=#Tp (|BDCs) & ~WB_WE_I;

          end

        5'b010_01, 5'b010_11 :

          begin

            WbEn <=#Tp 1'b0;

            RxEn <=#Tp 1'b0;

            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled

            ram_addr <=#Tp {TxBDAddress, TxPointerRead};

            ram_di <=#Tp TxBDDataIn;

          end

        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :

          begin

            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)

            RxEn <=#Tp 1'b0;

            TxEn <=#Tp 1'b0;

            ram_addr <=#Tp WB_ADR_I[9:2];

            ram_di <=#Tp WB_DAT_I;

            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};

            BDRead <=#Tp (|BDCs) & ~WB_WE_I;

          end

        5'b100_00 :

          begin

            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit

          end

        5'b000_00 :

          begin

            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.

            RxEn <=#Tp 1'b0;

            TxEn <=#Tp 1'b0;

            ram_addr <=#Tp WB_ADR_I[9:2];

            ram_di <=#Tp WB_DAT_I;

            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};

            BDRead <=#Tp (|BDCs) & ~WB_WE_I;

          end

      endcase

    end

end

// Delayed stage signals

always @ (posedge WB_CLK_I or posedge Reset)

begin

  if(Reset)

    begin

      WbEn_q <=#Tp 1'b0;

      RxEn_q <=#Tp 1'b0;

      TxEn_q <=#Tp 1'b0;

      r_TxEn_q <=#Tp 1'b0;

      r_RxEn_q <=#Tp 1'b0;

    end

  else

    begin

      WbEn_q <=#Tp WbEn;

      RxEn_q <=#Tp RxEn;

      TxEn_q <=#Tp TxEn;

      r_TxEn_q <=#Tp r_TxEn;

      r_RxEn_q <=#Tp r_RxEn;

    end

end

// Changes for tx occur every second clock. Flop is used for this manner.

always @ (posedge MTxClk or posedge Reset)

begin

  if(Reset)

    Flop <=#Tp 1'b0;

  else

  if(TxDone | TxAbort | TxRetry_q)

    Flop <=#Tp 1'b0;

  else

  if(TxUsedData)

    Flop <=#Tp ~Flop;

end

wire ResetTxBDReady;

assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;

// Latching READY status of the Tx buffer descriptor

always @ (posedge WB_CLK_I or posedge Reset)

begin

  if(Reset)

    TxBDReady <=#Tp 1'b0;

  else

  if(TxEn & TxEn_q & TxBDRead)

    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.

  else                                                // Only packets larger then 4 bytes are transmitted.

  if(ResetTxBDReady)

    TxBDReady <=#Tp 1'b0;