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[/] [amber/] [trunk/] [hw/] [vlog/] [lib/] [generic_sram_line_en.v] - Blame information for rev 88

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//////////////////////////////////////////////////////////////////
//                                                              //
//  Generic Library SRAM with single write enable               //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Configurable depth and width.                               //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
 
module generic_sram_line_en
#(
parameter DATA_WIDTH            = 128,
parameter ADDRESS_WIDTH         = 7,
parameter INITIALIZE_TO_ZERO    = 0
)
 
(
input                           i_clk,
input      [DATA_WIDTH-1:0]     i_write_data,
input                           i_write_enable,
input      [ADDRESS_WIDTH-1:0]  i_address,
output reg [DATA_WIDTH-1:0]     o_read_data
);
 
reg [DATA_WIDTH-1:0]   mem  [0:2**ADDRESS_WIDTH-1];
 
generate
if ( INITIALIZE_TO_ZERO ) begin : init0
integer i;
initial
    begin
    for (i=0;i<2**ADDRESS_WIDTH;i=i+1)
        mem[i] <= 'd0;
    end
end
endgenerate
 
 
always @(posedge i_clk)
    begin
    // read
    o_read_data <= i_write_enable ? {DATA_WIDTH{1'd0}} : mem[i_address];
 
    // write
    if (i_write_enable)
        mem[i_address] <= i_write_data;
    end
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	2	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Generic Library SRAM with single write enable //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Configurable depth and width. //`
10			`// //`
11			`// Author(s): //`
12			`// - Conor Santifort, csantifort.amber@gmail.com //`
13			`// //`
14			`//////////////////////////////////////////////////////////////////`
15			`// //`
16			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
17			`// //`
18			`// This source file may be used and distributed without //`
19			`// restriction provided that this copyright statement is not //`
20			`// removed from the file and that any derivative work contains //`
21			`// the original copyright notice and the associated disclaimer. //`
22			`// //`
23			`// This source file is free software; you can redistribute it //`
24			`// and/or modify it under the terms of the GNU Lesser General //`
25			`// Public License as published by the Free Software Foundation; //`
26			`// either version 2.1 of the License, or (at your option) any //`
27			`// later version. //`
28			`// //`
29			`// This source is distributed in the hope that it will be //`
30			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
31			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
32			`// PURPOSE. See the GNU Lesser General Public License for more //`
33			`// details. //`
34			`// //`
35			`// You should have received a copy of the GNU Lesser General //`
36			`// Public License along with this source; if not, download it //`
37			`// from http://www.opencores.org/lgpl.shtml //`
38			`// //`
39			`//////////////////////////////////////////////////////////////////`
40
41
42			`module generic_sram_line_en`
43			`#(`
44			`parameter DATA_WIDTH = 128,`
45			`parameter ADDRESS_WIDTH = 7,`
46			`parameter INITIALIZE_TO_ZERO = 0`
47			`)`
48
49			`(`
50			`input i_clk,`
51			`input [DATA_WIDTH-1:0] i_write_data,`
52			`input i_write_enable,`
53			`input [ADDRESS_WIDTH-1:0] i_address,`
54			`output reg [DATA_WIDTH-1:0] o_read_data`
55			`);`
56
57			`reg [DATA_WIDTH-1:0] mem [0:2**ADDRESS_WIDTH-1];`
58
59			`generate`
60			`if ( INITIALIZE_TO_ZERO ) begin : init0`
61			`integer i;`
62			`initial`
63			`begin`
64			`for (i=0;i<2**ADDRESS_WIDTH;i=i+1)`
65			`mem[i] <= 'd0;`
66			`end`
67			`end`
68			`endgenerate`
69
70
71			`always @(posedge i_clk)`
72			`begin`
73			`// read`
74			`o_read_data <= i_write_enable ? {DATA_WIDTH{1'd0}} : mem[i_address];`
75
76			`// write`
77			`if (i_write_enable)`
78			`mem[i_address] <= i_write_data;`
79			`end`
80
81
82
83			`endmodule`
84

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[/] [amber/] [trunk/] [hw/] [vlog/] [lib/] [generic_sram_line_en.v] - Blame information for rev 88