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//////////////////////////////////////////////////////////////////
//                                                              //
//  Wrapper for Xilinx Spartan-6 DSP48 Block                    //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  DSP block configured as an N-bit adder and substractor      //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
 
module xs6_addsub_n #(
parameter WIDTH=32
)(
input [WIDTH-1:0]   i_a,
input [WIDTH-1:0]   i_b,
input               i_cin,
input               i_sub,
 
output [WIDTH-1:0]  o_sum,
output              o_co
);
 
 
wire [7:0]  opmode;
wire [47:0] in_a, in_b;
wire [47:0] out;
 
assign opmode = {i_sub, 1'd0, i_cin, 1'd0, 2'd3, 2'd3 };
assign in_a   = {{48-WIDTH{1'd0}}, i_a};
assign in_b   = {{48-WIDTH{1'd0}}, i_b};
assign o_sum  = out[WIDTH-1:0];
assign o_co   = out[WIDTH];
 
 
DSP48A1  #(
    // Enable registers
    .A1REG          ( 0         ),
    .B0REG          ( 0         ),
    .B1REG          ( 0         ),
    .CARRYINREG     ( 0         ),
    .CARRYOUTREG    ( 0         ),
    .CREG           ( 0         ),
    .DREG           ( 0         ),
    .MREG           ( 0         ),
    .OPMODEREG      ( 0         ),
    .PREG           ( 0         ),
    .CARRYINSEL     ("OPMODE5"  ),
    .RSTTYPE        ( "SYNC"    )
)
 
u_dsp48 (
    // Outputs
    .BCOUT         (                        ),
    .CARRYOUT      (                        ),
    .CARRYOUTF     (                        ),
    .M             (                        ),
    .P             ( out                    ),
    .PCOUT         (                        ),
 
    // Inputs
    .CLK           ( 1'd0                   ),
 
    .A             (         in_b[35:18]    ),
    .B             (         in_b[17:00]    ),
    .C             (         in_a           ),
    .D             ( {6'd0,  in_b[47:36]}   ),
 
    .CARRYIN       ( 1'd0                   ),  // uses opmode bit 5 for carry in
    .OPMODE        ( opmode                 ),
    .PCIN          ( 48'd0                  ),
 
    // Clock enables
    .CEA           ( 1'd1                   ),
    .CEB           ( 1'd1                   ),
    .CEC           ( 1'd1                   ),
    .CED           ( 1'd1                   ),
    .CEM           ( 1'd1                   ),
    .CEP           ( 1'd1                   ),
    .CECARRYIN     ( 1'd1                   ),
    .CEOPMODE      ( 1'd1                   ),
 
    // Register Resets
    .RSTA          ( 1'd0                   ),
    .RSTB          ( 1'd0                   ),
    .RSTC          ( 1'd0                   ),
    .RSTCARRYIN    ( 1'd0                   ),
    .RSTD          ( 1'd0                   ),
    .RSTM          ( 1'd0                   ),
    .RSTOPMODE     ( 1'd0                   ),
    .RSTP          ( 1'd0                   )
    );
 
 
endmodule

Line No.	Rev	Author	Line
1	2	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Wrapper for Xilinx Spartan-6 DSP48 Block //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// DSP block configured as an N-bit adder and substractor //`
10			`// //`
11			`// Author(s): //`
12			`// - Conor Santifort, csantifort.amber@gmail.com //`
13			`// //`
14			`//////////////////////////////////////////////////////////////////`
15			`// //`
16			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
17			`// //`
18			`// This source file may be used and distributed without //`
19			`// restriction provided that this copyright statement is not //`
20			`// removed from the file and that any derivative work contains //`
21			`// the original copyright notice and the associated disclaimer. //`
22			`// //`
23			`// This source file is free software; you can redistribute it //`
24			`// and/or modify it under the terms of the GNU Lesser General //`
25			`// Public License as published by the Free Software Foundation; //`
26			`// either version 2.1 of the License, or (at your option) any //`
27			`// later version. //`
28			`// //`
29			`// This source is distributed in the hope that it will be //`
30			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
31			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
32			`// PURPOSE. See the GNU Lesser General Public License for more //`
33			`// details. //`
34			`// //`
35			`// You should have received a copy of the GNU Lesser General //`
36			`// Public License along with this source; if not, download it //`
37			`// from http://www.opencores.org/lgpl.shtml //`
38			`// //`
39			`//////////////////////////////////////////////////////////////////`
40
41
42			`module xs6_addsub_n #(`
43			`parameter WIDTH=32`
44			`)(`
45			`input [WIDTH-1:0] i_a,`
46			`input [WIDTH-1:0] i_b,`
47			`input i_cin,`
48			`input i_sub,`
49
50			`output [WIDTH-1:0] o_sum,`
51			`output o_co`
52			`);`
53
54
55			`wire [7:0] opmode;`
56			`wire [47:0] in_a, in_b;`
57			`wire [47:0] out;`
58
59			`assign opmode = {i_sub, 1'd0, i_cin, 1'd0, 2'd3, 2'd3 };`
60			`assign in_a = {{48-WIDTH{1'd0}}, i_a};`
61			`assign in_b = {{48-WIDTH{1'd0}}, i_b};`
62			`assign o_sum = out[WIDTH-1:0];`
63			`assign o_co = out[WIDTH];`
64
65
66			`DSP48A1 #(`
67			`// Enable registers`
68			`.A1REG ( 0 ),`
69			`.B0REG ( 0 ),`
70			`.B1REG ( 0 ),`
71			`.CARRYINREG ( 0 ),`
72			`.CARRYOUTREG ( 0 ),`
73			`.CREG ( 0 ),`
74			`.DREG ( 0 ),`
75			`.MREG ( 0 ),`
76			`.OPMODEREG ( 0 ),`
77			`.PREG ( 0 ),`
78			`.CARRYINSEL ("OPMODE5" ),`
79			`.RSTTYPE ( "SYNC" )`
80			`)`
81
82			`u_dsp48 (`
83			`// Outputs`
84			`.BCOUT ( ),`
85			`.CARRYOUT ( ),`
86			`.CARRYOUTF ( ),`
87			`.M ( ),`
88			`.P ( out ),`
89			`.PCOUT ( ),`
90
91			`// Inputs`
92			`.CLK ( 1'd0 ),`
93
94			`.A ( in_b[35:18] ),`
95			`.B ( in_b[17:00] ),`
96			`.C ( in_a ),`
97			`.D ( {6'd0, in_b[47:36]} ),`
98
99			`.CARRYIN ( 1'd0 ), // uses opmode bit 5 for carry in`
100			`.OPMODE ( opmode ),`
101			`.PCIN ( 48'd0 ),`
102
103			`// Clock enables`
104			`.CEA ( 1'd1 ),`
105			`.CEB ( 1'd1 ),`
106			`.CEC ( 1'd1 ),`
107			`.CED ( 1'd1 ),`
108			`.CEM ( 1'd1 ),`
109			`.CEP ( 1'd1 ),`
110			`.CECARRYIN ( 1'd1 ),`
111			`.CEOPMODE ( 1'd1 ),`
112
113			`// Register Resets`
114			`.RSTA ( 1'd0 ),`
115			`.RSTB ( 1'd0 ),`
116			`.RSTC ( 1'd0 ),`
117			`.RSTCARRYIN ( 1'd0 ),`
118			`.RSTD ( 1'd0 ),`
119			`.RSTM ( 1'd0 ),`
120			`.RSTOPMODE ( 1'd0 ),`
121			`.RSTP ( 1'd0 )`
122			`);`
123
124
125			`endmodule`

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[/] [amber/] [trunk/] [hw/] [vlog/] [lib/] [xs6_addsub_n.v] - Blame information for rev 2