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csantifort |
//////////////////////////////////////////////////////////////////
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// //
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// Generic Asynchronous FIFO //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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module afifo
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#(
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parameter D_WIDTH = 32
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)
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(
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input wr_clk,
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input rd_clk,
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input [D_WIDTH-1:0] i_data,
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output [D_WIDTH-1:0] o_data,
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input i_push,
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input i_pop,
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output o_full,
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output o_empty
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);
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reg [2:0] wr_pointer = 'd0, rd_pointer = 'd0;
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reg [2:0] wr_pointer_d1 = 'd0, rd_pointer_d1 = 'd0;
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reg [2:0] wr_pointer_d2 = 'd0, rd_pointer_d2 = 'd0;
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wire [2:0] wr_pointer_rd, rd_pointer_wr;
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reg [D_WIDTH-1:0] data [3:0];
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always @( posedge wr_clk )
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if ( i_push && !o_full )
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begin
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wr_pointer <= wr_pointer + 1'd1;
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data[wr_pointer[1:0]] <= i_data;
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end
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always @( posedge wr_clk )
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begin
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rd_pointer_d1 <= gray8(rd_pointer);
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rd_pointer_d2 <= rd_pointer_d1;
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end
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always @( posedge rd_clk )
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if ( i_pop && !o_empty )
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rd_pointer <= rd_pointer + 1'd1;
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always @( posedge rd_clk )
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begin
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wr_pointer_d1 <= gray8(wr_pointer);
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wr_pointer_d2 <= wr_pointer_d1;
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end
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assign wr_pointer_rd = ungray8(wr_pointer_d2);
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assign rd_pointer_wr = ungray8(rd_pointer_d2);
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assign o_data = data[rd_pointer[1:0]];
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assign o_full = {~wr_pointer[2], wr_pointer[1:0]} == rd_pointer_wr;
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assign o_empty = wr_pointer_rd == rd_pointer;
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function [2:0] gray8;
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input [2:0] binary;
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begin
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case(binary)
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3'b000 : gray8 = 3'b000;
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3'b001 : gray8 = 3'b001;
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3'b010 : gray8 = 3'b011;
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3'b011 : gray8 = 3'b010;
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3'b100 : gray8 = 3'b110;
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3'b101 : gray8 = 3'b111;
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3'b110 : gray8 = 3'b101;
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3'b111 : gray8 = 3'b100;
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endcase
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end
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endfunction
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function [2:0] ungray8;
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input [2:0] gray;
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begin
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case(gray)
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3'b000 : ungray8 = 3'b000;
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3'b001 : ungray8 = 3'b001;
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3'b011 : ungray8 = 3'b010;
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3'b010 : ungray8 = 3'b011;
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3'b110 : ungray8 = 3'b100;
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3'b111 : ungray8 = 3'b101;
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3'b101 : ungray8 = 3'b110;
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3'b100 : ungray8 = 3'b111;
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endcase
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end
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endfunction
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endmodule
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