OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [afifo.v] - Blame information for rev 79

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  Generic Asynchronous FIFO                                   //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//                                                              //
10
//  Author(s):                                                  //
11
//      - Conor Santifort, csantifort.amber@gmail.com           //
12
//                                                              //
13
//////////////////////////////////////////////////////////////////
14
//                                                              //
15
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
16
//                                                              //
17
// This source file may be used and distributed without         //
18
// restriction provided that this copyright statement is not    //
19
// removed from the file and that any derivative work contains  //
20
// the original copyright notice and the associated disclaimer. //
21
//                                                              //
22
// This source file is free software; you can redistribute it   //
23
// and/or modify it under the terms of the GNU Lesser General   //
24
// Public License as published by the Free Software Foundation; //
25
// either version 2.1 of the License, or (at your option) any   //
26
// later version.                                               //
27
//                                                              //
28
// This source is distributed in the hope that it will be       //
29
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
30
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
31
// PURPOSE.  See the GNU Lesser General Public License for more //
32
// details.                                                     //
33
//                                                              //
34
// You should have received a copy of the GNU Lesser General    //
35
// Public License along with this source; if not, download it   //
36
// from http://www.opencores.org/lgpl.shtml                     //
37
//                                                              //
38
//////////////////////////////////////////////////////////////////
39
 
40
 
41
module afifo
42
#(
43
parameter D_WIDTH = 32
44
)
45
(
46
input                       wr_clk,
47
input                       rd_clk,
48
 
49
input   [D_WIDTH-1:0]       i_data,
50
output  [D_WIDTH-1:0]       o_data,
51
input                       i_push,
52
input                       i_pop,
53
 
54
output                      o_full,
55
output                      o_empty
56
);
57
 
58
reg  [2:0] wr_pointer = 'd0, rd_pointer = 'd0;
59
reg  [2:0] wr_pointer_d1 = 'd0, rd_pointer_d1 = 'd0;
60
reg  [2:0] wr_pointer_d2 = 'd0, rd_pointer_d2 = 'd0;
61
wire [2:0] wr_pointer_rd, rd_pointer_wr;
62
 
63
 
64
reg [D_WIDTH-1:0] data [3:0];
65
 
66
 
67
always @( posedge wr_clk )
68
    if ( i_push && !o_full )
69
        begin
70
        wr_pointer <= wr_pointer + 1'd1;
71
        data[wr_pointer[1:0]] <= i_data;
72
        end
73
 
74
 
75
always @( posedge wr_clk )
76
    begin
77
    rd_pointer_d1 <= gray8(rd_pointer);
78
    rd_pointer_d2 <= rd_pointer_d1;
79
    end
80
 
81
 
82
always @( posedge rd_clk )
83
    if ( i_pop && !o_empty )
84
        rd_pointer <= rd_pointer + 1'd1;
85
 
86
 
87
always @( posedge rd_clk )
88
    begin
89
    wr_pointer_d1 <= gray8(wr_pointer);
90
    wr_pointer_d2 <= wr_pointer_d1;
91
    end
92
 
93
 
94
assign wr_pointer_rd = ungray8(wr_pointer_d2);
95
assign rd_pointer_wr = ungray8(rd_pointer_d2);
96
 
97
assign o_data  = data[rd_pointer[1:0]];
98
assign o_full  = {~wr_pointer[2], wr_pointer[1:0]} == rd_pointer_wr;
99
assign o_empty = wr_pointer_rd == rd_pointer;
100
 
101
 
102
function [2:0] gray8;
103
input [2:0] binary;
104
begin
105
    case(binary)
106
        3'b000 : gray8 = 3'b000;
107
        3'b001 : gray8 = 3'b001;
108
        3'b010 : gray8 = 3'b011;
109
        3'b011 : gray8 = 3'b010;
110
        3'b100 : gray8 = 3'b110;
111
        3'b101 : gray8 = 3'b111;
112
        3'b110 : gray8 = 3'b101;
113
        3'b111 : gray8 = 3'b100;
114
    endcase
115
end
116
endfunction
117
 
118
 
119
function [2:0] ungray8;
120
input [2:0] gray;
121
begin
122
    case(gray)
123
        3'b000 : ungray8 = 3'b000;
124
        3'b001 : ungray8 = 3'b001;
125
        3'b011 : ungray8 = 3'b010;
126
        3'b010 : ungray8 = 3'b011;
127
        3'b110 : ungray8 = 3'b100;
128
        3'b111 : ungray8 = 3'b101;
129
        3'b101 : ungray8 = 3'b110;
130
        3'b100 : ungray8 = 3'b111;
131
    endcase
132
end
133
endfunction
134
 
135
endmodule
136
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.