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[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [boot_mem128.v] - Blame information for rev 49

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1 2 csantifort
//////////////////////////////////////////////////////////////////
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//                                                              //
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//  8KBytes SRAM configured with boot software                  //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Holds just enough software to get the system going.         //
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//  The boot loader fits into this 8KB embedded SRAM on the     //
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//  FPGA and enables it to load large applications via the      //
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//  serial port (UART) into the DDR3 memory                     //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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45 36 csantifort
module boot_mem128 #(
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parameter WB_DWIDTH   = 128,
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parameter WB_SWIDTH   = 16,
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parameter MADDR_WIDTH = 9
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)(
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input                       i_wb_clk,     // WISHBONE clock
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input       [31:0]          i_wb_adr,
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input       [WB_SWIDTH-1:0] i_wb_sel,
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input                       i_wb_we,
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output      [WB_DWIDTH-1:0] o_wb_dat,
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input       [WB_DWIDTH-1:0] i_wb_dat,
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input                       i_wb_cyc,
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input                       i_wb_stb,
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output                      o_wb_ack,
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output                      o_wb_err
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);
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wire                    start_write;
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wire                    start_read;
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wire [WB_DWIDTH-1:0]    read_data;
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wire [WB_DWIDTH-1:0]    write_data;
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wire [WB_SWIDTH-1:0]    byte_enable;
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wire [MADDR_WIDTH-1:0]  address;
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`ifdef AMBER_WISHBONE_DEBUG
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    reg  [7:0]              jitter_r = 8'h0f;
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    reg  [1:0]              start_read_r = 'd0;
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`else
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    reg                     start_read_r = 'd0;
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`endif
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// Can't start a write while a read is completing. The ack for the read cycle
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// needs to be sent first
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`ifdef AMBER_WISHBONE_DEBUG
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    assign start_write = i_wb_stb &&  i_wb_we && !(|start_read_r) && jitter_r[0];
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`else
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    assign start_write = i_wb_stb &&  i_wb_we && !(|start_read_r);
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`endif
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assign start_read  = i_wb_stb && !i_wb_we && !(|start_read_r);
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`ifdef AMBER_WISHBONE_DEBUG
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    always @( posedge i_wb_clk )
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        jitter_r <= {jitter_r[6:0], jitter_r[7] ^ jitter_r[4] ^ jitter_r[1]};
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    always @( posedge i_wb_clk )
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        if (start_read)
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            start_read_r <= {3'd0, start_read};
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        else if (o_wb_ack)
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            start_read_r <= 'd0;
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        else
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            start_read_r <= {start_read_r[2:0], start_read};
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`else
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    always @( posedge i_wb_clk )
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        start_read_r <= start_read;
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`endif
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assign o_wb_err = 1'd0;
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assign write_data  = i_wb_dat;
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assign byte_enable = i_wb_sel;
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assign o_wb_dat    = read_data;
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assign address     = i_wb_adr[MADDR_WIDTH+3:4];
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`ifdef AMBER_WISHBONE_DEBUG
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    assign o_wb_ack    = i_wb_stb && ( start_write || start_read_r[jitter_r[1]] );
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`else
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    assign o_wb_ack    = i_wb_stb && ( start_write || start_read_r );
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`endif
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// ------------------------------------------------------
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// Instantiate SRAMs
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// ------------------------------------------------------
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//         
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`ifdef XILINX_FPGA
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    `ifdef XILINX_SPARTAN6_FPGA
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        xs6_sram_512x128_byte_en
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    `endif
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    `ifdef XILINX_VIRTEX6_FPGA
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        xv6_sram_512x128_byte_en
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    `endif
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#(
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// This file holds a software image used for FPGA simulations
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// This pre-processor syntax works with both the simulator
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// and ISE, which I couldn't get to work with giving it the
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// file name as a define.
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`ifdef BOOT_MEM_PARAMS_FILE
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    `include `BOOT_MEM_PARAMS_FILE
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`else
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    // default file
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    `include "boot-loader_memparams128.v"
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`endif
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)
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`endif
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`ifndef XILINX_FPGA
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generic_sram_byte_en
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#(
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    .DATA_WIDTH     ( WB_DWIDTH         ),
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    .ADDRESS_WIDTH  ( MADDR_WIDTH       )
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)
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`endif
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u_mem (
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    .i_clk          ( i_wb_clk          ),
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    .i_write_enable ( start_write       ),
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    .i_byte_enable  ( byte_enable       ),
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    .i_address      ( address           ),  // 2048 words, 32 bits
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    .o_read_data    ( read_data         ),
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    .i_write_data   ( write_data        )
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);
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// =======================================================================================
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// =======================================================================================
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// =======================================================================================
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// Non-synthesizable debug code
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// =======================================================================================
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//synopsys translate_off
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`ifdef XILINX_SPARTAN6_FPGA
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    `ifdef BOOT_MEM_PARAMS_FILE
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        initial
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            $display("Boot mem file is %s", `BOOT_MEM_PARAMS_FILE );
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    `endif
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`endif
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//synopsys translate_on
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endmodule
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