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[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [boot_mem32.v] - Blame information for rev 50

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//////////////////////////////////////////////////////////////////
//                                                              //
//  8KBytes SRAM configured with boot software                  //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Holds just enough software to get the system going.         //
//  The boot loader fits into this 8KB embedded SRAM on the     //
//  FPGA and enables it to load large applications via the      //
//  serial port (UART) into the DDR3 memory                     //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
 
module boot_mem32 #(
parameter WB_DWIDTH   = 32,
parameter WB_SWIDTH   = 4,
parameter MADDR_WIDTH = 11
)(
input                       i_wb_clk,     // WISHBONE clock
 
input       [31:0]          i_wb_adr,
input       [WB_SWIDTH-1:0] i_wb_sel,
input                       i_wb_we,
output      [WB_DWIDTH-1:0] o_wb_dat,
input       [WB_DWIDTH-1:0] i_wb_dat,
input                       i_wb_cyc,
input                       i_wb_stb,
output                      o_wb_ack,
output                      o_wb_err
 
);
 
wire                    start_write;
wire                    start_read;
`ifdef AMBER_WISHBONE_DEBUG
    reg  [7:0]              jitter_r = 8'h0f;
    reg  [1:0]              start_read_r = 'd0;
`else
    reg                     start_read_r = 'd0;
`endif
wire [WB_DWIDTH-1:0]    read_data;
wire [WB_DWIDTH-1:0]    write_data;
wire [WB_SWIDTH-1:0]    byte_enable;
wire [MADDR_WIDTH-1:0]  address;
 
 
// Can't start a write while a read is completing. The ack for the read cycle
// needs to be sent first
`ifdef AMBER_WISHBONE_DEBUG
    assign start_write = i_wb_stb &&  i_wb_we && !(|start_read_r) && jitter_r[0];
`else
    assign start_write = i_wb_stb &&  i_wb_we && !(|start_read_r);
`endif
assign start_read  = i_wb_stb && !i_wb_we && !start_read_r;
 
 
`ifdef AMBER_WISHBONE_DEBUG
    always @( posedge i_wb_clk )
        jitter_r <= {jitter_r[6:0], jitter_r[7] ^ jitter_r[4] ^ jitter_r[1]};
 
    always @( posedge i_wb_clk )
        if (start_read)
            start_read_r <= {3'd0, start_read};
        else if (o_wb_ack)
            start_read_r <= 'd0;
        else
            start_read_r <= {start_read_r[2:0], start_read};
`else
    always @( posedge i_wb_clk )
        start_read_r <= start_read;
`endif
 
assign o_wb_err = 1'd0;
 
assign write_data  = i_wb_dat;
assign byte_enable = i_wb_sel;
assign o_wb_dat    = read_data;
assign address     = i_wb_adr[MADDR_WIDTH+1:2];
 
`ifdef AMBER_WISHBONE_DEBUG
    assign o_wb_ack    = i_wb_stb && ( start_write || start_read_r[jitter_r[1]] );
`else
    assign o_wb_ack    = i_wb_stb && ( start_write || start_read_r );
`endif
 
// ------------------------------------------------------
// Instantiate SRAMs
// ------------------------------------------------------
//         
`ifdef XILINX_FPGA
 
    `ifdef XILINX_SPARTAN6_FPGA
        xs6_sram_2048x32_byte_en
    `endif
    `ifdef XILINX_VIRTEX6_FPGA
        xv6_sram_2048x32_byte_en
    `endif
 
#(
// This file holds a software image used for FPGA simulations
// This pre-processor syntax works with both the simulator
// and ISE, which I couldn't get to work with giving it the
// file name as a define.
 
`ifdef BOOT_MEM_PARAMS_FILE
    `include `BOOT_MEM_PARAMS_FILE
`else
    // default file
    `include "boot-loader_memparams32.v"
`endif
 
)
`endif
 
`ifndef XILINX_FPGA
generic_sram_byte_en
#(
    .DATA_WIDTH     ( WB_DWIDTH             ),
    .ADDRESS_WIDTH  ( MADDR_WIDTH           )
)
`endif
u_mem (
    .i_clk          ( i_wb_clk             ),
    .i_write_enable ( start_write          ),
    .i_byte_enable  ( byte_enable          ),
    .i_address      ( address              ),  // 2048 words, 32 bits
    .o_read_data    ( read_data            ),
    .i_write_data   ( write_data           )
);
 
 
// =======================================================================================
// =======================================================================================
// =======================================================================================
// Non-synthesizable debug code
// =======================================================================================
 
 
//synopsys translate_off
`ifdef XILINX_SPARTAN6_FPGA
    `ifdef BOOT_MEM_PARAMS_FILE
        initial
            $display("Boot mem file is %s", `BOOT_MEM_PARAMS_FILE );
    `endif
`endif
//synopsys translate_on
 
endmodule
 
 

Line No.	Rev	Author	Line
1	2	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// 8KBytes SRAM configured with boot software //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Holds just enough software to get the system going. //`
10			`// The boot loader fits into this 8KB embedded SRAM on the //`
11			`// FPGA and enables it to load large applications via the //`
12			`// serial port (UART) into the DDR3 memory //`
13			`// //`
14			`// Author(s): //`
15			`// - Conor Santifort, csantifort.amber@gmail.com //`
16			`// //`
17			`//////////////////////////////////////////////////////////////////`
18			`// //`
19			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
20			`// //`
21			`// This source file may be used and distributed without //`
22			`// restriction provided that this copyright statement is not //`
23			`// removed from the file and that any derivative work contains //`
24			`// the original copyright notice and the associated disclaimer. //`
25			`// //`
26			`// This source file is free software; you can redistribute it //`
27			`// and/or modify it under the terms of the GNU Lesser General //`
28			`// Public License as published by the Free Software Foundation; //`
29			`// either version 2.1 of the License, or (at your option) any //`
30			`// later version. //`
31			`// //`
32			`// This source is distributed in the hope that it will be //`
33			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
34			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
35			`// PURPOSE. See the GNU Lesser General Public License for more //`
36			`// details. //`
37			`// //`
38			`// You should have received a copy of the GNU Lesser General //`
39			`// Public License along with this source; if not, download it //`
40			`// from http://www.opencores.org/lgpl.shtml //`
41			`// //`
42			`//////////////////////////////////////////////////////////////////`
43
44
45	36	csantifort	`module boot_mem32 #(`
46			`parameter WB_DWIDTH = 32,`
47			`parameter WB_SWIDTH = 4,`
48			`parameter MADDR_WIDTH = 11`
49	35	csantifort	`)(`
50	2	csantifort	`input i_wb_clk, // WISHBONE clock`
51
52			`input [31:0] i_wb_adr,`
53	35	csantifort	`input [WB_SWIDTH-1:0] i_wb_sel,`
54	2	csantifort	`input i_wb_we,`
55	35	csantifort	`output [WB_DWIDTH-1:0] o_wb_dat,`
56			`input [WB_DWIDTH-1:0] i_wb_dat,`
57	2	csantifort	`input i_wb_cyc,`
58			`input i_wb_stb,`
59			`output o_wb_ack,`
60			`output o_wb_err`
61
62			`);`
63
64	36	csantifort	`wire start_write;`
65			`wire start_read;`
66	40	csantifort	`ifdef AMBER_WISHBONE_DEBUG
67			`reg [7:0] jitter_r = 8'h0f;`
68			`reg [1:0] start_read_r = 'd0;`
69			`else
70			`reg start_read_r = 'd0;`
71			`endif
72	36	csantifort	`wire [WB_DWIDTH-1:0] read_data;`
73			`wire [WB_DWIDTH-1:0] write_data;`
74			`wire [WB_SWIDTH-1:0] byte_enable;`
75			`wire [MADDR_WIDTH-1:0] address;`
76	2	csantifort
77	35	csantifort
78	2	csantifort	`// Can't start a write while a read is completing. The ack for the read cycle`
79			`// needs to be sent first`
80	40	csantifort	`ifdef AMBER_WISHBONE_DEBUG
81			`assign start_write = i_wb_stb && i_wb_we && !(\|start_read_r) && jitter_r[0];`
82			`else
83			`assign start_write = i_wb_stb && i_wb_we && !(\|start_read_r);`
84			`endif
85	36	csantifort	`assign start_read = i_wb_stb && !i_wb_we && !start_read_r;`
86	2	csantifort
87
88	40	csantifort	`ifdef AMBER_WISHBONE_DEBUG
89			`always @( posedge i_wb_clk )`
90			`jitter_r <= {jitter_r[6:0], jitter_r[7] ^ jitter_r[4] ^ jitter_r[1]};`
91
92			`always @( posedge i_wb_clk )`
93			`if (start_read)`
94			`start_read_r <= {3'd0, start_read};`
95			`else if (o_wb_ack)`
96			`start_read_r <= 'd0;`
97			`else`
98			`start_read_r <= {start_read_r[2:0], start_read};`
99			`else
100			`always @( posedge i_wb_clk )`
101			`start_read_r <= start_read;`
102			`endif
103	2	csantifort
104			`assign o_wb_err = 1'd0;`
105
106	36	csantifort	`assign write_data = i_wb_dat;`
107			`assign byte_enable = i_wb_sel;`
108			`assign o_wb_dat = read_data;`
109			`assign address = i_wb_adr[MADDR_WIDTH+1:2];`
110	35	csantifort
111	40	csantifort	`ifdef AMBER_WISHBONE_DEBUG
112			`assign o_wb_ack = i_wb_stb && ( start_write \|\| start_read_r[jitter_r[1]] );`
113			`else
114			`assign o_wb_ack = i_wb_stb && ( start_write \|\| start_read_r );`
115			`endif
116
117	2	csantifort	`// ------------------------------------------------------`
118			`// Instantiate SRAMs`
119			`// ------------------------------------------------------`
120			`//`
121			`ifdef XILINX_FPGA
122
123			`ifdef XILINX_SPARTAN6_FPGA
124			`xs6_sram_2048x32_byte_en`
125			`endif
126			`ifdef XILINX_VIRTEX6_FPGA
127			`xv6_sram_2048x32_byte_en`
128			`endif
129
130			`#(`
131			`// This file holds a software image used for FPGA simulations`
132			`// This pre-processor syntax works with both the simulator`
133			`// and ISE, which I couldn't get to work with giving it the`
134			`// file name as a define.`
135
136			`ifdef BOOT_MEM_PARAMS_FILE
137			`include `BOOT_MEM_PARAMS_FILE
138			`else
139			`// default file`
140	36	csantifort	`include "boot-loader_memparams32.v"
141	2	csantifort	`endif
142
143			`)`
144			`endif
145
146			`ifndef XILINX_FPGA
147			`generic_sram_byte_en`
148			`#(`
149	36	csantifort	`.DATA_WIDTH ( WB_DWIDTH ),`
150			`.ADDRESS_WIDTH ( MADDR_WIDTH )`
151	2	csantifort	`)`
152			`endif
153			`u_mem (`
154			`.i_clk ( i_wb_clk ),`
155			`.i_write_enable ( start_write ),`
156	35	csantifort	`.i_byte_enable ( byte_enable ),`
157			`.i_address ( address ), // 2048 words, 32 bits`
158			`.o_read_data ( read_data ),`
159			`.i_write_data ( write_data )`
160	2	csantifort	`);`
161
162
163			`// =======================================================================================`
164			`// =======================================================================================`
165			`// =======================================================================================`
166			`// Non-synthesizable debug code`
167			`// =======================================================================================`
168
169
170			`//synopsys translate_off`
171			`ifdef XILINX_SPARTAN6_FPGA
172			`ifdef BOOT_MEM_PARAMS_FILE
173			`initial`
174			$display("Boot mem file is %s", `BOOT_MEM_PARAMS_FILE );
175			`endif
176			`endif
177			`//synopsys translate_on`
178
179			`endmodule`
180
181

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[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [boot_mem32.v] - Blame information for rev 50