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//////////////////////////////////////////////////////////////////
//                                                              //
//  Clock and Resets                                            //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Takes in the 200MHx board clock and generates the main      //
//  system clock. For the FPGA this is done with a PLL.         //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
 
//
// Clocks and Resets Module
//
 
module clocks_resets  (
input                       i_brd_rst,
input                       i_brd_clk_n,
input                       i_brd_clk_p,
input                       i_ddr_calib_done,
output                      o_sys_rst,
output                      o_sys_clk,
output                      o_clk_200
 
);
 
 
wire                        calib_done_33mhz;
wire                        rst0;
 
assign o_sys_rst = rst0 || !calib_done_33mhz;
 
 
 
`ifdef XILINX_FPGA
 
    localparam                  RST_SYNC_NUM = 25;
    wire                        pll_locked;
    wire                        clkfbout_clkfbin;
    reg [RST_SYNC_NUM-1:0]      rst0_sync_r    /* synthesis syn_maxfan = 10 */;
    reg [RST_SYNC_NUM-1:0]      ddr_calib_done_sync_r    /* synthesis syn_maxfan = 10 */;
    wire                        rst_tmp;
    wire                        pll_clk;
 
    (* KEEP = "TRUE" *)  wire brd_clk_ibufg;
 
 
    IBUFGDS # (
         .DIFF_TERM  ( "TRUE"     ),
         .IOSTANDARD ( "LVDS_25"  ))  // SP605 on chip termination of LVDS clock
         u_ibufgds_brd
        (
         .I  ( i_brd_clk_p    ),
         .IB ( i_brd_clk_n    ),
         .O  ( brd_clk_ibufg  )
         );
 
 
    assign rst0             = rst0_sync_r[RST_SYNC_NUM-1];
    assign calib_done_33mhz = ddr_calib_done_sync_r[RST_SYNC_NUM-1];
    assign o_clk_200        = brd_clk_ibufg;
 
 
    `ifdef XILINX_SPARTAN6_FPGA
    // ======================================
    // Xilinx Spartan-6 PLL
    // ======================================
        PLL_ADV #
            (
             .BANDWIDTH          ( "OPTIMIZED"        ),
             .CLKIN1_PERIOD      ( 5                  ),
             .CLKIN2_PERIOD      ( 1                  ),
             .CLKOUT0_DIVIDE     ( 1                  ),
             .CLKOUT1_DIVIDE     (                    ),
             .CLKOUT2_DIVIDE     ( `AMBER_CLK_DIVIDER ),   // = 800 MHz / LP_CLK_DIVIDER
             .CLKOUT3_DIVIDE     ( 1                  ),
             .CLKOUT4_DIVIDE     ( 1                  ),
             .CLKOUT5_DIVIDE     ( 1                  ),
             .CLKOUT0_PHASE      ( 0.000              ),
             .CLKOUT1_PHASE      ( 0.000              ),
             .CLKOUT2_PHASE      ( 0.000              ),
             .CLKOUT3_PHASE      ( 0.000              ),
             .CLKOUT4_PHASE      ( 0.000              ),
             .CLKOUT5_PHASE      ( 0.000              ),
             .CLKOUT0_DUTY_CYCLE ( 0.500              ),
             .CLKOUT1_DUTY_CYCLE ( 0.500              ),
             .CLKOUT2_DUTY_CYCLE ( 0.500              ),
             .CLKOUT3_DUTY_CYCLE ( 0.500              ),
             .CLKOUT4_DUTY_CYCLE ( 0.500              ),
             .CLKOUT5_DUTY_CYCLE ( 0.500              ),
             .COMPENSATION       ( "INTERNAL"         ),
             .DIVCLK_DIVIDE      ( 1                  ),
             .CLKFBOUT_MULT      ( 4                  ),   // 200 MHz clock input, x4 to get 800 MHz MCB
             .CLKFBOUT_PHASE     ( 0.0                ),
             .REF_JITTER         ( 0.005000           )
             )
            u_pll_adv
              (
               .CLKFBIN     ( clkfbout_clkfbin  ),
               .CLKINSEL    ( 1'b1              ),
               .CLKIN1      ( brd_clk_ibufg     ),
               .CLKIN2      ( 1'b0              ),
               .DADDR       ( 5'b0              ),
               .DCLK        ( 1'b0              ),
               .DEN         ( 1'b0              ),
               .DI          ( 16'b0             ),
               .DWE         ( 1'b0              ),
               .REL         ( 1'b0              ),
               .RST         ( i_brd_rst          ),
               .CLKFBDCM    (                   ),
               .CLKFBOUT    ( clkfbout_clkfbin  ),
               .CLKOUTDCM0  (                   ),
               .CLKOUTDCM1  (                   ),
               .CLKOUTDCM2  (                   ),
               .CLKOUTDCM3  (                   ),
               .CLKOUTDCM4  (                   ),
               .CLKOUTDCM5  (                   ),
               .CLKOUT0     (                   ),
               .CLKOUT1     (                   ),
               .CLKOUT2     ( pll_clk           ),
               .CLKOUT3     (                   ),
               .CLKOUT4     (                   ),
               .CLKOUT5     (                   ),
               .DO          (                   ),
               .DRDY        (                   ),
               .LOCKED      ( pll_locked        )
               );
    `endif
 
 
    `ifdef XILINX_VIRTEX6_FPGA
    // ======================================
    // Xilinx Virtex-6 PLL
    // ======================================
        MMCM_ADV #
        (
         .CLKIN1_PERIOD      ( 5                    ),   // 200 MHz
         .CLKOUT2_DIVIDE     ( `AMBER_CLK_DIVIDER   ),
         .CLKFBOUT_MULT_F    ( 5                    )    // 200 MHz x 5 = 1000 MHz
         )
        u_pll_adv
          (
           .CLKFBOUT     ( clkfbout_clkfbin ),
           .CLKFBOUTB    (                  ),
           .CLKFBSTOPPED (                  ),
           .CLKINSTOPPED (                  ),
           .CLKOUT0      (                  ),
           .CLKOUT0B     (                  ),
           .CLKOUT1      (                  ),
           .CLKOUT1B     (                  ),
           .CLKOUT2      ( pll_clk          ),
           .CLKOUT2B     (                  ),
           .CLKOUT3      (                  ),
           .CLKOUT3B     (                  ),
           .CLKOUT4      (                  ),
           .CLKOUT5      (                  ),
           .CLKOUT6      (                  ),
           .DRDY         (                  ),
           .LOCKED       ( pll_locked       ),
           .PSDONE       (                  ),
           .DO           (                  ),
           .CLKFBIN      ( clkfbout_clkfbin ),
           .CLKIN1       ( brd_clk_ibufg    ),
           .CLKIN2       ( 1'b0             ),
           .CLKINSEL     ( 1'b1             ),
           .DCLK         ( 1'b0             ),
           .DEN          ( 1'b0             ),
           .DWE          ( 1'b0             ),
           .PSCLK        ( 1'd0             ),
           .PSEN         ( 1'd0             ),
           .PSINCDEC     ( 1'd0             ),
           .PWRDWN       ( 1'd0             ),
           .RST          ( i_brd_rst         ),
           .DI           ( 16'b0            ),
           .DADDR        ( 7'b0             )
           );
    `endif
 
 
    BUFG u_bufg_sys_clk (
         .O ( o_sys_clk  ),
         .I ( pll_clk    )
         );
 
 
    // ======================================
    // Synchronous reset generation
    // ======================================
    assign rst_tmp = i_brd_rst | ~pll_locked;
 
      // synthesis attribute max_fanout of rst0_sync_r is 10
    always @(posedge o_sys_clk or posedge rst_tmp)
        if (rst_tmp)
          rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
        else
          // logical left shift by one (pads with 0)
          rst0_sync_r <= rst0_sync_r << 1;
 
    always @(posedge o_sys_clk or posedge rst_tmp)
        if (rst_tmp)
            ddr_calib_done_sync_r <= {RST_SYNC_NUM{1'b0}};
        else
            ddr_calib_done_sync_r <= {ddr_calib_done_sync_r[RST_SYNC_NUM-2:0], i_ddr_calib_done};
 
    `endif
 
 
 
`ifndef XILINX_FPGA
 
real      brd_clk_period = 6000;  // use starting value of 6000pS
real      pll_clk_period = 1000;  // use starting value of 1000pS
real      brd_temp;
reg       pll_clk_beh;
reg       sys_clk_beh;
integer   pll_div_count = 0;
 
// measure input clock period
initial
    begin
    @ (posedge i_brd_clk_p)
    brd_temp = $time;
    @ (posedge i_brd_clk_p)
    brd_clk_period = $time - brd_temp;
    pll_clk_period = brd_clk_period / 4;
    end
 
// Generate an 800MHz pll clock based off the input clock
always @( posedge i_brd_clk_p )
    begin
    pll_clk_beh = 1'd1;
    # ( pll_clk_period / 2 )
    pll_clk_beh = 1'd0;
    # ( pll_clk_period / 2 )
 
    pll_clk_beh = 1'd1;
    # ( pll_clk_period / 2 )
    pll_clk_beh = 1'd0;
    # ( pll_clk_period / 2 )
 
    pll_clk_beh = 1'd1;
    # ( pll_clk_period / 2 )
    pll_clk_beh = 1'd0;
    # ( pll_clk_period / 2 )
 
    pll_clk_beh = 1'd1;
    # ( pll_clk_period / 2 )
    pll_clk_beh = 1'd0;
 
    end
 
// Divide the pll clock down to get the system clock
always @( pll_clk_beh )
    begin
    if ( pll_div_count == (
        `AMBER_CLK_DIVIDER
        * 2 ) - 1 )
        pll_div_count <= 'd0;
    else
        pll_div_count <= pll_div_count + 1'd1;
 
    if ( pll_div_count == 0 )
        sys_clk_beh = 1'd1;
    else if ( pll_div_count ==
        `AMBER_CLK_DIVIDER
        )
        sys_clk_beh = 1'd0;
    end
 
assign o_sys_clk        = sys_clk_beh;
assign rst0             = i_brd_rst;
assign calib_done_33mhz = 1'd1;
assign o_clk_200        = i_brd_clk_p;
 
`endif
 
 
endmodule
 
 

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[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [clocks_resets.v] - Blame information for rev 39

Line No.	Rev	Author	Line
1	2	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Clock and Resets //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Takes in the 200MHx board clock and generates the main //`
10			`// system clock. For the FPGA this is done with a PLL. //`
11			`// //`
12			`// Author(s): //`
13			`// - Conor Santifort, csantifort.amber@gmail.com //`
14			`// //`
15			`//////////////////////////////////////////////////////////////////`
16			`// //`
17			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
18			`// //`
19			`// This source file may be used and distributed without //`
20			`// restriction provided that this copyright statement is not //`
21			`// removed from the file and that any derivative work contains //`
22			`// the original copyright notice and the associated disclaimer. //`
23			`// //`
24			`// This source file is free software; you can redistribute it //`
25			`// and/or modify it under the terms of the GNU Lesser General //`
26			`// Public License as published by the Free Software Foundation; //`
27			`// either version 2.1 of the License, or (at your option) any //`
28			`// later version. //`
29			`// //`
30			`// This source is distributed in the hope that it will be //`
31			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
32			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
33			`// PURPOSE. See the GNU Lesser General Public License for more //`
34			`// details. //`
35			`// //`
36			`// You should have received a copy of the GNU Lesser General //`
37			`// Public License along with this source; if not, download it //`
38			`// from http://www.opencores.org/lgpl.shtml //`
39			`// //`
40			`//////////////////////////////////////////////////////////////////`
41
42
43			`//`
44			`// Clocks and Resets Module`
45			`//`
46
47			`module clocks_resets (`
48			`input i_brd_rst,`
49			`input i_brd_clk_n,`
50			`input i_brd_clk_p,`
51			`input i_ddr_calib_done,`
52			`output o_sys_rst,`
53			`output o_sys_clk,`
54			`output o_clk_200`
55
56			`);`
57
58
59			`wire calib_done_33mhz;`
60			`wire rst0;`
61
62			`assign o_sys_rst = rst0 \|\| !calib_done_33mhz;`
63
64
65
66			`ifdef XILINX_FPGA
67
68			`localparam RST_SYNC_NUM = 25;`
69			`wire pll_locked;`
70			`wire clkfbout_clkfbin;`
71			`reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;`
72			`reg [RST_SYNC_NUM-1:0] ddr_calib_done_sync_r /* synthesis syn_maxfan = 10 */;`
73			`wire rst_tmp;`
74			`wire pll_clk;`
75
76			`(* KEEP = "TRUE" *) wire brd_clk_ibufg;`
77
78
79			`IBUFGDS # (`
80			`.DIFF_TERM ( "TRUE" ),`
81			`.IOSTANDARD ( "LVDS_25" )) // SP605 on chip termination of LVDS clock`
82			`u_ibufgds_brd`
83			`(`
84			`.I ( i_brd_clk_p ),`
85			`.IB ( i_brd_clk_n ),`
86			`.O ( brd_clk_ibufg )`
87			`);`
88
89
90			`assign rst0 = rst0_sync_r[RST_SYNC_NUM-1];`
91			`assign calib_done_33mhz = ddr_calib_done_sync_r[RST_SYNC_NUM-1];`
92			`assign o_clk_200 = brd_clk_ibufg;`
93
94
95			`ifdef XILINX_SPARTAN6_FPGA
96			`// ======================================`
97			`// Xilinx Spartan-6 PLL`
98			`// ======================================`
99			`PLL_ADV #`
100			`(`
101			`.BANDWIDTH ( "OPTIMIZED" ),`
102			`.CLKIN1_PERIOD ( 5 ),`
103			`.CLKIN2_PERIOD ( 1 ),`
104			`.CLKOUT0_DIVIDE ( 1 ),`
105			`.CLKOUT1_DIVIDE ( ),`
106			.CLKOUT2_DIVIDE ( `AMBER_CLK_DIVIDER ), // = 800 MHz / LP_CLK_DIVIDER
107			`.CLKOUT3_DIVIDE ( 1 ),`
108			`.CLKOUT4_DIVIDE ( 1 ),`
109			`.CLKOUT5_DIVIDE ( 1 ),`
110			`.CLKOUT0_PHASE ( 0.000 ),`
111			`.CLKOUT1_PHASE ( 0.000 ),`
112			`.CLKOUT2_PHASE ( 0.000 ),`
113			`.CLKOUT3_PHASE ( 0.000 ),`
114			`.CLKOUT4_PHASE ( 0.000 ),`
115			`.CLKOUT5_PHASE ( 0.000 ),`
116			`.CLKOUT0_DUTY_CYCLE ( 0.500 ),`
117			`.CLKOUT1_DUTY_CYCLE ( 0.500 ),`
118			`.CLKOUT2_DUTY_CYCLE ( 0.500 ),`
119			`.CLKOUT3_DUTY_CYCLE ( 0.500 ),`
120			`.CLKOUT4_DUTY_CYCLE ( 0.500 ),`
121			`.CLKOUT5_DUTY_CYCLE ( 0.500 ),`
122			`.COMPENSATION ( "INTERNAL" ),`
123			`.DIVCLK_DIVIDE ( 1 ),`
124			`.CLKFBOUT_MULT ( 4 ), // 200 MHz clock input, x4 to get 800 MHz MCB`
125			`.CLKFBOUT_PHASE ( 0.0 ),`
126			`.REF_JITTER ( 0.005000 )`
127			`)`
128			`u_pll_adv`
129			`(`
130			`.CLKFBIN ( clkfbout_clkfbin ),`
131			`.CLKINSEL ( 1'b1 ),`
132			`.CLKIN1 ( brd_clk_ibufg ),`
133			`.CLKIN2 ( 1'b0 ),`
134			`.DADDR ( 5'b0 ),`
135			`.DCLK ( 1'b0 ),`
136			`.DEN ( 1'b0 ),`
137			`.DI ( 16'b0 ),`
138			`.DWE ( 1'b0 ),`
139			`.REL ( 1'b0 ),`
140			`.RST ( i_brd_rst ),`
141			`.CLKFBDCM ( ),`
142			`.CLKFBOUT ( clkfbout_clkfbin ),`
143			`.CLKOUTDCM0 ( ),`
144			`.CLKOUTDCM1 ( ),`
145			`.CLKOUTDCM2 ( ),`
146			`.CLKOUTDCM3 ( ),`
147			`.CLKOUTDCM4 ( ),`
148			`.CLKOUTDCM5 ( ),`
149			`.CLKOUT0 ( ),`
150			`.CLKOUT1 ( ),`
151			`.CLKOUT2 ( pll_clk ),`
152			`.CLKOUT3 ( ),`
153			`.CLKOUT4 ( ),`
154			`.CLKOUT5 ( ),`
155			`.DO ( ),`
156			`.DRDY ( ),`
157			`.LOCKED ( pll_locked )`
158			`);`
159			`endif
160
161
162			`ifdef XILINX_VIRTEX6_FPGA
163			`// ======================================`
164			`// Xilinx Virtex-6 PLL`
165			`// ======================================`
166			`MMCM_ADV #`
167			`(`
168			`.CLKIN1_PERIOD ( 5 ), // 200 MHz`
169			.CLKOUT2_DIVIDE ( `AMBER_CLK_DIVIDER ),
170			`.CLKFBOUT_MULT_F ( 5 ) // 200 MHz x 5 = 1000 MHz`
171			`)`
172			`u_pll_adv`
173			`(`
174			`.CLKFBOUT ( clkfbout_clkfbin ),`
175			`.CLKFBOUTB ( ),`
176			`.CLKFBSTOPPED ( ),`
177			`.CLKINSTOPPED ( ),`
178			`.CLKOUT0 ( ),`
179			`.CLKOUT0B ( ),`
180			`.CLKOUT1 ( ),`
181			`.CLKOUT1B ( ),`
182			`.CLKOUT2 ( pll_clk ),`
183			`.CLKOUT2B ( ),`
184			`.CLKOUT3 ( ),`
185			`.CLKOUT3B ( ),`
186			`.CLKOUT4 ( ),`
187			`.CLKOUT5 ( ),`
188			`.CLKOUT6 ( ),`
189			`.DRDY ( ),`
190			`.LOCKED ( pll_locked ),`
191			`.PSDONE ( ),`
192			`.DO ( ),`
193			`.CLKFBIN ( clkfbout_clkfbin ),`
194			`.CLKIN1 ( brd_clk_ibufg ),`
195			`.CLKIN2 ( 1'b0 ),`
196			`.CLKINSEL ( 1'b1 ),`
197			`.DCLK ( 1'b0 ),`
198			`.DEN ( 1'b0 ),`
199			`.DWE ( 1'b0 ),`
200			`.PSCLK ( 1'd0 ),`
201			`.PSEN ( 1'd0 ),`
202			`.PSINCDEC ( 1'd0 ),`
203			`.PWRDWN ( 1'd0 ),`
204			`.RST ( i_brd_rst ),`
205			`.DI ( 16'b0 ),`
206			`.DADDR ( 7'b0 )`
207			`);`
208			`endif
209
210
211			`BUFG u_bufg_sys_clk (`
212			`.O ( o_sys_clk ),`
213			`.I ( pll_clk )`
214			`);`
215
216
217			`// ======================================`
218			`// Synchronous reset generation`
219			`// ======================================`
220			`assign rst_tmp = i_brd_rst \| ~pll_locked;`
221
222			`// synthesis attribute max_fanout of rst0_sync_r is 10`
223			`always @(posedge o_sys_clk or posedge rst_tmp)`
224			`if (rst_tmp)`
225			`rst0_sync_r <= {RST_SYNC_NUM{1'b1}};`
226			`else`
227			`// logical left shift by one (pads with 0)`
228			`rst0_sync_r <= rst0_sync_r << 1;`
229
230			`always @(posedge o_sys_clk or posedge rst_tmp)`
231			`if (rst_tmp)`
232			`ddr_calib_done_sync_r <= {RST_SYNC_NUM{1'b0}};`
233			`else`
234			`ddr_calib_done_sync_r <= {ddr_calib_done_sync_r[RST_SYNC_NUM-2:0], i_ddr_calib_done};`
235
236			`endif
237
238
239
240			`ifndef XILINX_FPGA
241
242	14	csantifort	`real brd_clk_period = 6000; // use starting value of 6000pS`
243			`real pll_clk_period = 1000; // use starting value of 1000pS`
244			`real brd_temp;`
245			`reg pll_clk_beh;`
246			`reg sys_clk_beh;`
247			`integer pll_div_count = 0;`
248	2	csantifort
249	14	csantifort	`// measure input clock period`
250	2	csantifort	`initial`
251			`begin`
252	14	csantifort	`@ (posedge i_brd_clk_p)`
253			`brd_temp = $time;`
254			`@ (posedge i_brd_clk_p)`
255			`brd_clk_period = $time - brd_temp;`
256			`pll_clk_period = brd_clk_period / 4;`
257	2	csantifort	`end`
258
259	14	csantifort	`// Generate an 800MHz pll clock based off the input clock`
260			`always @( posedge i_brd_clk_p )`
261			`begin`
262			`pll_clk_beh = 1'd1;`
263			`# ( pll_clk_period / 2 )`
264			`pll_clk_beh = 1'd0;`
265			`# ( pll_clk_period / 2 )`
266
267			`pll_clk_beh = 1'd1;`
268			`# ( pll_clk_period / 2 )`
269			`pll_clk_beh = 1'd0;`
270			`# ( pll_clk_period / 2 )`
271
272			`pll_clk_beh = 1'd1;`
273			`# ( pll_clk_period / 2 )`
274			`pll_clk_beh = 1'd0;`
275			`# ( pll_clk_period / 2 )`
276
277			`pll_clk_beh = 1'd1;`
278			`# ( pll_clk_period / 2 )`
279			`pll_clk_beh = 1'd0;`
280
281			`end`
282
283			`// Divide the pll clock down to get the system clock`
284			`always @( pll_clk_beh )`
285			`begin`
286			`if ( pll_div_count == (`
287			`AMBER_CLK_DIVIDER
288			`* 2 ) - 1 )`
289			`pll_div_count <= 'd0;`
290			`else`
291			`pll_div_count <= pll_div_count + 1'd1;`
292
293			`if ( pll_div_count == 0 )`
294			`sys_clk_beh = 1'd1;`
295			`else if ( pll_div_count ==`
296			`AMBER_CLK_DIVIDER
297			`)`
298			`sys_clk_beh = 1'd0;`
299			`end`
300
301			`assign o_sys_clk = sys_clk_beh;`
302	2	csantifort	`assign rst0 = i_brd_rst;`
303			`assign calib_done_33mhz = 1'd1;`
304			`assign o_clk_200 = i_brd_clk_p;`
305
306			`endif
307
308
309			`endmodule`
310
311