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csantifort |
//////////////////////////////////////////////////////////////////
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// //
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// Asynchronous FIFO set for Wishbone to Xilinx Virtex-6 //
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// DDR3 Bridge //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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module ddr3_afifo
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#(
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parameter ADDR_WIDTH = 30,
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parameter DATA_WIDTH = 32
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)
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(
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input i_sys_clk,
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input i_ddr_clk,
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// Write-Side Ports
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input i_cmd_en, // Command Enable
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input [2:0] i_cmd_instr, // write = 000, read = 001
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input [ADDR_WIDTH-1:0] i_cmd_byte_addr, // Memory address
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output o_cmd_full, // DDR3 I/F Command FIFO is full
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output o_wr_full, // DDR3 I/F Write Data FIFO is full
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input i_wr_en, // Write data enable
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input [DATA_WIDTH/8-1:0] i_wr_mask, // 1 bit per byte
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input [DATA_WIDTH-1:0] i_wr_data, // 16 bytes write data
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input [1:0] i_wr_addr_32, // address bits [3:2]
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output [DATA_WIDTH-1:0] o_rd_data, // 16 bytes of read data
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output o_rd_valid, // low when read data is valid
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// Read-Side Ports
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output o_ddr_cmd_en, // Command Enable
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output [2:0] o_ddr_cmd_instr, // write = 000, read = 001
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output [ADDR_WIDTH-1:0] o_ddr_cmd_byte_addr, // Memory address
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input i_ddr_cmd_full, // DDR3 I/F Command FIFO is full
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input i_ddr_wr_full, // DDR3 I/F Write Data FIFO is full
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output o_ddr_wr_en, // Write data enable
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output [DATA_WIDTH/8-1:0] o_ddr_wr_mask, // 1 bit per byte
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output [DATA_WIDTH-1:0] o_ddr_wr_data, // 16 bytes write data
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output [1:0] o_ddr_wr_addr_32, // address bits [3:2]
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input [DATA_WIDTH-1:0] i_ddr_rd_data, // 16 bytes of read data
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input i_ddr_rd_valid // low when read data is valid
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);
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wire cmd_empty, wr_empty, rd_empty;
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assign o_ddr_cmd_en = !cmd_empty;
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assign o_ddr_wr_en = !wr_empty;
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assign o_rd_valid = !rd_empty;
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afifo #(.D_WIDTH(ADDR_WIDTH+3)) u_afifo_cmd (
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.wr_clk ( i_sys_clk ),
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.rd_clk ( i_ddr_clk ),
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.i_data ( {i_cmd_instr, i_cmd_byte_addr} ),
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.o_data ( {o_ddr_cmd_instr, o_ddr_cmd_byte_addr} ),
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.i_push ( i_cmd_en ),
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.i_pop ( o_ddr_cmd_en && !i_ddr_cmd_full ),
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.o_full ( o_cmd_full ),
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.o_empty ( cmd_empty )
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);
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afifo #(.D_WIDTH(DATA_WIDTH+DATA_WIDTH/8+2)) u_afifo_wr (
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.wr_clk ( i_sys_clk ),
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.rd_clk ( i_ddr_clk ),
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.i_data ( {i_wr_addr_32, i_wr_mask, i_wr_data } ),
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.o_data ( {o_ddr_wr_addr_32, o_ddr_wr_mask, o_ddr_wr_data} ),
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.i_push ( i_wr_en ),
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.i_pop ( o_ddr_wr_en && !i_ddr_wr_full ),
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.o_full ( o_wr_full ),
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.o_empty ( wr_empty )
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);
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afifo #(.D_WIDTH(DATA_WIDTH)) u_afifo_rd (
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.wr_clk ( i_ddr_clk ),
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.rd_clk ( i_sys_clk ),
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.i_data ( i_ddr_rd_data ),
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.o_data ( o_rd_data ),
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.i_push ( i_ddr_rd_valid ),
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.i_pop ( o_rd_valid ),
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.o_full ( ),
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.o_empty ( rd_empty )
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);
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endmodule
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