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[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [ethmac_wb.v] - Blame information for rev 49

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1 35 csantifort
//////////////////////////////////////////////////////////////////
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//                                                              //
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//  Ethmac module Wishbone bus width and endian switch          //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Arbitrates between two wishbone masters and 13 wishbone     //
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//  slave modules. The ethernet MAC wishbone master is given    //
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//  priority over the Amber core.                               //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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module ethmac_wb #(
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parameter WB_DWIDTH  = 32,
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parameter WB_SWIDTH  = 4
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)(
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// Ethmac side
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input       [31:0]          i_m_wb_adr,
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input       [3:0]           i_m_wb_sel,
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input                       i_m_wb_we,
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output      [31:0]          o_m_wb_rdat,
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input       [31:0]          i_m_wb_wdat,
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input                       i_m_wb_cyc,
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input                       i_m_wb_stb,
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output                      o_m_wb_ack,
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output                      o_m_wb_err,
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// Wishbone arbiter side
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output      [31:0]          o_m_wb_adr,
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output      [WB_SWIDTH-1:0] o_m_wb_sel,
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output                      o_m_wb_we,
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input       [WB_DWIDTH-1:0] i_m_wb_rdat,
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output      [WB_DWIDTH-1:0] o_m_wb_wdat,
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output                      o_m_wb_cyc,
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output                      o_m_wb_stb,
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input                       i_m_wb_ack,
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input                       i_m_wb_err,
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// Wishbone arbiter side
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input       [31:0]          i_s_wb_adr,
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input       [WB_SWIDTH-1:0] i_s_wb_sel,
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input                       i_s_wb_we,
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output      [WB_DWIDTH-1:0] o_s_wb_rdat,
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input       [WB_DWIDTH-1:0] i_s_wb_wdat,
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input                       i_s_wb_cyc,
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input                       i_s_wb_stb,
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output                      o_s_wb_ack,
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output                      o_s_wb_err,
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// Ethmac side
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output      [31:0]          o_s_wb_adr,
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output      [3:0]           o_s_wb_sel,
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output                      o_s_wb_we,
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input       [31:0]          i_s_wb_rdat,
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output      [31:0]          o_s_wb_wdat,
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output                      o_s_wb_cyc,
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output                      o_s_wb_stb,
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input                       i_s_wb_ack,
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input                       i_s_wb_err
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);
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`include "system_functions.v"
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// =========================
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// Master interface - with endian conversion
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// =========================
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generate
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if (WB_DWIDTH == 128)
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    begin : wbm128
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    assign o_m_wb_rdat = i_m_wb_adr[3:2] == 2'd3 ? endian_x32(i_m_wb_rdat[127:96]) :
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                         i_m_wb_adr[3:2] == 2'd2 ? endian_x32(i_m_wb_rdat[ 95:64]) :
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                         i_m_wb_adr[3:2] == 2'd1 ? endian_x32(i_m_wb_rdat[ 63:32]) :
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                                                   endian_x32(i_m_wb_rdat[ 31: 0]) ;
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    assign o_m_wb_sel  = i_m_wb_adr[3:2] == 2'd3 ? {       endian_x4(i_m_wb_sel), 12'd0} :
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                         i_m_wb_adr[3:2] == 2'd2 ? { 4'd0, endian_x4(i_m_wb_sel),  8'd0} :
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                         i_m_wb_adr[3:2] == 2'd1 ? { 8'd0, endian_x4(i_m_wb_sel),  4'd0} :
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                                                   {12'd0, endian_x4(i_m_wb_sel)       } ;
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    assign o_m_wb_wdat = i_m_wb_adr[3:2] == 2'd3 ? {       endian_x32(i_m_wb_wdat), 96'd0} :
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                         i_m_wb_adr[3:2] == 2'd2 ? {32'd0, endian_x32(i_m_wb_wdat), 64'd0} :
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                         i_m_wb_adr[3:2] == 2'd1 ? {64'd0, endian_x32(i_m_wb_wdat), 32'd0} :
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                                                   {96'd0, endian_x32(i_m_wb_wdat)       } ;
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    end
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else
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    begin : wbm32
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    assign o_m_wb_rdat = endian_x32(i_m_wb_rdat);
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    assign o_m_wb_sel  = endian_x4 (i_m_wb_sel);
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    assign o_m_wb_wdat = endian_x32(i_m_wb_wdat);
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    end
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endgenerate
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assign o_m_wb_ack = i_m_wb_ack;
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assign o_m_wb_err = i_m_wb_err;
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assign o_m_wb_adr = i_m_wb_adr;
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assign o_m_wb_we  = i_m_wb_we ;
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assign o_m_wb_cyc = i_m_wb_cyc;
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assign o_m_wb_stb = i_m_wb_stb;
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// =========================
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// Slave interface - no endian conversion
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// =========================
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generate
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if (WB_DWIDTH == 128)
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    begin : wbs128
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    assign o_s_wb_wdat = i_s_wb_adr[3:2] == 2'd3 ? i_s_wb_wdat[127:96] :
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                         i_s_wb_adr[3:2] == 2'd2 ? i_s_wb_wdat[ 95:64] :
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                         i_s_wb_adr[3:2] == 2'd1 ? i_s_wb_wdat[ 63:32] :
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                                                   i_s_wb_wdat[ 31: 0] ;
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    assign o_s_wb_sel  = i_s_wb_adr[3:2] == 2'd3 ? i_s_wb_sel[15:12] :
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                         i_s_wb_adr[3:2] == 2'd2 ? i_s_wb_sel[11: 8] :
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                         i_s_wb_adr[3:2] == 2'd1 ? i_s_wb_sel[ 7: 4] :
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                                                   i_s_wb_sel[ 3: 0] ;
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    assign o_s_wb_rdat = i_s_wb_adr[3:2] == 2'd3 ? {       i_s_wb_rdat, 96'd0} :
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                         i_s_wb_adr[3:2] == 2'd2 ? {32'd0, i_s_wb_rdat, 64'd0} :
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                         i_s_wb_adr[3:2] == 2'd1 ? {64'd0, i_s_wb_rdat, 32'd0} :
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                                                   {96'd0, i_s_wb_rdat       } ;
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    end
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else
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    begin : wbs32
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    assign o_s_wb_wdat = i_s_wb_wdat;
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    assign o_s_wb_sel  = i_s_wb_sel;
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    assign o_s_wb_rdat = i_s_wb_rdat;
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    end
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endgenerate
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assign o_s_wb_ack = i_s_wb_ack;
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assign o_s_wb_err = i_s_wb_err;
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assign o_s_wb_adr = i_s_wb_adr;
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assign o_s_wb_we  = i_s_wb_we ;
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assign o_s_wb_cyc = i_s_wb_cyc;
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assign o_s_wb_stb = i_s_wb_stb;
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endmodule
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