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csantifort |
//////////////////////////////////////////////////////////////////
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// //
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// Main memory for simulations. //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// Non-synthesizable main memory. Holds 128MBytes //
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// The memory path in this module is purely combinational. //
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// Addresses and write_cmd_req data are registered as //
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// the leave the execute module and read data is registered //
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// as it enters the instruction_decode module. //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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module main_mem
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(
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input i_clk,
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// Wishbone Bus
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input [31:0] i_wb_adr,
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input [3:0] i_wb_sel,
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input i_wb_we,
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output reg [31:0] o_wb_dat = 'd0,
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input [31:0] i_wb_dat,
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input i_wb_cyc,
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input i_wb_stb,
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output o_wb_ack,
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output o_wb_err
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);
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`include "memory_configuration.v"
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reg [127:0] ram [2**(MAIN_MSB-2)-1:0];
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wire start_write;
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wire start_read;
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reg start_read_d1;
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reg start_read_d2;
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wire [127:0] rd_data;
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wire [127:0] masked_wdata;
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reg wr_en = 'd0;
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reg [15:0] wr_mask = 'd0;
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reg [127:0] wr_data = 'd0;
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reg [27:0] addr_d1 = 'd0;
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wire busy;
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genvar i;
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assign start_write = i_wb_stb && i_wb_we && !busy;
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assign start_read = i_wb_stb && !i_wb_we && !busy;
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assign busy = start_read_d1 || start_read_d2;
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assign o_wb_err = 'd0;
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// ------------------------------------------------------
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// Write
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// ------------------------------------------------------
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always @( posedge i_clk )
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begin
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wr_en <= start_write;
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wr_mask <= i_wb_adr[3:2] == 2'd0 ? { 12'hfff, ~i_wb_sel } :
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i_wb_adr[3:2] == 2'd1 ? { 8'hff, ~i_wb_sel, 4'hf } :
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i_wb_adr[3:2] == 2'd2 ? { 4'hf, ~i_wb_sel, 8'hff } :
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{ ~i_wb_sel, 12'hfff } ;
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wr_data <= {4{i_wb_dat}};
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addr_d1 <= i_wb_adr[29:2];
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if ( wr_en )
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ram [addr_d1[27:2]] <= masked_wdata;
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end
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generate
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for (i=0;i<16;i=i+1) begin : masked
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assign masked_wdata[8*i+7:8*i] = wr_mask[i] ? rd_data[8*i+7:8*i] : wr_data[8*i+7:8*i];
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end
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endgenerate
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// ------------------------------------------------------
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// Read
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// ------------------------------------------------------
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assign rd_data = ram [addr_d1[27:2]];
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always @( posedge i_clk )
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begin
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start_read_d1 <= start_read;
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start_read_d2 <= start_read_d1;
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if ( start_read_d1 )
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begin
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o_wb_dat <= addr_d1[1:0] == 2'd0 ? rd_data[ 31: 0] :
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addr_d1[1:0] == 2'd1 ? rd_data[ 63:32] :
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addr_d1[1:0] == 2'd2 ? rd_data[ 95:64] :
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rd_data[127:96] ;
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end
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end
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assign o_wb_ack = i_wb_stb && ( start_write || start_read_d2 );
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endmodule
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