URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [memory_configuration.vh] - Blame information for rev 83

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////
//                                                              //
//  Memory configuration and Wishbone address decoding          //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  This module provides a set of functions that are used to    //
//  decode memory addresses so other modules know if an address //
//  is for example in main memory, or boot memory, or a UART    //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
// e.g. 24 for 32MBytes, 26 for 128MBytes
localparam MAIN_MSB             = 26;
 
// e.g. 13 for 4k words
localparam BOOT_MSB             = 13;
 
localparam MAIN_BASE            = 32'h0000_0000; /*  Main Memory            */
localparam BOOT_BASE            = 32'h0000_0000; /*  Cachable Boot Memory   */
localparam AMBER_TM_BASE        = 16'h1300;      /*  Timers Module          */
localparam AMBER_IC_BASE        = 16'h1400;      /*  Interrupt Controller   */
localparam AMBER_UART0_BASE     = 16'h1600;      /*  UART 0                 */
localparam AMBER_UART1_BASE     = 16'h1700;      /*  UART 1                 */
localparam ETHMAC_BASE          = 16'h2000;      /*  Ethernet MAC           */
localparam HIBOOT_BASE          = 32'h2800_0000; /*  Uncachable Boot Memory */
localparam TEST_BASE            = 16'hf000;      /*  Test Module            */
 
 
 
function in_loboot_mem;
    input [31:0] address;
begin
in_loboot_mem  = (address >= BOOT_BASE   &&
                 address < (BOOT_BASE   + 2**(BOOT_MSB+1)-1));
end
endfunction
 
 
function in_hiboot_mem;
    input [31:0] address;
begin
in_hiboot_mem  = (address[31:BOOT_MSB+1] == HIBOOT_BASE[31:BOOT_MSB+1]);
end
endfunction
 
 
function in_boot_mem;
    input [31:0] address;
begin
in_boot_mem  =  in_loboot_mem(address) || in_hiboot_mem(address);
end
endfunction
 
 
function in_main_mem;
    input [31:0] address;
begin
in_main_mem  = (address >= MAIN_BASE   &&
                address < (MAIN_BASE   + 2**(MAIN_MSB+1)-1)) &&
                !in_boot_mem ( address );
end
endfunction
 
 
// UART 0 address space
function in_uart0;
    input [31:0] address;
begin
    in_uart0 = address [31:16] == AMBER_UART0_BASE;
end
endfunction
 
 
// UART 1 address space
function in_uart1;
    input [31:0] address;
begin
    in_uart1 = address [31:16] == AMBER_UART1_BASE;
end
endfunction
 
 
// Interrupt Controller address space
function in_ic;
    input [31:0] address;
begin
    in_ic = address [31:16] == AMBER_IC_BASE;
end
endfunction
 
 
// Timer Module address space
function in_tm;
    input [31:0] address;
begin
    in_tm = address [31:16] == AMBER_TM_BASE;
end
endfunction
 
 
// Test module
function in_test;
    input [31:0] address;
begin
    in_test = address [31:16] == TEST_BASE;
end
endfunction
 
 
// Ethernet MAC
function in_ethmac;
    input [31:0] address;
begin
    in_ethmac = address [31:16] == ETHMAC_BASE;
end
endfunction
 
 
// Used in fetch.v and l2cache.v to allow accesses to these addresses
// to be cached
function in_cachable_mem;
    input [31:0] address;
begin
    in_cachable_mem = in_loboot_mem     ( address ) ||
                      in_main_mem       ( address ) ;
end
endfunction
 

Line No.	Rev	Author	Line
1	2	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Memory configuration and Wishbone address decoding //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// This module provides a set of functions that are used to //`
10			`// decode memory addresses so other modules know if an address //`
11			`// is for example in main memory, or boot memory, or a UART //`
12			`// //`
13			`// Author(s): //`
14			`// - Conor Santifort, csantifort.amber@gmail.com //`
15			`// //`
16			`//////////////////////////////////////////////////////////////////`
17			`// //`
18			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
19			`// //`
20			`// This source file may be used and distributed without //`
21			`// restriction provided that this copyright statement is not //`
22			`// removed from the file and that any derivative work contains //`
23			`// the original copyright notice and the associated disclaimer. //`
24			`// //`
25			`// This source file is free software; you can redistribute it //`
26			`// and/or modify it under the terms of the GNU Lesser General //`
27			`// Public License as published by the Free Software Foundation; //`
28			`// either version 2.1 of the License, or (at your option) any //`
29			`// later version. //`
30			`// //`
31			`// This source is distributed in the hope that it will be //`
32			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
33			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
34			`// PURPOSE. See the GNU Lesser General Public License for more //`
35			`// details. //`
36			`// //`
37			`// You should have received a copy of the GNU Lesser General //`
38			`// Public License along with this source; if not, download it //`
39			`// from http://www.opencores.org/lgpl.shtml //`
40			`// //`
41			`//////////////////////////////////////////////////////////////////`
42
43			`// e.g. 24 for 32MBytes, 26 for 128MBytes`
44			`localparam MAIN_MSB = 26;`
45
46	61	csantifort	`// e.g. 13 for 4k words`
47			`localparam BOOT_MSB = 13;`
48	2	csantifort
49			`localparam MAIN_BASE = 32'h0000_0000; /* Main Memory */`
50			`localparam BOOT_BASE = 32'h0000_0000; /* Cachable Boot Memory */`
51			`localparam AMBER_TM_BASE = 16'h1300; /* Timers Module */`
52			`localparam AMBER_IC_BASE = 16'h1400; /* Interrupt Controller */`
53			`localparam AMBER_UART0_BASE = 16'h1600; /* UART 0 */`
54			`localparam AMBER_UART1_BASE = 16'h1700; /* UART 1 */`
55			`localparam ETHMAC_BASE = 16'h2000; /* Ethernet MAC */`
56			`localparam HIBOOT_BASE = 32'h2800_0000; /* Uncachable Boot Memory */`
57			`localparam TEST_BASE = 16'hf000; /* Test Module */`
58
59
60
61			`function in_loboot_mem;`
62			`input [31:0] address;`
63			`begin`
64			`in_loboot_mem = (address >= BOOT_BASE &&`
65			`address < (BOOT_BASE + 2**(BOOT_MSB+1)-1));`
66			`end`
67			`endfunction`
68
69
70			`function in_hiboot_mem;`
71			`input [31:0] address;`
72			`begin`
73			`in_hiboot_mem = (address[31:BOOT_MSB+1] == HIBOOT_BASE[31:BOOT_MSB+1]);`
74			`end`
75			`endfunction`
76
77
78			`function in_boot_mem;`
79			`input [31:0] address;`
80			`begin`
81			`in_boot_mem = in_loboot_mem(address) \|\| in_hiboot_mem(address);`
82			`end`
83			`endfunction`
84
85
86			`function in_main_mem;`
87			`input [31:0] address;`
88			`begin`
89			`in_main_mem = (address >= MAIN_BASE &&`
90			`address < (MAIN_BASE + 2**(MAIN_MSB+1)-1)) &&`
91			`!in_boot_mem ( address );`
92			`end`
93			`endfunction`
94
95
96			`// UART 0 address space`
97			`function in_uart0;`
98			`input [31:0] address;`
99			`begin`
100			`in_uart0 = address [31:16] == AMBER_UART0_BASE;`
101			`end`
102			`endfunction`
103
104
105			`// UART 1 address space`
106			`function in_uart1;`
107			`input [31:0] address;`
108			`begin`
109			`in_uart1 = address [31:16] == AMBER_UART1_BASE;`
110			`end`
111			`endfunction`
112
113
114			`// Interrupt Controller address space`
115			`function in_ic;`
116			`input [31:0] address;`
117			`begin`
118			`in_ic = address [31:16] == AMBER_IC_BASE;`
119			`end`
120			`endfunction`
121
122
123			`// Timer Module address space`
124			`function in_tm;`
125			`input [31:0] address;`
126			`begin`
127			`in_tm = address [31:16] == AMBER_TM_BASE;`
128			`end`
129			`endfunction`
130
131
132			`// Test module`
133			`function in_test;`
134			`input [31:0] address;`
135			`begin`
136			`in_test = address [31:16] == TEST_BASE;`
137			`end`
138			`endfunction`
139
140
141			`// Ethernet MAC`
142			`function in_ethmac;`
143			`input [31:0] address;`
144			`begin`
145			`in_ethmac = address [31:16] == ETHMAC_BASE;`
146			`end`
147			`endfunction`
148
149
150			`// Used in fetch.v and l2cache.v to allow accesses to these addresses`
151			`// to be cached`
152			`function in_cachable_mem;`
153			`input [31:0] address;`
154			`begin`
155			`in_cachable_mem = in_loboot_mem ( address ) \|\|`
156			`in_main_mem ( address ) ;`
157			`end`
158			`endfunction`
159

Browse

Tools

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [memory_configuration.vh] - Blame information for rev 83