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csantifort |
//////////////////////////////////////////////////////////////////
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// //
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// Top-level module instantiating the entire Amber 2 system. //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// This is the highest level synthesizable module in the //
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// project. The ports in this module represent pins on the //
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// FPGA. //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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module system
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(
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input brd_rst,
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input brd_clk_n,
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input brd_clk_p,
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`ifdef XILINX_VIRTEX6_FPGA
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input sys_clk_p,
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input sys_clk_n,
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`endif
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// UART 0 Interface
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input i_uart0_rts,
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output o_uart0_rx,
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output o_uart0_cts,
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input i_uart0_tx,
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// Xilinx Spartan 6 MCB DDR3 Interface
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inout [15:0] ddr3_dq,
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output [12:0] ddr3_addr,
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output [2:0] ddr3_ba,
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output ddr3_ras_n,
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output ddr3_cas_n,
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output ddr3_we_n,
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output ddr3_odt,
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output ddr3_reset_n,
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output ddr3_cke,
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output [1:0] ddr3_dm,
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inout [1:0] ddr3_dqs_p,
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inout [1:0] ddr3_dqs_n,
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output ddr3_ck_p,
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output ddr3_ck_n,
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`ifdef XILINX_VIRTEX6_FPGA
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output ddr3_cs_n,
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`endif
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`ifdef XILINX_SPARTAN6_FPGA
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inout mcb3_rzq,
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inout mcb3_zio,
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`endif
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// Ethmac B100 MAC to PHY Interface
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input mtx_clk_pad_i,
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output [3:0] mtxd_pad_o,
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output mtxen_pad_o,
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output mtxerr_pad_o,
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input mrx_clk_pad_i,
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input [3:0] mrxd_pad_i,
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input mrxdv_pad_i,
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input mrxerr_pad_i,
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input mcoll_pad_i,
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input mcrs_pad_i,
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inout md_pad_io,
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output mdc_pad_o,
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output phy_reset_n
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);
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wire sys_clk; // System clock
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wire sys_rst; // Active low reset, synchronous to sys_clk
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wire clk_200; // 200MHz from board
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// ======================================
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// Xilinx MCB DDR3 Controller connections
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// ======================================
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`ifdef XILINX_SPARTAN6_FPGA
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wire c3_p0_cmd_en;
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wire [2:0] c3_p0_cmd_instr;
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wire [29:0] c3_p0_cmd_byte_addr;
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wire c3_p0_wr_en;
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wire [15:0] c3_p0_wr_mask;
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wire [127:0] c3_p0_wr_data;
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wire [127:0] c3_p0_rd_data;
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wire c3_p0_rd_empty;
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wire c3_p0_cmd_full;
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wire c3_p0_wr_full;
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`endif
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wire phy_init_done;
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csantifort |
wire test_mem_ctrl;
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csantifort |
wire system_rdy;
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2 |
csantifort |
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// ======================================
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// Xilinx Virtex-6 DDR3 Controller connections
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// ======================================
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`ifdef XILINX_VIRTEX6_FPGA
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wire phy_init_done1;
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wire xv6_cmd_en;
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wire [2:0] xv6_cmd_instr;
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wire [26:0] xv6_cmd_byte_addr;
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wire xv6_cmd_full;
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wire xv6_wr_full;
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wire xv6_wr_en;
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wire xv6_wr_end;
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wire [7:0] xv6_wr_mask;
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wire [63:0] xv6_wr_data;
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wire [63:0] xv6_rd_data;
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wire xv6_rd_data_valid;
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wire xv6_ddr3_clk;
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`endif
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// ======================================
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// Ethmac MII
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// ======================================
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wire md_pad_i;
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wire md_pad_o;
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wire md_padoe_o;
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// ======================================
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// Wishbone Buses
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// ======================================
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localparam WB_MASTERS = 2;
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localparam WB_SLAVES = 9;
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// Wishbone Master Buses
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wire [31:0] m_wb_adr [WB_MASTERS-1:0];
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wire [3:0] m_wb_sel [WB_MASTERS-1:0];
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wire [WB_MASTERS-1:0] m_wb_we ;
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wire [31:0] m_wb_dat_w [WB_MASTERS-1:0];
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wire [31:0] m_wb_dat_r [WB_MASTERS-1:0];
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wire [WB_MASTERS-1:0] m_wb_cyc ;
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wire [WB_MASTERS-1:0] m_wb_stb ;
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wire [WB_MASTERS-1:0] m_wb_ack ;
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wire [WB_MASTERS-1:0] m_wb_err ;
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// Wishbone Slave Buses
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wire [31:0] s_wb_adr [WB_SLAVES-1:0];
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wire [3:0] s_wb_sel [WB_SLAVES-1:0];
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wire [WB_SLAVES-1:0] s_wb_we ;
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wire [31:0] s_wb_dat_w [WB_SLAVES-1:0];
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wire [31:0] s_wb_dat_r [WB_SLAVES-1:0];
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wire [WB_SLAVES-1:0] s_wb_cyc ;
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wire [WB_SLAVES-1:0] s_wb_stb ;
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wire [WB_SLAVES-1:0] s_wb_ack ;
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wire [WB_SLAVES-1:0] s_wb_err ;
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// ======================================
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// Interrupts
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// ======================================
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wire amber_irq;
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wire amber_firq;
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wire ethmac_int;
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wire test_reg_irq;
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wire test_reg_firq;
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wire uart0_int;
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wire uart1_int;
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wire [2:0] timer_int;
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// ======================================
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// Clocks and Resets Module
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// ======================================
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clocks_resets u_clocks_resets (
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.i_brd_rst ( brd_rst ),
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.i_brd_clk_n ( brd_clk_n ),
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.i_brd_clk_p ( brd_clk_p ),
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.i_ddr_calib_done ( phy_init_done ),
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.o_sys_rst ( sys_rst ),
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.o_sys_clk ( sys_clk ),
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.o_clk_200 ( clk_200 )
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);
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// -------------------------------------------------------------
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// Instantiate Amber Processor Core
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// -------------------------------------------------------------
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15 |
csantifort |
`ifdef AMBER_A25_CORE
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a25_core u_amber (
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`else
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a23_core u_amber (
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`endif
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2 |
csantifort |
.i_clk ( sys_clk ),
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.i_irq ( amber_irq ),
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.i_firq ( amber_firq ),
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15 |
csantifort |
.i_system_rdy ( system_rdy ),
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2 |
csantifort |
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.o_wb_adr ( m_wb_adr [1] ),
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.o_wb_sel ( m_wb_sel [1] ),
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.o_wb_we ( m_wb_we [1] ),
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.i_wb_dat ( m_wb_dat_r[1] ),
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.o_wb_dat ( m_wb_dat_w[1] ),
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.o_wb_cyc ( m_wb_cyc [1] ),
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.o_wb_stb ( m_wb_stb [1] ),
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.i_wb_ack ( m_wb_ack [1] ),
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.i_wb_err ( m_wb_err [1] )
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);
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// -------------------------------------------------------------
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// Instantiate B100 Ethernet MAC
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// -------------------------------------------------------------
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eth_top u_eth_top (
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.wb_clk_i ( sys_clk ),
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.wb_rst_i ( sys_rst ),
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// WISHBONE slave
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.wb_adr_i ( s_wb_adr [0][11:2] ),
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.wb_sel_i ( s_wb_sel [0] ),
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.wb_we_i ( s_wb_we [0] ),
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.wb_cyc_i ( s_wb_cyc [0] ),
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.wb_stb_i ( s_wb_stb [0] ),
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.wb_ack_o ( s_wb_ack [0] ),
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.wb_dat_i ( s_wb_dat_w [0] ),
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.wb_dat_o ( s_wb_dat_r [0] ),
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.wb_err_o ( s_wb_err [0] ),
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// WISHBONE master
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.m_wb_adr_o ( m_wb_adr [0] ),
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.m_wb_sel_o ( m_wb_sel [0] ),
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.m_wb_we_o ( m_wb_we [0] ),
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.m_wb_dat_i ( m_wb_dat_r [0] ),
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.m_wb_dat_o ( m_wb_dat_w [0] ),
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.m_wb_cyc_o ( m_wb_cyc [0] ),
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.m_wb_stb_o ( m_wb_stb [0] ),
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.m_wb_ack_i ( m_wb_ack [0] ),
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.m_wb_err_i ( m_wb_err [0] ),
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// MAC to PHY I/F
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.mtx_clk_pad_i ( mtx_clk_pad_i ),
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.mtxd_pad_o ( mtxd_pad_o ),
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.mtxen_pad_o ( mtxen_pad_o ),
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.mtxerr_pad_o ( mtxerr_pad_o ),
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.mrx_clk_pad_i ( mrx_clk_pad_i ),
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.mrxd_pad_i ( mrxd_pad_i ),
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.mrxdv_pad_i ( mrxdv_pad_i ),
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.mrxerr_pad_i ( mrxerr_pad_i ),
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.mcoll_pad_i ( mcoll_pad_i ),
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.mcrs_pad_i ( mcrs_pad_i ),
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.md_pad_i ( md_pad_i ),
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.mdc_pad_o ( mdc_pad_o ),
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.md_pad_o ( md_pad_o ),
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.md_padoe_o ( md_padoe_o ),
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// Interrupt
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.int_o ( ethmac_int )
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);
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// -------------------------------------------------------------
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// Instantiate Ethernet Control Interface tri-state buffer
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// -------------------------------------------------------------
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| 294 |
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`ifdef XILINX_FPGA
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IOBUF u_iobuf (
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| 296 |
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`else
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generic_iobuf u_iobuf (
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`endif
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.O ( md_pad_i ),
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.IO ( md_pad_io ),
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.I ( md_pad_o ),
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// T is high for tri-state output
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.T ( ~md_padoe_o )
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);
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// Ethernet MII PHY reset
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assign phy_reset_n = !sys_rst;
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15 |
csantifort |
// Halt core until system is ready
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assign system_rdy = phy_init_done && !sys_rst;
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| 311 |
2 |
csantifort |
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| 312 |
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// -------------------------------------------------------------
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// Instantiate Boot Memory - 8KBytes of Embedded SRAM
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// -------------------------------------------------------------
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boot_mem u_boot_mem (
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| 316 |
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.i_wb_clk ( sys_clk ),
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.i_wb_adr ( s_wb_adr [1] ),
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.i_wb_sel ( s_wb_sel [1] ),
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.i_wb_we ( s_wb_we [1] ),
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.o_wb_dat ( s_wb_dat_r[1] ),
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.i_wb_dat ( s_wb_dat_w[1] ),
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.i_wb_cyc ( s_wb_cyc [1] ),
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.i_wb_stb ( s_wb_stb [1] ),
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|
|
.o_wb_ack ( s_wb_ack [1] ),
|
| 326 |
|
|
.o_wb_err ( s_wb_err [1] )
|
| 327 |
|
|
);
|
| 328 |
|
|
|
| 329 |
|
|
|
| 330 |
|
|
|
| 331 |
|
|
// -------------------------------------------------------------
|
| 332 |
|
|
// Instantiate UART0
|
| 333 |
|
|
// -------------------------------------------------------------
|
| 334 |
|
|
uart u_uart0 (
|
| 335 |
|
|
.i_clk ( sys_clk ),
|
| 336 |
|
|
|
| 337 |
|
|
.o_uart_int ( uart0_int ),
|
| 338 |
|
|
|
| 339 |
|
|
.i_uart_cts_n ( i_uart0_rts ),
|
| 340 |
|
|
.o_uart_txd ( o_uart0_rx ),
|
| 341 |
|
|
.o_uart_rts_n ( o_uart0_cts ),
|
| 342 |
|
|
.i_uart_rxd ( i_uart0_tx ),
|
| 343 |
|
|
|
| 344 |
|
|
.i_wb_adr ( s_wb_adr [3] ),
|
| 345 |
|
|
.i_wb_sel ( s_wb_sel [3] ),
|
| 346 |
|
|
.i_wb_we ( s_wb_we [3] ),
|
| 347 |
|
|
.o_wb_dat ( s_wb_dat_r[3] ),
|
| 348 |
|
|
.i_wb_dat ( s_wb_dat_w[3] ),
|
| 349 |
|
|
.i_wb_cyc ( s_wb_cyc [3] ),
|
| 350 |
|
|
.i_wb_stb ( s_wb_stb [3] ),
|
| 351 |
|
|
.o_wb_ack ( s_wb_ack [3] ),
|
| 352 |
|
|
.o_wb_err ( s_wb_err [3] )
|
| 353 |
|
|
);
|
| 354 |
|
|
|
| 355 |
|
|
|
| 356 |
|
|
// -------------------------------------------------------------
|
| 357 |
|
|
// Instantiate UART1
|
| 358 |
|
|
// -------------------------------------------------------------
|
| 359 |
|
|
uart u_uart1 (
|
| 360 |
|
|
.i_clk ( sys_clk ),
|
| 361 |
|
|
|
| 362 |
|
|
.o_uart_int ( uart1_int ),
|
| 363 |
|
|
|
| 364 |
|
|
// These are not connected. ONly pins for 1 UART
|
| 365 |
|
|
// on my development board
|
| 366 |
|
|
.i_uart_cts_n ( 1'd1 ),
|
| 367 |
|
|
.o_uart_txd ( ),
|
| 368 |
|
|
.o_uart_rts_n ( ),
|
| 369 |
|
|
.i_uart_rxd ( 1'd1 ),
|
| 370 |
|
|
|
| 371 |
|
|
.i_wb_adr ( s_wb_adr [4] ),
|
| 372 |
|
|
.i_wb_sel ( s_wb_sel [4] ),
|
| 373 |
|
|
.i_wb_we ( s_wb_we [4] ),
|
| 374 |
|
|
.o_wb_dat ( s_wb_dat_r[4] ),
|
| 375 |
|
|
.i_wb_dat ( s_wb_dat_w[4] ),
|
| 376 |
|
|
.i_wb_cyc ( s_wb_cyc [4] ),
|
| 377 |
|
|
.i_wb_stb ( s_wb_stb [4] ),
|
| 378 |
|
|
.o_wb_ack ( s_wb_ack [4] ),
|
| 379 |
|
|
.o_wb_err ( s_wb_err [4] )
|
| 380 |
|
|
);
|
| 381 |
|
|
|
| 382 |
|
|
|
| 383 |
|
|
// -------------------------------------------------------------
|
| 384 |
|
|
// Instantiate Test Module
|
| 385 |
|
|
// - includes register used to terminate tests
|
| 386 |
|
|
// -------------------------------------------------------------
|
| 387 |
|
|
test_module u_test_module (
|
| 388 |
|
|
.i_clk ( sys_clk ),
|
| 389 |
|
|
|
| 390 |
|
|
.o_irq ( test_reg_irq ),
|
| 391 |
|
|
.o_firq ( test_reg_firq ),
|
| 392 |
11 |
csantifort |
.o_mem_ctrl ( test_mem_ctrl ),
|
| 393 |
2 |
csantifort |
.i_wb_adr ( s_wb_adr [5] ),
|
| 394 |
|
|
.i_wb_sel ( s_wb_sel [5] ),
|
| 395 |
|
|
.i_wb_we ( s_wb_we [5] ),
|
| 396 |
|
|
.o_wb_dat ( s_wb_dat_r[5] ),
|
| 397 |
|
|
.i_wb_dat ( s_wb_dat_w[5] ),
|
| 398 |
|
|
.i_wb_cyc ( s_wb_cyc [5] ),
|
| 399 |
|
|
.i_wb_stb ( s_wb_stb [5] ),
|
| 400 |
|
|
.o_wb_ack ( s_wb_ack [5] ),
|
| 401 |
|
|
.o_wb_err ( s_wb_err [5] )
|
| 402 |
|
|
);
|
| 403 |
|
|
|
| 404 |
|
|
|
| 405 |
|
|
// -------------------------------------------------------------
|
| 406 |
|
|
// Instantiate Timer Module
|
| 407 |
|
|
// -------------------------------------------------------------
|
| 408 |
|
|
timer_module u_timer_module (
|
| 409 |
|
|
.i_clk ( sys_clk ),
|
| 410 |
|
|
|
| 411 |
|
|
// Interrupt outputs
|
| 412 |
|
|
.o_timer_int ( timer_int ),
|
| 413 |
|
|
|
| 414 |
|
|
// Wishbone interface
|
| 415 |
|
|
.i_wb_adr ( s_wb_adr [6] ),
|
| 416 |
|
|
.i_wb_sel ( s_wb_sel [6] ),
|
| 417 |
|
|
.i_wb_we ( s_wb_we [6] ),
|
| 418 |
|
|
.o_wb_dat ( s_wb_dat_r[6] ),
|
| 419 |
|
|
.i_wb_dat ( s_wb_dat_w[6] ),
|
| 420 |
|
|
.i_wb_cyc ( s_wb_cyc [6] ),
|
| 421 |
|
|
.i_wb_stb ( s_wb_stb [6] ),
|
| 422 |
|
|
.o_wb_ack ( s_wb_ack [6] ),
|
| 423 |
|
|
.o_wb_err ( s_wb_err [6] )
|
| 424 |
|
|
);
|
| 425 |
|
|
|
| 426 |
|
|
|
| 427 |
|
|
// -------------------------------------------------------------
|
| 428 |
|
|
// Instantiate Interrupt Controller Module
|
| 429 |
|
|
// -------------------------------------------------------------
|
| 430 |
|
|
interrupt_controller u_interrupt_controller (
|
| 431 |
|
|
.i_clk ( sys_clk ),
|
| 432 |
|
|
|
| 433 |
|
|
// Interrupt outputs
|
| 434 |
|
|
.o_irq ( amber_irq ),
|
| 435 |
|
|
.o_firq ( amber_firq ),
|
| 436 |
|
|
|
| 437 |
|
|
// Interrupt inputs
|
| 438 |
|
|
.i_uart0_int ( uart0_int ),
|
| 439 |
|
|
.i_uart1_int ( uart1_int ),
|
| 440 |
|
|
.i_ethmac_int ( ethmac_int ),
|
| 441 |
|
|
.i_test_reg_irq ( test_reg_irq ),
|
| 442 |
|
|
.i_test_reg_firq ( test_reg_firq ),
|
| 443 |
|
|
.i_tm_timer_int ( timer_int ),
|
| 444 |
|
|
|
| 445 |
|
|
// Wishbone interface
|
| 446 |
|
|
.i_wb_adr ( s_wb_adr [7] ),
|
| 447 |
|
|
.i_wb_sel ( s_wb_sel [7] ),
|
| 448 |
|
|
.i_wb_we ( s_wb_we [7] ),
|
| 449 |
|
|
.o_wb_dat ( s_wb_dat_r[7] ),
|
| 450 |
|
|
.i_wb_dat ( s_wb_dat_w[7] ),
|
| 451 |
|
|
.i_wb_cyc ( s_wb_cyc [7] ),
|
| 452 |
|
|
.i_wb_stb ( s_wb_stb [7] ),
|
| 453 |
|
|
.o_wb_ack ( s_wb_ack [7] ),
|
| 454 |
|
|
.o_wb_err ( s_wb_err [7] )
|
| 455 |
|
|
);
|
| 456 |
|
|
|
| 457 |
|
|
|
| 458 |
|
|
|
| 459 |
|
|
|
| 460 |
|
|
`ifndef XILINX_FPGA
|
| 461 |
|
|
// ======================================
|
| 462 |
|
|
// Instantiate non-synthesizable main memory model
|
| 463 |
|
|
// ======================================
|
| 464 |
|
|
|
| 465 |
|
|
assign phy_init_done = 1'd1;
|
| 466 |
|
|
|
| 467 |
|
|
main_mem u_main_mem (
|
| 468 |
|
|
.i_clk ( sys_clk ),
|
| 469 |
11 |
csantifort |
.i_mem_ctrl ( test_mem_ctrl ),
|
| 470 |
2 |
csantifort |
.i_wb_adr ( s_wb_adr [2] ),
|
| 471 |
|
|
.i_wb_sel ( s_wb_sel [2] ),
|
| 472 |
|
|
.i_wb_we ( s_wb_we [2] ),
|
| 473 |
|
|
.o_wb_dat ( s_wb_dat_r[2] ),
|
| 474 |
|
|
.i_wb_dat ( s_wb_dat_w[2] ),
|
| 475 |
|
|
.i_wb_cyc ( s_wb_cyc [2] ),
|
| 476 |
|
|
.i_wb_stb ( s_wb_stb [2] ),
|
| 477 |
|
|
.o_wb_ack ( s_wb_ack [2] ),
|
| 478 |
|
|
.o_wb_err ( s_wb_err [2] )
|
| 479 |
|
|
);
|
| 480 |
|
|
|
| 481 |
|
|
`endif
|
| 482 |
|
|
|
| 483 |
|
|
|
| 484 |
|
|
`ifdef XILINX_SPARTAN6_FPGA
|
| 485 |
|
|
// -------------------------------------------------------------
|
| 486 |
|
|
// Instantiate Wishbone to Xilinx Spartan-6 DDR3 Bridge
|
| 487 |
|
|
// -------------------------------------------------------------
|
| 488 |
|
|
// The clock crossing fifo for spartan-6 is build into the mcb
|
| 489 |
|
|
wb_xs6_ddr3_bridge u_wb_xs6_ddr3_bridge (
|
| 490 |
|
|
.i_clk ( sys_clk ),
|
| 491 |
|
|
|
| 492 |
|
|
.o_cmd_en ( c3_p0_cmd_en ),
|
| 493 |
|
|
.o_cmd_instr ( c3_p0_cmd_instr ),
|
| 494 |
|
|
.o_cmd_byte_addr ( c3_p0_cmd_byte_addr ),
|
| 495 |
|
|
.i_cmd_full ( c3_p0_cmd_full ),
|
| 496 |
|
|
.i_wr_full ( c3_p0_wr_full ),
|
| 497 |
|
|
.o_wr_en ( c3_p0_wr_en ),
|
| 498 |
|
|
.o_wr_mask ( c3_p0_wr_mask ),
|
| 499 |
|
|
.o_wr_data ( c3_p0_wr_data ),
|
| 500 |
|
|
.i_rd_data ( c3_p0_rd_data ),
|
| 501 |
|
|
.i_rd_empty ( c3_p0_rd_empty ),
|
| 502 |
|
|
|
| 503 |
11 |
csantifort |
.i_mem_ctrl ( test_mem_ctrl ),
|
| 504 |
2 |
csantifort |
.i_wb_adr ( s_wb_adr [2] ),
|
| 505 |
|
|
.i_wb_sel ( s_wb_sel [2] ),
|
| 506 |
|
|
.i_wb_we ( s_wb_we [2] ),
|
| 507 |
|
|
.o_wb_dat ( s_wb_dat_r[2] ),
|
| 508 |
|
|
.i_wb_dat ( s_wb_dat_w[2] ),
|
| 509 |
|
|
.i_wb_cyc ( s_wb_cyc [2] ),
|
| 510 |
|
|
.i_wb_stb ( s_wb_stb [2] ),
|
| 511 |
|
|
.o_wb_ack ( s_wb_ack [2] ),
|
| 512 |
|
|
.o_wb_err ( s_wb_err [2] )
|
| 513 |
|
|
);
|
| 514 |
|
|
|
| 515 |
|
|
|
| 516 |
|
|
// -------------------------------------------------------------
|
| 517 |
|
|
// Instantiate Xilinx Spartan-6 FPGA MCB-DDR3 Controller
|
| 518 |
|
|
// -------------------------------------------------------------
|
| 519 |
|
|
mcb_ddr3 u_mcb_ddr3 (
|
| 520 |
|
|
|
| 521 |
|
|
// DDR3 signals
|
| 522 |
|
|
.mcb3_dram_dq ( ddr3_dq ),
|
| 523 |
|
|
.mcb3_dram_a ( ddr3_addr ),
|
| 524 |
|
|
.mcb3_dram_ba ( ddr3_ba ),
|
| 525 |
|
|
.mcb3_dram_ras_n ( ddr3_ras_n ),
|
| 526 |
|
|
.mcb3_dram_cas_n ( ddr3_cas_n ),
|
| 527 |
|
|
.mcb3_dram_we_n ( ddr3_we_n ),
|
| 528 |
|
|
.mcb3_dram_odt ( ddr3_odt ),
|
| 529 |
|
|
.mcb3_dram_reset_n ( ddr3_reset_n ),
|
| 530 |
|
|
.mcb3_dram_cke ( ddr3_cke ),
|
| 531 |
|
|
.mcb3_dram_udm ( ddr3_dm[1] ),
|
| 532 |
|
|
.mcb3_dram_dm ( ddr3_dm[0] ),
|
| 533 |
|
|
.mcb3_rzq ( mcb3_rzq ),
|
| 534 |
|
|
.mcb3_zio ( mcb3_zio ),
|
| 535 |
|
|
.mcb3_dram_udqs ( ddr3_dqs_p[1] ),
|
| 536 |
|
|
.mcb3_dram_dqs ( ddr3_dqs_p[0] ),
|
| 537 |
|
|
.mcb3_dram_udqs_n ( ddr3_dqs_n[1] ),
|
| 538 |
|
|
.mcb3_dram_dqs_n ( ddr3_dqs_n[0] ),
|
| 539 |
|
|
.mcb3_dram_ck ( ddr3_ck_p ),
|
| 540 |
|
|
.mcb3_dram_ck_n ( ddr3_ck_n ),
|
| 541 |
|
|
|
| 542 |
|
|
.sys_clk_ibufg ( clk_200 ),
|
| 543 |
|
|
.c3_sys_rst_n ( brd_rst ),
|
| 544 |
|
|
|
| 545 |
|
|
.c3_calib_done ( phy_init_done ),
|
| 546 |
|
|
|
| 547 |
|
|
.c3_p0_cmd_clk ( sys_clk ),
|
| 548 |
|
|
|
| 549 |
|
|
.c3_p0_cmd_en ( c3_p0_cmd_en ),
|
| 550 |
|
|
.c3_p0_cmd_instr ( c3_p0_cmd_instr ),
|
| 551 |
|
|
.c3_p0_cmd_bl ( 6'd0 ),
|
| 552 |
|
|
.c3_p0_cmd_byte_addr ( c3_p0_cmd_byte_addr ),
|
| 553 |
|
|
.c3_p0_cmd_empty ( ),
|
| 554 |
|
|
.c3_p0_cmd_full ( c3_p0_cmd_full ),
|
| 555 |
|
|
|
| 556 |
|
|
.c3_p0_wr_clk ( sys_clk ),
|
| 557 |
|
|
|
| 558 |
|
|
.c3_p0_wr_en ( c3_p0_wr_en ),
|
| 559 |
|
|
.c3_p0_wr_mask ( c3_p0_wr_mask ),
|
| 560 |
|
|
.c3_p0_wr_data ( c3_p0_wr_data ),
|
| 561 |
|
|
.c3_p0_wr_full ( c3_p0_wr_full ),
|
| 562 |
|
|
.c3_p0_wr_empty ( ),
|
| 563 |
|
|
.c3_p0_wr_count ( ),
|
| 564 |
|
|
.c3_p0_wr_underrun ( ),
|
| 565 |
|
|
.c3_p0_wr_error ( ),
|
| 566 |
|
|
|
| 567 |
|
|
.c3_p0_rd_clk ( sys_clk ),
|
| 568 |
|
|
|
| 569 |
|
|
.c3_p0_rd_en ( 1'd1 ),
|
| 570 |
|
|
.c3_p0_rd_data ( c3_p0_rd_data ),
|
| 571 |
|
|
.c3_p0_rd_full ( ),
|
| 572 |
|
|
.c3_p0_rd_empty ( c3_p0_rd_empty ),
|
| 573 |
|
|
.c3_p0_rd_count ( ),
|
| 574 |
|
|
.c3_p0_rd_overflow ( ),
|
| 575 |
|
|
.c3_p0_rd_error ( )
|
| 576 |
|
|
);
|
| 577 |
|
|
`endif
|
| 578 |
|
|
|
| 579 |
|
|
|
| 580 |
|
|
`ifdef XILINX_VIRTEX6_FPGA
|
| 581 |
|
|
// -------------------------------------------------------------
|
| 582 |
|
|
// Instantiate Wishbone to Xilinx Spartan-6 DDR3 Bridge
|
| 583 |
|
|
// -------------------------------------------------------------
|
| 584 |
|
|
// The clock crossing fifo for virtex-6 is insode the bridge
|
| 585 |
|
|
// module
|
| 586 |
|
|
wb_xv6_ddr3_bridge u_wb_xv6_ddr3_bridge (
|
| 587 |
|
|
.i_sys_clk ( sys_clk ),
|
| 588 |
|
|
.i_ddr_clk ( xv6_ddr3_clk ),
|
| 589 |
|
|
|
| 590 |
|
|
.o_ddr_cmd_en ( xv6_cmd_en ),
|
| 591 |
|
|
.o_ddr_cmd_instr ( xv6_cmd_instr ),
|
| 592 |
|
|
.o_ddr_cmd_byte_addr ( xv6_cmd_byte_addr ),
|
| 593 |
|
|
.i_ddr_cmd_full ( xv6_cmd_full ),
|
| 594 |
|
|
|
| 595 |
|
|
.i_ddr_wr_full ( xv6_wr_full ),
|
| 596 |
|
|
.o_ddr_wr_en ( xv6_wr_en ),
|
| 597 |
|
|
.o_ddr_wr_end ( xv6_wr_end ),
|
| 598 |
|
|
.o_ddr_wr_mask ( xv6_wr_mask ),
|
| 599 |
|
|
.o_ddr_wr_data ( xv6_wr_data ),
|
| 600 |
|
|
|
| 601 |
|
|
.i_ddr_rd_data ( xv6_rd_data ),
|
| 602 |
|
|
.i_ddr_rd_valid ( xv6_rd_data_valid ),
|
| 603 |
|
|
|
| 604 |
|
|
.i_phy_init_done ( phy_init_done1 ),
|
| 605 |
|
|
.o_phy_init_done ( phy_init_done ), // delayed version
|
| 606 |
|
|
|
| 607 |
11 |
csantifort |
.i_mem_ctrl ( test_mem_ctrl ),
|
| 608 |
2 |
csantifort |
.i_wb_adr ( s_wb_adr [2] ),
|
| 609 |
|
|
.i_wb_sel ( s_wb_sel [2] ),
|
| 610 |
|
|
.i_wb_we ( s_wb_we [2] ),
|
| 611 |
|
|
.o_wb_dat ( s_wb_dat_r[2] ),
|
| 612 |
|
|
.i_wb_dat ( s_wb_dat_w[2] ),
|
| 613 |
|
|
.i_wb_cyc ( s_wb_cyc [2] ),
|
| 614 |
|
|
.i_wb_stb ( s_wb_stb [2] ),
|
| 615 |
|
|
.o_wb_ack ( s_wb_ack [2] ),
|
| 616 |
|
|
.o_wb_err ( s_wb_err [2] )
|
| 617 |
|
|
);
|
| 618 |
|
|
|
| 619 |
|
|
|
| 620 |
|
|
// -------------------------------------------------------------
|
| 621 |
|
|
// Instantiate Xilinx Virtex-6 FPGA DDR3 Controller
|
| 622 |
|
|
// -------------------------------------------------------------
|
| 623 |
|
|
xv6_ddr3
|
| 624 |
|
|
#( // - Skip the memory initilization sequence,
|
| 625 |
|
|
.SIM_INIT_OPTION ("SKIP_PU_DLY" ),
|
| 626 |
|
|
// - Skip the delay Calibration process
|
| 627 |
|
|
.SIM_CAL_OPTION ("FAST_CAL" ),
|
| 628 |
|
|
.RST_ACT_LOW ( 0 )
|
| 629 |
|
|
)
|
| 630 |
|
|
u_xv6_ddr3 (
|
| 631 |
|
|
// DDR3 signals
|
| 632 |
|
|
.ddr3_dq ( ddr3_dq ),
|
| 633 |
|
|
.ddr3_addr ( ddr3_addr ),
|
| 634 |
|
|
.ddr3_ba ( ddr3_ba ),
|
| 635 |
|
|
.ddr3_ras_n ( ddr3_ras_n ),
|
| 636 |
|
|
.ddr3_cas_n ( ddr3_cas_n ),
|
| 637 |
|
|
.ddr3_we_n ( ddr3_we_n ),
|
| 638 |
|
|
.ddr3_odt ( ddr3_odt ),
|
| 639 |
|
|
.ddr3_reset_n ( ddr3_reset_n ),
|
| 640 |
|
|
.ddr3_cke ( ddr3_cke ),
|
| 641 |
|
|
.ddr3_dm ( ddr3_dm ),
|
| 642 |
|
|
.ddr3_dqs_p ( ddr3_dqs_p ),
|
| 643 |
|
|
.ddr3_dqs_n ( ddr3_dqs_n ),
|
| 644 |
|
|
.ddr3_ck_p ( ddr3_ck_p ),
|
| 645 |
|
|
.ddr3_ck_n ( ddr3_ck_n ),
|
| 646 |
|
|
.ddr3_cs_n ( ddr3_cs_n ),
|
| 647 |
|
|
|
| 648 |
|
|
// DDR clock
|
| 649 |
|
|
.sys_clk_p ( sys_clk_p ),
|
| 650 |
|
|
.sys_clk_n ( sys_clk_n ),
|
| 651 |
|
|
.clk_ref ( clk_200 ),
|
| 652 |
|
|
.sys_rst ( brd_rst ),
|
| 653 |
|
|
.tb_rst ( ),
|
| 654 |
|
|
.tb_clk ( xv6_ddr3_clk ),
|
| 655 |
|
|
.phy_init_done ( phy_init_done1 ),
|
| 656 |
|
|
|
| 657 |
|
|
.app_en ( xv6_cmd_en ),
|
| 658 |
|
|
.app_cmd ( xv6_cmd_instr ),
|
| 659 |
|
|
.tg_addr ( xv6_cmd_byte_addr ),
|
| 660 |
|
|
.app_full ( xv6_cmd_full ),
|
| 661 |
|
|
|
| 662 |
|
|
.app_wdf_wren ( xv6_wr_en ),
|
| 663 |
|
|
.app_wdf_mask ( xv6_wr_mask ),
|
| 664 |
|
|
.app_wdf_data ( xv6_wr_data ),
|
| 665 |
|
|
.app_wdf_end ( xv6_wr_end ),
|
| 666 |
|
|
.app_wdf_full ( xv6_wr_full ),
|
| 667 |
|
|
|
| 668 |
|
|
.app_rd_data ( xv6_rd_data ),
|
| 669 |
|
|
.app_rd_data_valid ( xv6_rd_data_valid )
|
| 670 |
|
|
);
|
| 671 |
|
|
|
| 672 |
|
|
`endif
|
| 673 |
|
|
|
| 674 |
|
|
|
| 675 |
|
|
|
| 676 |
|
|
// -------------------------------------------------------------
|
| 677 |
|
|
// Instantiate Wishbone Arbiter
|
| 678 |
|
|
// -------------------------------------------------------------
|
| 679 |
|
|
wishbone_arbiter u_wishbone_arbiter (
|
| 680 |
|
|
.i_wb_clk ( sys_clk ),
|
| 681 |
|
|
|
| 682 |
|
|
// WISHBONE master 0 - Ethmac
|
| 683 |
|
|
.i_m0_wb_adr ( m_wb_adr [0] ),
|
| 684 |
|
|
.i_m0_wb_sel ( m_wb_sel [0] ),
|
| 685 |
|
|
.i_m0_wb_we ( m_wb_we [0] ),
|
| 686 |
|
|
.o_m0_wb_dat ( m_wb_dat_r [0] ),
|
| 687 |
|
|
.i_m0_wb_dat ( m_wb_dat_w [0] ),
|
| 688 |
|
|
.i_m0_wb_cyc ( m_wb_cyc [0] ),
|
| 689 |
|
|
.i_m0_wb_stb ( m_wb_stb [0] ),
|
| 690 |
|
|
.o_m0_wb_ack ( m_wb_ack [0] ),
|
| 691 |
|
|
.o_m0_wb_err ( m_wb_err [0] ),
|
| 692 |
|
|
|
| 693 |
|
|
|
| 694 |
|
|
// WISHBONE master 1 - Amber Process or
|
| 695 |
|
|
.i_m1_wb_adr ( m_wb_adr [1] ),
|
| 696 |
|
|
.i_m1_wb_sel ( m_wb_sel [1] ),
|
| 697 |
|
|
.i_m1_wb_we ( m_wb_we [1] ),
|
| 698 |
|
|
.o_m1_wb_dat ( m_wb_dat_r [1] ),
|
| 699 |
|
|
.i_m1_wb_dat ( m_wb_dat_w [1] ),
|
| 700 |
|
|
.i_m1_wb_cyc ( m_wb_cyc [1] ),
|
| 701 |
|
|
.i_m1_wb_stb ( m_wb_stb [1] ),
|
| 702 |
|
|
.o_m1_wb_ack ( m_wb_ack [1] ),
|
| 703 |
|
|
.o_m1_wb_err ( m_wb_err [1] ),
|
| 704 |
|
|
|
| 705 |
|
|
|
| 706 |
|
|
// WISHBONE slave 0 - Ethmac
|
| 707 |
|
|
.o_s0_wb_adr ( s_wb_adr [0] ),
|
| 708 |
|
|
.o_s0_wb_sel ( s_wb_sel [0] ),
|
| 709 |
|
|
.o_s0_wb_we ( s_wb_we [0] ),
|
| 710 |
|
|
.i_s0_wb_dat ( s_wb_dat_r [0] ),
|
| 711 |
|
|
.o_s0_wb_dat ( s_wb_dat_w [0] ),
|
| 712 |
|
|
.o_s0_wb_cyc ( s_wb_cyc [0] ),
|
| 713 |
|
|
.o_s0_wb_stb ( s_wb_stb [0] ),
|
| 714 |
|
|
.i_s0_wb_ack ( s_wb_ack [0] ),
|
| 715 |
|
|
.i_s0_wb_err ( s_wb_err [0] ),
|
| 716 |
|
|
|
| 717 |
|
|
|
| 718 |
|
|
// WISHBONE slave 1 - Boot Memory
|
| 719 |
|
|
.o_s1_wb_adr ( s_wb_adr [1] ),
|
| 720 |
|
|
.o_s1_wb_sel ( s_wb_sel [1] ),
|
| 721 |
|
|
.o_s1_wb_we ( s_wb_we [1] ),
|
| 722 |
|
|
.i_s1_wb_dat ( s_wb_dat_r [1] ),
|
| 723 |
|
|
.o_s1_wb_dat ( s_wb_dat_w [1] ),
|
| 724 |
|
|
.o_s1_wb_cyc ( s_wb_cyc [1] ),
|
| 725 |
|
|
.o_s1_wb_stb ( s_wb_stb [1] ),
|
| 726 |
|
|
.i_s1_wb_ack ( s_wb_ack [1] ),
|
| 727 |
|
|
.i_s1_wb_err ( s_wb_err [1] ),
|
| 728 |
|
|
|
| 729 |
|
|
|
| 730 |
|
|
// WISHBONE slave 2 - Main Memory
|
| 731 |
|
|
.o_s2_wb_adr ( s_wb_adr [2] ),
|
| 732 |
|
|
.o_s2_wb_sel ( s_wb_sel [2] ),
|
| 733 |
|
|
.o_s2_wb_we ( s_wb_we [2] ),
|
| 734 |
|
|
.i_s2_wb_dat ( s_wb_dat_r [2] ),
|
| 735 |
|
|
.o_s2_wb_dat ( s_wb_dat_w [2] ),
|
| 736 |
|
|
.o_s2_wb_cyc ( s_wb_cyc [2] ),
|
| 737 |
|
|
.o_s2_wb_stb ( s_wb_stb [2] ),
|
| 738 |
|
|
.i_s2_wb_ack ( s_wb_ack [2] ),
|
| 739 |
|
|
.i_s2_wb_err ( s_wb_err [2] ),
|
| 740 |
|
|
|
| 741 |
|
|
|
| 742 |
|
|
// WISHBONE slave 3 - UART 0
|
| 743 |
|
|
.o_s3_wb_adr ( s_wb_adr [3] ),
|
| 744 |
|
|
.o_s3_wb_sel ( s_wb_sel [3] ),
|
| 745 |
|
|
.o_s3_wb_we ( s_wb_we [3] ),
|
| 746 |
|
|
.i_s3_wb_dat ( s_wb_dat_r [3] ),
|
| 747 |
|
|
.o_s3_wb_dat ( s_wb_dat_w [3] ),
|
| 748 |
|
|
.o_s3_wb_cyc ( s_wb_cyc [3] ),
|
| 749 |
|
|
.o_s3_wb_stb ( s_wb_stb [3] ),
|
| 750 |
|
|
.i_s3_wb_ack ( s_wb_ack [3] ),
|
| 751 |
|
|
.i_s3_wb_err ( s_wb_err [3] ),
|
| 752 |
|
|
|
| 753 |
|
|
|
| 754 |
|
|
// WISHBONE slave 4 - UART 1
|
| 755 |
|
|
.o_s4_wb_adr ( s_wb_adr [4] ),
|
| 756 |
|
|
.o_s4_wb_sel ( s_wb_sel [4] ),
|
| 757 |
|
|
.o_s4_wb_we ( s_wb_we [4] ),
|
| 758 |
|
|
.i_s4_wb_dat ( s_wb_dat_r [4] ),
|
| 759 |
|
|
.o_s4_wb_dat ( s_wb_dat_w [4] ),
|
| 760 |
|
|
.o_s4_wb_cyc ( s_wb_cyc [4] ),
|
| 761 |
|
|
.o_s4_wb_stb ( s_wb_stb [4] ),
|
| 762 |
|
|
.i_s4_wb_ack ( s_wb_ack [4] ),
|
| 763 |
|
|
.i_s4_wb_err ( s_wb_err [4] ),
|
| 764 |
|
|
|
| 765 |
|
|
|
| 766 |
|
|
// WISHBONE slave 5 - Test Module
|
| 767 |
|
|
.o_s5_wb_adr ( s_wb_adr [5] ),
|
| 768 |
|
|
.o_s5_wb_sel ( s_wb_sel [5] ),
|
| 769 |
|
|
.o_s5_wb_we ( s_wb_we [5] ),
|
| 770 |
|
|
.i_s5_wb_dat ( s_wb_dat_r [5] ),
|
| 771 |
|
|
.o_s5_wb_dat ( s_wb_dat_w [5] ),
|
| 772 |
|
|
.o_s5_wb_cyc ( s_wb_cyc [5] ),
|
| 773 |
|
|
.o_s5_wb_stb ( s_wb_stb [5] ),
|
| 774 |
|
|
.i_s5_wb_ack ( s_wb_ack [5] ),
|
| 775 |
|
|
.i_s5_wb_err ( s_wb_err [5] ),
|
| 776 |
|
|
|
| 777 |
|
|
|
| 778 |
|
|
// WISHBONE slave 6 - Timer Module
|
| 779 |
|
|
.o_s6_wb_adr ( s_wb_adr [6] ),
|
| 780 |
|
|
.o_s6_wb_sel ( s_wb_sel [6] ),
|
| 781 |
|
|
.o_s6_wb_we ( s_wb_we [6] ),
|
| 782 |
|
|
.i_s6_wb_dat ( s_wb_dat_r [6] ),
|
| 783 |
|
|
.o_s6_wb_dat ( s_wb_dat_w [6] ),
|
| 784 |
|
|
.o_s6_wb_cyc ( s_wb_cyc [6] ),
|
| 785 |
|
|
.o_s6_wb_stb ( s_wb_stb [6] ),
|
| 786 |
|
|
.i_s6_wb_ack ( s_wb_ack [6] ),
|
| 787 |
|
|
.i_s6_wb_err ( s_wb_err [6] ),
|
| 788 |
|
|
|
| 789 |
|
|
|
| 790 |
|
|
// WISHBONE slave 7 - Interrupt Controller
|
| 791 |
|
|
.o_s7_wb_adr ( s_wb_adr [7] ),
|
| 792 |
|
|
.o_s7_wb_sel ( s_wb_sel [7] ),
|
| 793 |
|
|
.o_s7_wb_we ( s_wb_we [7] ),
|
| 794 |
|
|
.i_s7_wb_dat ( s_wb_dat_r [7] ),
|
| 795 |
|
|
.o_s7_wb_dat ( s_wb_dat_w [7] ),
|
| 796 |
|
|
.o_s7_wb_cyc ( s_wb_cyc [7] ),
|
| 797 |
|
|
.o_s7_wb_stb ( s_wb_stb [7] ),
|
| 798 |
|
|
.i_s7_wb_ack ( s_wb_ack [7] ),
|
| 799 |
|
|
.i_s7_wb_err ( s_wb_err [7] )
|
| 800 |
|
|
);
|
| 801 |
|
|
|
| 802 |
|
|
|
| 803 |
|
|
|
| 804 |
|
|
endmodule
|
| 805 |
|
|
|
