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//////////////////////////////////////////////////////////////////
//                                                              //
//  Test Module                                                 //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Contains a random number generator and a couple of timers   //
//  that connect to interrupt lines. Used for testing the       //
//  ssytem.                                                     //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
 
module test_module (
input                       i_clk,
 
output                      o_irq,
output                      o_firq,
 
input       [31:0]          i_wb_adr,
input       [3:0]           i_wb_sel,
input                       i_wb_we,
output      [31:0]          o_wb_dat,
input       [31:0]          i_wb_dat,
input                       i_wb_cyc,
input                       i_wb_stb,
output                      o_wb_ack,
output                      o_wb_err
 
 
);
 
`include "register_addresses.v"
 
 
reg [7:0]       firq_timer          = 'd0;
reg [7:0]       irq_timer           = 'd0;
reg [7:0]       random_num          = 8'hf3;
 
//synopsys translate_off
reg [1:0]       tb_uart_control_reg = 'd0;
reg [1:0]       tb_uart_status_reg  = 'd0;
reg             tb_uart_push        = 'd0;
reg [7:0]       tb_uart_txd_reg     = 'd0;
//synopsys translate_on
 
reg [1:0]       sim_ctrl_reg        = 'd0; // 1,2 = simulation, 0 = fpga
reg [31:0]      test_status_reg     = 'd0;
reg             test_status_set     = 'd0; // used to terminate tests
 
wire            wb_start_write;
wire            wb_start_read;
reg             wb_start_read_d1    = 'd0;
reg  [31:0]     wb_rdata            = 'd0;
 
// Can't start a write while a read is completing. The ack for the read cycle
// needs to be sent first
assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
assign wb_start_read  = i_wb_stb && !i_wb_we && !o_wb_ack;
 
always @( posedge i_clk )
    wb_start_read_d1 <= wb_start_read;
 
assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
assign o_wb_err = 1'd0;
assign o_wb_dat = wb_rdata;
 
 
// ========================================================
// Register Reads
// ========================================================
always @( posedge i_clk )
    if ( wb_start_read )
        case ( i_wb_adr[15:0] )
            AMBER_TEST_STATUS:           wb_rdata <= test_status_reg;
            AMBER_TEST_FIRQ_TIMER:        wb_rdata <= {24'd0, firq_timer};
            AMBER_TEST_IRQ_TIMER:        wb_rdata <= {24'd0, irq_timer};
            AMBER_TEST_RANDOM_NUM:       wb_rdata <= {24'd0, random_num};
 
            /* Allow access to the random register over
               a 16-word address range to load a series
               of random numbers using lmd instruction. */
            AMBER_TEST_RANDOM_NUM00: wb_rdata <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM01: wb_rdata <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM02: wb_rdata <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM03: wb_rdata <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM04: wb_rdata <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM05: wb_rdata <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM06: wb_rdata <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM07: wb_rdata <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM08: wb_rdata <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM09: wb_rdata <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM10: wb_rdata <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM11: wb_rdata <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM12: wb_rdata <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM13: wb_rdata <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM14: wb_rdata <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM15: wb_rdata <= {24'd0, random_num};
 
            //synopsys translate_off
            AMBER_TEST_UART_CONTROL:     wb_rdata <= {30'd0, tb_uart_control_reg};
            AMBER_TEST_UART_STATUS:      wb_rdata <= {30'd0, tb_uart_status_reg};
            AMBER_TEST_UART_TXD:         wb_rdata <= {24'd0, tb_uart_txd_reg};
            //synopsys translate_on
 
            AMBER_TEST_SIM_CTRL:         wb_rdata <= {30'd0, sim_ctrl_reg};
            default:                     wb_rdata <= 32'haabbccdd;
 
        endcase
 
 
// ======================================
// Simulation bit
// ======================================
 
// This register bit is a 1 in simulation but a 0 in the real fpga
// Used by software to tell the difference    
//synopsys translate_off
 
`ifndef AMBER_SIM_CTRL
    `define AMBER_SIM_CTRL 0
`endif
 
always @( posedge i_clk )
    begin
    // Value reads as 1 in simulation, and zero in the FPGA
    sim_ctrl_reg <= 2'd `AMBER_SIM_CTRL ;
    end
//synopsys translate_on
 
 
// ======================================
// Interrupts
// ======================================
assign o_irq  = irq_timer  == 8'd1;
assign o_firq = firq_timer == 8'd1;
 
 
// ======================================
// FIRQ Timer Register
// ======================================
    // Write a value > 1 to set the firq timer
    // Write 0 to clear it
always @( posedge i_clk )
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_FIRQ_TIMER )
        firq_timer <= i_wb_dat[7:0];
    else if ( firq_timer > 8'd1 )
        firq_timer <= firq_timer - 1'd1;
 
 
// ======================================
// IRQ Timer Register
// ======================================
    // Write a value > 1 to set the irq timer
    // Write 0 to clear it
always @( posedge i_clk )
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_IRQ_TIMER )
        irq_timer <= i_wb_dat[7:0];
    else if ( irq_timer > 8'd1 )
        irq_timer <= irq_timer - 1'd1;
 
 
// ======================================
// Random Number Generator Register
// ======================================
// Write a value > 1 to set the irq timer
// Write 0 to clear it
always @( posedge i_clk )
    begin
    if ( wb_start_write && i_wb_adr[15:8] == AMBER_TEST_RANDOM_NUM[15:8] )
        random_num <= i_wb_dat[7:0];
 
    // generate a new random number on every read access
    else if ( wb_start_read && i_wb_adr[15:8] == AMBER_TEST_RANDOM_NUM[15:8] )
        random_num <= { random_num[3]^random_num[1],
                        random_num[0]^random_num[5],
                        ~random_num[7]^random_num[4],
                        ~random_num[2],
                        random_num[6],
                        random_num[4]^~random_num[3],
                        random_num[7]^~random_num[1],
                        random_num[7]
                      };
    end
 
 
// ======================================
// Test Status Write
// ======================================
always @( posedge i_clk )
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )
        test_status_reg <= i_wb_dat;
 
 
// ======================================
// Test Status Write
// ======================================
always @( posedge i_clk )
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )
        test_status_set <= 1'd1;
 
 
// ======================================
// Test UART registers
// ======================================
// These control the testbench UART, not the real
// UART in system
 
//synopsys translate_off
always @( posedge i_clk )
    begin
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_UART_CONTROL )
        tb_uart_control_reg <= i_wb_dat[1:0];
 
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_UART_TXD )
        begin
        tb_uart_txd_reg   <= i_wb_dat[7:0];
        tb_uart_push      <= !tb_uart_push;
        end
    end
//synopsys translate_on
 
 
 
endmodule
 

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[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [test_module.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Test Module //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Contains a random number generator and a couple of timers //`
10			`// that connect to interrupt lines. Used for testing the //`
11			`// ssytem. //`
12			`// //`
13			`// Author(s): //`
14			`// - Conor Santifort, csantifort.amber@gmail.com //`
15			`// //`
16			`//////////////////////////////////////////////////////////////////`
17			`// //`
18			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
19			`// //`
20			`// This source file may be used and distributed without //`
21			`// restriction provided that this copyright statement is not //`
22			`// removed from the file and that any derivative work contains //`
23			`// the original copyright notice and the associated disclaimer. //`
24			`// //`
25			`// This source file is free software; you can redistribute it //`
26			`// and/or modify it under the terms of the GNU Lesser General //`
27			`// Public License as published by the Free Software Foundation; //`
28			`// either version 2.1 of the License, or (at your option) any //`
29			`// later version. //`
30			`// //`
31			`// This source is distributed in the hope that it will be //`
32			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
33			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
34			`// PURPOSE. See the GNU Lesser General Public License for more //`
35			`// details. //`
36			`// //`
37			`// You should have received a copy of the GNU Lesser General //`
38			`// Public License along with this source; if not, download it //`
39			`// from http://www.opencores.org/lgpl.shtml //`
40			`// //`
41			`//////////////////////////////////////////////////////////////////`
42
43
44			`module test_module (`
45			`input i_clk,`
46
47			`output o_irq,`
48			`output o_firq,`
49
50			`input [31:0] i_wb_adr,`
51			`input [3:0] i_wb_sel,`
52			`input i_wb_we,`
53			`output [31:0] o_wb_dat,`
54			`input [31:0] i_wb_dat,`
55			`input i_wb_cyc,`
56			`input i_wb_stb,`
57			`output o_wb_ack,`
58			`output o_wb_err`
59
60
61			`);`
62
63			`include "register_addresses.v"
64
65
66			`reg [7:0] firq_timer = 'd0;`
67			`reg [7:0] irq_timer = 'd0;`
68			`reg [7:0] random_num = 8'hf3;`
69
70			`//synopsys translate_off`
71			`reg [1:0] tb_uart_control_reg = 'd0;`
72			`reg [1:0] tb_uart_status_reg = 'd0;`
73			`reg tb_uart_push = 'd0;`
74			`reg [7:0] tb_uart_txd_reg = 'd0;`
75			`//synopsys translate_on`
76
77			`reg [1:0] sim_ctrl_reg = 'd0; // 1,2 = simulation, 0 = fpga`
78			`reg [31:0] test_status_reg = 'd0;`
79			`reg test_status_set = 'd0; // used to terminate tests`
80
81			`wire wb_start_write;`
82			`wire wb_start_read;`
83			`reg wb_start_read_d1 = 'd0;`
84			`reg [31:0] wb_rdata = 'd0;`
85
86			`// Can't start a write while a read is completing. The ack for the read cycle`
87			`// needs to be sent first`
88			`assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;`
89			`assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;`
90
91			`always @( posedge i_clk )`
92			`wb_start_read_d1 <= wb_start_read;`
93
94			`assign o_wb_ack = i_wb_stb && ( wb_start_write \|\| wb_start_read_d1 );`
95			`assign o_wb_err = 1'd0;`
96			`assign o_wb_dat = wb_rdata;`
97
98
99			`// ========================================================`
100			`// Register Reads`
101			`// ========================================================`
102			`always @( posedge i_clk )`
103			`if ( wb_start_read )`
104			`case ( i_wb_adr[15:0] )`
105			`AMBER_TEST_STATUS: wb_rdata <= test_status_reg;`
106			`AMBER_TEST_FIRQ_TIMER: wb_rdata <= {24'd0, firq_timer};`
107			`AMBER_TEST_IRQ_TIMER: wb_rdata <= {24'd0, irq_timer};`
108			`AMBER_TEST_RANDOM_NUM: wb_rdata <= {24'd0, random_num};`
109
110			`/* Allow access to the random register over`
111			`a 16-word address range to load a series`
112			`of random numbers using lmd instruction. */`
113			`AMBER_TEST_RANDOM_NUM00: wb_rdata <= {24'd0, random_num};`
114			`AMBER_TEST_RANDOM_NUM01: wb_rdata <= {24'd0, random_num};`
115			`AMBER_TEST_RANDOM_NUM02: wb_rdata <= {24'd0, random_num};`
116			`AMBER_TEST_RANDOM_NUM03: wb_rdata <= {24'd0, random_num};`
117			`AMBER_TEST_RANDOM_NUM04: wb_rdata <= {24'd0, random_num};`
118			`AMBER_TEST_RANDOM_NUM05: wb_rdata <= {24'd0, random_num};`
119			`AMBER_TEST_RANDOM_NUM06: wb_rdata <= {24'd0, random_num};`
120			`AMBER_TEST_RANDOM_NUM07: wb_rdata <= {24'd0, random_num};`
121			`AMBER_TEST_RANDOM_NUM08: wb_rdata <= {24'd0, random_num};`
122			`AMBER_TEST_RANDOM_NUM09: wb_rdata <= {24'd0, random_num};`
123			`AMBER_TEST_RANDOM_NUM10: wb_rdata <= {24'd0, random_num};`
124			`AMBER_TEST_RANDOM_NUM11: wb_rdata <= {24'd0, random_num};`
125			`AMBER_TEST_RANDOM_NUM12: wb_rdata <= {24'd0, random_num};`
126			`AMBER_TEST_RANDOM_NUM13: wb_rdata <= {24'd0, random_num};`
127			`AMBER_TEST_RANDOM_NUM14: wb_rdata <= {24'd0, random_num};`
128			`AMBER_TEST_RANDOM_NUM15: wb_rdata <= {24'd0, random_num};`
129
130			`//synopsys translate_off`
131			`AMBER_TEST_UART_CONTROL: wb_rdata <= {30'd0, tb_uart_control_reg};`
132			`AMBER_TEST_UART_STATUS: wb_rdata <= {30'd0, tb_uart_status_reg};`
133			`AMBER_TEST_UART_TXD: wb_rdata <= {24'd0, tb_uart_txd_reg};`
134			`//synopsys translate_on`
135
136			`AMBER_TEST_SIM_CTRL: wb_rdata <= {30'd0, sim_ctrl_reg};`
137			`default: wb_rdata <= 32'haabbccdd;`
138
139			`endcase`
140
141
142			`// ======================================`
143			`// Simulation bit`
144			`// ======================================`
145
146			`// This register bit is a 1 in simulation but a 0 in the real fpga`
147			`// Used by software to tell the difference`
148			`//synopsys translate_off`
149
150			`ifndef AMBER_SIM_CTRL
151			`define AMBER_SIM_CTRL 0
152			`endif
153
154			`always @( posedge i_clk )`
155			`begin`
156			`// Value reads as 1 in simulation, and zero in the FPGA`
157			sim_ctrl_reg <= 2'd `AMBER_SIM_CTRL ;
158			`end`
159			`//synopsys translate_on`
160
161
162			`// ======================================`
163			`// Interrupts`
164			`// ======================================`
165			`assign o_irq = irq_timer == 8'd1;`
166			`assign o_firq = firq_timer == 8'd1;`
167
168
169			`// ======================================`
170			`// FIRQ Timer Register`
171			`// ======================================`
172			`// Write a value > 1 to set the firq timer`
173			`// Write 0 to clear it`
174			`always @( posedge i_clk )`
175			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_FIRQ_TIMER )`
176			`firq_timer <= i_wb_dat[7:0];`
177			`else if ( firq_timer > 8'd1 )`
178			`firq_timer <= firq_timer - 1'd1;`
179
180
181			`// ======================================`
182			`// IRQ Timer Register`
183			`// ======================================`
184			`// Write a value > 1 to set the irq timer`
185			`// Write 0 to clear it`
186			`always @( posedge i_clk )`
187			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_IRQ_TIMER )`
188			`irq_timer <= i_wb_dat[7:0];`
189			`else if ( irq_timer > 8'd1 )`
190			`irq_timer <= irq_timer - 1'd1;`
191
192
193			`// ======================================`
194			`// Random Number Generator Register`
195			`// ======================================`
196			`// Write a value > 1 to set the irq timer`
197			`// Write 0 to clear it`
198			`always @( posedge i_clk )`
199			`begin`
200			`if ( wb_start_write && i_wb_adr[15:8] == AMBER_TEST_RANDOM_NUM[15:8] )`
201			`random_num <= i_wb_dat[7:0];`
202
203			`// generate a new random number on every read access`
204			`else if ( wb_start_read && i_wb_adr[15:8] == AMBER_TEST_RANDOM_NUM[15:8] )`
205			`random_num <= { random_num[3]^random_num[1],`
206			`random_num[0]^random_num[5],`
207			`~random_num[7]^random_num[4],`
208			`~random_num[2],`
209			`random_num[6],`
210			`random_num[4]^~random_num[3],`
211			`random_num[7]^~random_num[1],`
212			`random_num[7]`
213			`};`
214			`end`
215
216
217			`// ======================================`
218			`// Test Status Write`
219			`// ======================================`
220			`always @( posedge i_clk )`
221			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )`
222			`test_status_reg <= i_wb_dat;`
223
224
225			`// ======================================`
226			`// Test Status Write`
227			`// ======================================`
228			`always @( posedge i_clk )`
229			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )`
230			`test_status_set <= 1'd1;`
231
232
233			`// ======================================`
234			`// Test UART registers`
235			`// ======================================`
236			`// These control the testbench UART, not the real`
237			`// UART in system`
238
239			`//synopsys translate_off`
240			`always @( posedge i_clk )`
241			`begin`
242			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_UART_CONTROL )`
243			`tb_uart_control_reg <= i_wb_dat[1:0];`
244
245			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_UART_TXD )`
246			`begin`
247			`tb_uart_txd_reg <= i_wb_dat[7:0];`
248			`tb_uart_push <= !tb_uart_push;`
249			`end`
250			`end`
251			`//synopsys translate_on`
252
253
254
255			`endmodule`
256