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//////////////////////////////////////////////////////////////////
//                                                              //
//  Test Module                                                 //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Contains a random number generator and a couple of timers   //
//  that connect to interrupt lines. Used for testing the       //
//  ssytem.                                                     //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
 
module test_module   #(
parameter WB_DWIDTH  = 32,
parameter WB_SWIDTH  = 4
)(
input                       i_clk,
 
output                      o_irq,
output                      o_firq,
output                      o_mem_ctrl,  // 0=128MB, 1=32MB
input       [31:0]          i_wb_adr,
input       [WB_SWIDTH-1:0] i_wb_sel,
input                       i_wb_we,
output      [WB_DWIDTH-1:0] o_wb_dat,
input       [WB_DWIDTH-1:0] i_wb_dat,
input                       i_wb_cyc,
input                       i_wb_stb,
output                      o_wb_ack,
output                      o_wb_err
 
 
);
 
`include "register_addresses.v"
 
 
reg [7:0]       firq_timer          = 'd0;
reg [7:0]       irq_timer           = 'd0;
reg [7:0]       random_num          = 8'hf3;
 
//synopsys translate_off
reg [1:0]       tb_uart_control_reg = 'd0;
reg [1:0]       tb_uart_status_reg  = 'd0;
reg             tb_uart_push        = 'd0;
reg [7:0]       tb_uart_txd_reg     = 'd0;
//synopsys translate_on
 
reg [2:0]       sim_ctrl_reg        = 'd0; // 0 = fpga, other values for simulations
reg             mem_ctrl_reg        = 'd0; // 0 = 128MB, 1 = 32MB main memory
reg [31:0]      test_status_reg     = 'd0;
reg             test_status_set     = 'd0; // used to terminate tests
reg [31:0]      cycles_reg          = 'd0;
 
wire            wb_start_write;
wire            wb_start_read;
reg             wb_start_read_d1    = 'd0;
reg  [31:0]     wb_rdata32          = 'd0;
wire [31:0]     wb_wdata32;
 
// Can't start a write while a read is completing. The ack for the read cycle
// needs to be sent first
assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
assign wb_start_read  = i_wb_stb && !i_wb_we && !o_wb_ack;
 
always @( posedge i_clk )
    wb_start_read_d1 <= wb_start_read;
 
assign o_wb_ack   = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
assign o_wb_err   = 1'd0;
assign o_mem_ctrl = mem_ctrl_reg;
 
 
generate
if (WB_DWIDTH == 128)
    begin : wb128
    assign wb_wdata32   = i_wb_adr[3:2] == 2'd3 ? i_wb_dat[127:96] :
                          i_wb_adr[3:2] == 2'd2 ? i_wb_dat[ 95:64] :
                          i_wb_adr[3:2] == 2'd1 ? i_wb_dat[ 63:32] :
                                                  i_wb_dat[ 31: 0] ;
 
    assign o_wb_dat    = {4{wb_rdata32}};
    end
else
    begin : wb32
    assign wb_wdata32  = i_wb_dat;
    assign o_wb_dat    = wb_rdata32;
    end
endgenerate
 
// ========================================================
// Register Reads
// ========================================================
always @( posedge i_clk )
    if ( wb_start_read )
        case ( i_wb_adr[15:0] )
            AMBER_TEST_STATUS:           wb_rdata32 <= test_status_reg;
            AMBER_TEST_FIRQ_TIMER:       wb_rdata32 <= {24'd0, firq_timer};
            AMBER_TEST_IRQ_TIMER:        wb_rdata32 <= {24'd0, irq_timer};
            AMBER_TEST_RANDOM_NUM:       wb_rdata32 <= {24'd0, random_num};
 
            /* Allow access to the random register over
               a 16-word address range to load a series
               of random numbers using lmd instruction. */
            AMBER_TEST_RANDOM_NUM00: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM01: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM02: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM03: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM04: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM05: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM06: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM07: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM08: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM09: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM10: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM11: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM12: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM13: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM14: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM15: wb_rdata32 <= {24'd0, random_num};
 
            //synopsys translate_off
            AMBER_TEST_UART_CONTROL:     wb_rdata32 <= {30'd0, tb_uart_control_reg};
            AMBER_TEST_UART_STATUS:      wb_rdata32 <= {30'd0, tb_uart_status_reg};
            AMBER_TEST_UART_TXD:         wb_rdata32 <= {24'd0, tb_uart_txd_reg};
            //synopsys translate_on
 
            AMBER_TEST_SIM_CTRL:         wb_rdata32 <= {29'd0, sim_ctrl_reg};
            AMBER_TEST_MEM_CTRL:         wb_rdata32 <= {31'd0, mem_ctrl_reg};
 
            AMBER_TEST_CYCLES:           wb_rdata32 <=  cycles_reg;
            default:                     wb_rdata32 <= 32'haabbccdd;
 
        endcase
 
 
// ======================================
// Simulation bit
// ======================================
 
// This register bit is a 1 in simulation but a 0 in the real fpga
// Used by software to tell the difference    
//synopsys translate_off
 
`ifndef AMBER_SIM_CTRL
    `define AMBER_SIM_CTRL 0
`endif
 
always @( posedge i_clk )
    begin
    // Value reads as 1 in simulation, and zero in the FPGA
    sim_ctrl_reg <= 3'd `AMBER_SIM_CTRL ;
    end
//synopsys translate_on
 
 
// ======================================
// Interrupts
// ======================================
assign o_irq  = irq_timer  == 8'd1;
assign o_firq = firq_timer == 8'd1;
 
 
// ======================================
// FIRQ Timer Register
// ======================================
    // Write a value > 1 to set the firq timer
    // Write 0 to clear it
always @( posedge i_clk )
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_FIRQ_TIMER )
        firq_timer <= wb_wdata32[7:0];
    else if ( firq_timer > 8'd1 )
        firq_timer <= firq_timer - 1'd1;
 
 
// ======================================
// IRQ Timer Register
// ======================================
    // Write a value > 1 to set the irq timer
    // Write 0 to clear it
always @( posedge i_clk )
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_IRQ_TIMER )
        irq_timer <= wb_wdata32[7:0];
    else if ( irq_timer > 8'd1 )
        irq_timer <= irq_timer - 1'd1;
 
 
// ======================================
// Random Number Generator Register
// ======================================
// Write a value > 1 to set the irq timer
// Write 0 to clear it
always @( posedge i_clk )
    begin
    if ( wb_start_write && i_wb_adr[15:8] == AMBER_TEST_RANDOM_NUM[15:8] )
        random_num <= wb_wdata32[7:0];
 
    // generate a new random number on every read access
    else if ( wb_start_read && i_wb_adr[15:8] == AMBER_TEST_RANDOM_NUM[15:8] )
        random_num <= { random_num[3]^random_num[1],
                        random_num[0]^random_num[5],
                        ~random_num[7]^random_num[4],
                        ~random_num[2],
                        random_num[6],
                        random_num[4]^~random_num[3],
                        random_num[7]^~random_num[1],
                        random_num[7]
                      };
    end
 
 
// ======================================
// Test Status Write
// ======================================
always @( posedge i_clk )
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )
        test_status_reg <= wb_wdata32;
 
 
// ======================================
// Test Status Write
// ======================================
always @( posedge i_clk )
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )
        test_status_set <= 1'd1;
 
// ======================================
// Cycles counter
// ======================================
always @( posedge i_clk )
    cycles_reg <= cycles_reg + 1'd1;
 
// ======================================
// Memory Configuration Register Write
// ======================================
always @( posedge i_clk )
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_MEM_CTRL )
        mem_ctrl_reg <= wb_wdata32[0];
 
 
// ======================================
// Test UART registers
// ======================================
// These control the testbench UART, not the real
// UART in system
 
//synopsys translate_off
always @( posedge i_clk )
    begin
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_UART_CONTROL )
        tb_uart_control_reg <= wb_wdata32[1:0];
 
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_UART_TXD )
        begin
        tb_uart_txd_reg   <= wb_wdata32[7:0];
        tb_uart_push      <= !tb_uart_push;
        end
    end
//synopsys translate_on
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	2	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Test Module //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Contains a random number generator and a couple of timers //`
10			`// that connect to interrupt lines. Used for testing the //`
11			`// ssytem. //`
12			`// //`
13			`// Author(s): //`
14			`// - Conor Santifort, csantifort.amber@gmail.com //`
15			`// //`
16			`//////////////////////////////////////////////////////////////////`
17			`// //`
18			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
19			`// //`
20			`// This source file may be used and distributed without //`
21			`// restriction provided that this copyright statement is not //`
22			`// removed from the file and that any derivative work contains //`
23			`// the original copyright notice and the associated disclaimer. //`
24			`// //`
25			`// This source file is free software; you can redistribute it //`
26			`// and/or modify it under the terms of the GNU Lesser General //`
27			`// Public License as published by the Free Software Foundation; //`
28			`// either version 2.1 of the License, or (at your option) any //`
29			`// later version. //`
30			`// //`
31			`// This source is distributed in the hope that it will be //`
32			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
33			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
34			`// PURPOSE. See the GNU Lesser General Public License for more //`
35			`// details. //`
36			`// //`
37			`// You should have received a copy of the GNU Lesser General //`
38			`// Public License along with this source; if not, download it //`
39			`// from http://www.opencores.org/lgpl.shtml //`
40			`// //`
41			`//////////////////////////////////////////////////////////////////`
42
43
44	35	csantifort	`module test_module #(`
45			`parameter WB_DWIDTH = 32,`
46			`parameter WB_SWIDTH = 4`
47			`)(`
48	2	csantifort	`input i_clk,`
49
50			`output o_irq,`
51			`output o_firq,`
52	11	csantifort	`output o_mem_ctrl, // 0=128MB, 1=32MB`
53	2	csantifort	`input [31:0] i_wb_adr,`
54	35	csantifort	`input [WB_SWIDTH-1:0] i_wb_sel,`
55	2	csantifort	`input i_wb_we,`
56	35	csantifort	`output [WB_DWIDTH-1:0] o_wb_dat,`
57			`input [WB_DWIDTH-1:0] i_wb_dat,`
58	2	csantifort	`input i_wb_cyc,`
59			`input i_wb_stb,`
60			`output o_wb_ack,`
61			`output o_wb_err`
62
63
64			`);`
65
66			`include "register_addresses.v"
67
68
69			`reg [7:0] firq_timer = 'd0;`
70			`reg [7:0] irq_timer = 'd0;`
71			`reg [7:0] random_num = 8'hf3;`
72
73			`//synopsys translate_off`
74			`reg [1:0] tb_uart_control_reg = 'd0;`
75			`reg [1:0] tb_uart_status_reg = 'd0;`
76			`reg tb_uart_push = 'd0;`
77			`reg [7:0] tb_uart_txd_reg = 'd0;`
78			`//synopsys translate_on`
79
80	11	csantifort	`reg [2:0] sim_ctrl_reg = 'd0; // 0 = fpga, other values for simulations`
81			`reg mem_ctrl_reg = 'd0; // 0 = 128MB, 1 = 32MB main memory`
82	2	csantifort	`reg [31:0] test_status_reg = 'd0;`
83			`reg test_status_set = 'd0; // used to terminate tests`
84	32	csantifort	`reg [31:0] cycles_reg = 'd0;`
85	2	csantifort
86			`wire wb_start_write;`
87			`wire wb_start_read;`
88			`reg wb_start_read_d1 = 'd0;`
89	35	csantifort	`reg [31:0] wb_rdata32 = 'd0;`
90			`wire [31:0] wb_wdata32;`
91	2	csantifort
92			`// Can't start a write while a read is completing. The ack for the read cycle`
93			`// needs to be sent first`
94			`assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;`
95			`assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;`
96
97			`always @( posedge i_clk )`
98			`wb_start_read_d1 <= wb_start_read;`
99
100	11	csantifort	`assign o_wb_ack = i_wb_stb && ( wb_start_write \|\| wb_start_read_d1 );`
101			`assign o_wb_err = 1'd0;`
102			`assign o_mem_ctrl = mem_ctrl_reg;`
103	2	csantifort
104	35	csantifort
105			`generate`
106			`if (WB_DWIDTH == 128)`
107			`begin : wb128`
108			`assign wb_wdata32 = i_wb_adr[3:2] == 2'd3 ? i_wb_dat[127:96] :`
109			`i_wb_adr[3:2] == 2'd2 ? i_wb_dat[ 95:64] :`
110			`i_wb_adr[3:2] == 2'd1 ? i_wb_dat[ 63:32] :`
111			`i_wb_dat[ 31: 0] ;`
112
113			`assign o_wb_dat = {4{wb_rdata32}};`
114			`end`
115			`else`
116			`begin : wb32`
117			`assign wb_wdata32 = i_wb_dat;`
118			`assign o_wb_dat = wb_rdata32;`
119			`end`
120			`endgenerate`
121
122	2	csantifort	`// ========================================================`
123			`// Register Reads`
124			`// ========================================================`
125			`always @( posedge i_clk )`
126			`if ( wb_start_read )`
127			`case ( i_wb_adr[15:0] )`
128	35	csantifort	`AMBER_TEST_STATUS: wb_rdata32 <= test_status_reg;`
129			`AMBER_TEST_FIRQ_TIMER: wb_rdata32 <= {24'd0, firq_timer};`
130			`AMBER_TEST_IRQ_TIMER: wb_rdata32 <= {24'd0, irq_timer};`
131			`AMBER_TEST_RANDOM_NUM: wb_rdata32 <= {24'd0, random_num};`
132	2	csantifort
133			`/* Allow access to the random register over`
134			`a 16-word address range to load a series`
135			`of random numbers using lmd instruction. */`
136	35	csantifort	`AMBER_TEST_RANDOM_NUM00: wb_rdata32 <= {24'd0, random_num};`
137			`AMBER_TEST_RANDOM_NUM01: wb_rdata32 <= {24'd0, random_num};`
138			`AMBER_TEST_RANDOM_NUM02: wb_rdata32 <= {24'd0, random_num};`
139			`AMBER_TEST_RANDOM_NUM03: wb_rdata32 <= {24'd0, random_num};`
140			`AMBER_TEST_RANDOM_NUM04: wb_rdata32 <= {24'd0, random_num};`
141			`AMBER_TEST_RANDOM_NUM05: wb_rdata32 <= {24'd0, random_num};`
142			`AMBER_TEST_RANDOM_NUM06: wb_rdata32 <= {24'd0, random_num};`
143			`AMBER_TEST_RANDOM_NUM07: wb_rdata32 <= {24'd0, random_num};`
144			`AMBER_TEST_RANDOM_NUM08: wb_rdata32 <= {24'd0, random_num};`
145			`AMBER_TEST_RANDOM_NUM09: wb_rdata32 <= {24'd0, random_num};`
146			`AMBER_TEST_RANDOM_NUM10: wb_rdata32 <= {24'd0, random_num};`
147			`AMBER_TEST_RANDOM_NUM11: wb_rdata32 <= {24'd0, random_num};`
148			`AMBER_TEST_RANDOM_NUM12: wb_rdata32 <= {24'd0, random_num};`
149			`AMBER_TEST_RANDOM_NUM13: wb_rdata32 <= {24'd0, random_num};`
150			`AMBER_TEST_RANDOM_NUM14: wb_rdata32 <= {24'd0, random_num};`
151			`AMBER_TEST_RANDOM_NUM15: wb_rdata32 <= {24'd0, random_num};`
152	2	csantifort
153			`//synopsys translate_off`
154	35	csantifort	`AMBER_TEST_UART_CONTROL: wb_rdata32 <= {30'd0, tb_uart_control_reg};`
155			`AMBER_TEST_UART_STATUS: wb_rdata32 <= {30'd0, tb_uart_status_reg};`
156			`AMBER_TEST_UART_TXD: wb_rdata32 <= {24'd0, tb_uart_txd_reg};`
157	2	csantifort	`//synopsys translate_on`
158
159	35	csantifort	`AMBER_TEST_SIM_CTRL: wb_rdata32 <= {29'd0, sim_ctrl_reg};`
160			`AMBER_TEST_MEM_CTRL: wb_rdata32 <= {31'd0, mem_ctrl_reg};`
161	32	csantifort
162	35	csantifort	`AMBER_TEST_CYCLES: wb_rdata32 <= cycles_reg;`
163			`default: wb_rdata32 <= 32'haabbccdd;`
164	2	csantifort
165			`endcase`
166
167
168			`// ======================================`
169			`// Simulation bit`
170			`// ======================================`
171
172			`// This register bit is a 1 in simulation but a 0 in the real fpga`
173			`// Used by software to tell the difference`
174			`//synopsys translate_off`
175
176			`ifndef AMBER_SIM_CTRL
177			`define AMBER_SIM_CTRL 0
178			`endif
179
180			`always @( posedge i_clk )`
181			`begin`
182			`// Value reads as 1 in simulation, and zero in the FPGA`
183	11	csantifort	sim_ctrl_reg <= 3'd `AMBER_SIM_CTRL ;
184	2	csantifort	`end`
185			`//synopsys translate_on`
186
187
188			`// ======================================`
189			`// Interrupts`
190			`// ======================================`
191			`assign o_irq = irq_timer == 8'd1;`
192			`assign o_firq = firq_timer == 8'd1;`
193
194
195			`// ======================================`
196			`// FIRQ Timer Register`
197			`// ======================================`
198			`// Write a value > 1 to set the firq timer`
199			`// Write 0 to clear it`
200			`always @( posedge i_clk )`
201			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_FIRQ_TIMER )`
202	35	csantifort	`firq_timer <= wb_wdata32[7:0];`
203	2	csantifort	`else if ( firq_timer > 8'd1 )`
204			`firq_timer <= firq_timer - 1'd1;`
205
206
207			`// ======================================`
208			`// IRQ Timer Register`
209			`// ======================================`
210			`// Write a value > 1 to set the irq timer`
211			`// Write 0 to clear it`
212			`always @( posedge i_clk )`
213			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_IRQ_TIMER )`
214	35	csantifort	`irq_timer <= wb_wdata32[7:0];`
215	2	csantifort	`else if ( irq_timer > 8'd1 )`
216			`irq_timer <= irq_timer - 1'd1;`
217
218
219			`// ======================================`
220			`// Random Number Generator Register`
221			`// ======================================`
222			`// Write a value > 1 to set the irq timer`
223			`// Write 0 to clear it`
224			`always @( posedge i_clk )`
225			`begin`
226			`if ( wb_start_write && i_wb_adr[15:8] == AMBER_TEST_RANDOM_NUM[15:8] )`
227	35	csantifort	`random_num <= wb_wdata32[7:0];`
228	2	csantifort
229			`// generate a new random number on every read access`
230			`else if ( wb_start_read && i_wb_adr[15:8] == AMBER_TEST_RANDOM_NUM[15:8] )`
231			`random_num <= { random_num[3]^random_num[1],`
232			`random_num[0]^random_num[5],`
233			`~random_num[7]^random_num[4],`
234			`~random_num[2],`
235			`random_num[6],`
236			`random_num[4]^~random_num[3],`
237			`random_num[7]^~random_num[1],`
238			`random_num[7]`
239			`};`
240			`end`
241
242
243			`// ======================================`
244			`// Test Status Write`
245			`// ======================================`
246			`always @( posedge i_clk )`
247			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )`
248	35	csantifort	`test_status_reg <= wb_wdata32;`
249	2	csantifort
250
251			`// ======================================`
252			`// Test Status Write`
253			`// ======================================`
254			`always @( posedge i_clk )`
255			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )`
256			`test_status_set <= 1'd1;`
257
258			`// ======================================`
259	32	csantifort	`// Cycles counter`
260			`// ======================================`
261			`always @( posedge i_clk )`
262			`cycles_reg <= cycles_reg + 1'd1;`
263
264			`// ======================================`
265	11	csantifort	`// Memory Configuration Register Write`
266			`// ======================================`
267			`always @( posedge i_clk )`
268			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_MEM_CTRL )`
269	35	csantifort	`mem_ctrl_reg <= wb_wdata32[0];`
270	11	csantifort
271
272			`// ======================================`
273	2	csantifort	`// Test UART registers`
274			`// ======================================`
275			`// These control the testbench UART, not the real`
276			`// UART in system`
277
278			`//synopsys translate_off`
279			`always @( posedge i_clk )`
280			`begin`
281			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_UART_CONTROL )`
282	35	csantifort	`tb_uart_control_reg <= wb_wdata32[1:0];`
283	2	csantifort
284			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_UART_TXD )`
285			`begin`
286	35	csantifort	`tb_uart_txd_reg <= wb_wdata32[7:0];`
287	2	csantifort	`tb_uart_push <= !tb_uart_push;`
288			`end`
289			`end`
290			`//synopsys translate_on`
291
292
293
294			`endmodule`
295

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[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [test_module.v] - Blame information for rev 53