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[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [uart.v] - Blame information for rev 20

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1 2 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  UART                                                        //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  This is a synchronous UART meaning it uses the system       //
10
//  clock rather than having its own clock. This means the      //
11
//  standard UART Baud rates are approximated and not exact.    //
12
//  However the UART tandard provides for a 10% margin on       //
13
//  baud rates and this module is much more accurate than that. //
14
//                                                              //
15
//  The Baud rate must be set before synthesis and is not       //
16
//  programmable. This keeps the UART small.                    //
17
//                                                              //
18
//  The UART uses 8 data bits, 1 stop bit and no parity bits.   //
19
//                                                              //
20
//  The UART has a 16-byte transmit and a 16-byte receive FIFO  //
21
//  These FIFOs are implemented in flipflops - FPGAs have lots  //
22
//  of flipflops!                                               //
23
//                                                              //
24
//  Author(s):                                                  //
25
//      - Conor Santifort, csantifort.amber@gmail.com           //
26
//                                                              //
27
//////////////////////////////////////////////////////////////////
28
//                                                              //
29
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
30
//                                                              //
31
// This source file may be used and distributed without         //
32
// restriction provided that this copyright statement is not    //
33
// removed from the file and that any derivative work contains  //
34
// the original copyright notice and the associated disclaimer. //
35
//                                                              //
36
// This source file is free software; you can redistribute it   //
37
// and/or modify it under the terms of the GNU Lesser General   //
38
// Public License as published by the Free Software Foundation; //
39
// either version 2.1 of the License, or (at your option) any   //
40
// later version.                                               //
41
//                                                              //
42
// This source is distributed in the hope that it will be       //
43
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
44
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
45
// PURPOSE.  See the GNU Lesser General Public License for more //
46
// details.                                                     //
47
//                                                              //
48
// You should have received a copy of the GNU Lesser General    //
49
// Public License along with this source; if not, download it   //
50
// from http://www.opencores.org/lgpl.shtml                     //
51
//                                                              //
52
//////////////////////////////////////////////////////////////////
53
 
54
`include "system_config_defines.v"
55
 
56 13 csantifort
// Normally AMBER_UART_BAUD is defined in the system_config_defines.v file.
57
`ifndef AMBER_UART_BAUD
58
`define AMBER_UART_BAUD 230400
59
`endif
60
 
61 2 csantifort
module uart (
62
input                       i_clk,
63
 
64
input       [31:0]          i_wb_adr,
65
input       [3:0]           i_wb_sel,
66
input                       i_wb_we,
67
output      [31:0]          o_wb_dat,
68
input       [31:0]          i_wb_dat,
69
input                       i_wb_cyc,
70
input                       i_wb_stb,
71
output                      o_wb_ack,
72
output                      o_wb_err,
73
 
74
output                      o_uart_int,
75
 
76
input                       i_uart_cts_n,   // Clear To Send
77
output                      o_uart_txd,     // Transmit data
78
output                      o_uart_rts_n,   // Request to Send
79
input                       i_uart_rxd      // Receive data
80
 
81
);
82
 
83
 
84
`include "register_addresses.v"
85
 
86
 
87
localparam [3:0] TXD_IDLE  = 4'd0,
88
                 TXD_START = 4'd1,
89
                 TXD_DATA0 = 4'd2,
90
                 TXD_DATA1 = 4'd3,
91
                 TXD_DATA2 = 4'd4,
92
                 TXD_DATA3 = 4'd5,
93
                 TXD_DATA4 = 4'd6,
94
                 TXD_DATA5 = 4'd7,
95
                 TXD_DATA6 = 4'd8,
96
                 TXD_DATA7 = 4'd9,
97
                 TXD_STOP1 = 4'd10,
98
                 TXD_STOP2 = 4'd11,
99
                 TXD_STOP3 = 4'd12;
100
 
101 13 csantifort
localparam [3:0] RXD_IDLE       = 4'd0,
102
                 RXD_START      = 4'd1,
103
                 RXD_START_MID  = 4'd2,
104
                 RXD_START_MID1 = 4'd3,
105
                 RXD_DATA0      = 4'd4,
106
                 RXD_DATA1      = 4'd5,
107
                 RXD_DATA2      = 4'd6,
108
                 RXD_DATA3      = 4'd7,
109
                 RXD_DATA4      = 4'd8,
110
                 RXD_DATA5      = 4'd9,
111
                 RXD_DATA6      = 4'd10,
112
                 RXD_DATA7      = 4'd11,
113
                 RXD_STOP       = 4'd12;
114 2 csantifort
 
115
 
116
localparam RX_INTERRUPT_COUNT = 24'h3fffff;
117
 
118
 
119
// -------------------------------------------------------------------------
120
// Baud Rate Configuration
121
// -------------------------------------------------------------------------
122
 
123
`ifndef Veritak
124
localparam real UART_BAUD         = `AMBER_UART_BAUD;            // Hz
125 13 csantifort
 
126
`ifdef XILINX_VIRTEX6_FPGA
127
localparam real CLK_FREQ          = 1000.0 / `AMBER_CLK_DIVIDER ; // MHz
128
`else
129 2 csantifort
localparam real CLK_FREQ          = 800.0 / `AMBER_CLK_DIVIDER ; // MHz
130 13 csantifort
`endif
131
 
132 2 csantifort
localparam real UART_BIT_PERIOD   = 1000000000 / UART_BAUD;      // nS
133
localparam real UART_WORD_PERIOD  = ( UART_BIT_PERIOD * 12 );    // nS
134
localparam real CLK_PERIOD        = 1000 / CLK_FREQ;             // nS
135
localparam real CLKS_PER_WORD     = UART_WORD_PERIOD / CLK_PERIOD;
136
localparam real CLKS_PER_BIT      = CLKS_PER_WORD / 12;
137
 
138
// These are rounded to the nearest whole number
139
// i.e. 29.485960 -> 29
140
//      29.566303 -> 30    
141
localparam [9:0] TX_BITPULSE_COUNT         = CLKS_PER_BIT;
142
localparam [9:0] TX_CLKS_PER_WORD          = CLKS_PER_WORD;
143
`else
144
localparam [9:0] TX_BITPULSE_COUNT         = 30;
145
localparam [9:0] TX_CLKS_PER_WORD          = 360;
146
`endif
147
 
148
localparam [9:0] TX_BITADJUST_COUNT        = TX_CLKS_PER_WORD - 11*TX_BITPULSE_COUNT;
149
 
150
localparam [9:0] RX_BITPULSE_COUNT         = TX_BITPULSE_COUNT-2;
151
localparam [9:0] RX_HALFPULSE_COUNT        = TX_BITPULSE_COUNT/2 - 4;
152
 
153
 
154
// -------------------------------------------------------------------------
155
 
156
reg             tx_interrupt = 'd0;
157
reg             rx_interrupt = 'd0;
158
reg   [23:0]    rx_int_timer = 'd0;
159
 
160
wire            fifo_enable;
161
 
162
reg   [7:0]     tx_fifo    [0:15];
163
wire            tx_fifo_full;
164
wire            tx_fifo_empty;
165
wire            tx_fifo_half_or_less_full;
166
wire            tx_fifo_push;
167
wire            tx_fifo_push_not_full;
168
wire            tx_fifo_pop_not_empty;
169
reg   [4:0]     tx_fifo_wp = 'd0;
170
reg   [4:0]     tx_fifo_rp = 'd0;
171
reg   [4:0]     tx_fifo_count = 'd0;   // number of entries in the fifo
172
reg             tx_fifo_full_flag = 'd0;
173
 
174
reg   [7:0]     rx_fifo    [0:15];
175
reg             rx_fifo_empty = 1'd1;
176
reg             rx_fifo_full = 1'd0;
177
wire            rx_fifo_half_or_more;     // true when half full or greater
178
reg   [4:0]     rx_fifo_count = 'd0;   // number of entries in the fifo
179
wire            rx_fifo_push;
180
wire            rx_fifo_push_not_full;
181
wire            rx_fifo_pop;
182
wire            rx_fifo_pop_not_empty;
183
reg   [4:0]     rx_fifo_wp = 'd0;
184
reg   [4:0]     rx_fifo_rp = 'd0;
185
 
186
wire  [7:0]     tx_byte;
187
reg   [3:0]     txd_state = TXD_IDLE;
188
reg             txd = 1'd1;
189
reg             tx_bit_pulse = 'd0;
190
reg   [9:0]     tx_bit_pulse_count = 'd0;
191
 
192
reg   [7:0]     rx_byte = 'd0;
193
reg   [3:0]     rxd_state = RXD_IDLE;
194
wire            rx_start;
195
reg             rxen = 'd0;
196
reg   [9:0]     rx_bit_pulse_count = 'd0;
197
reg             restart_rx_bit_count = 'd0;
198
reg   [4:0]     rxd_d = 5'h1f;
199
reg   [3:0]     uart0_cts_n_d = 4'hf;
200
 
201
// Wishbone registers
202
reg  [7:0]      uart_rsr_reg = 'd0;       // Receive status, (Write) Error Clear
203
reg  [7:0]      uart_lcrh_reg = 'd0;      // Line Control High Byte
204
reg  [7:0]      uart_lcrm_reg = 'd0;      // Line Control Middle Byte
205
reg  [7:0]      uart_lcrl_reg = 'd0;      // Line Control Low Byte
206
reg  [7:0]      uart_cr_reg = 'd0;        // Control Register
207
 
208
// Wishbone interface
209
reg  [31:0]     wb_rdata = 'd0;
210
wire            wb_start_write;
211
wire            wb_start_read;
212
reg             wb_start_read_d1 = 'd0;
213
 
214
integer         i;
215
 
216
// ======================================================
217
// Wishbone Interface
218
// ======================================================
219
 
220
// Can't start a write while a read is completing. The ack for the read cycle
221
// needs to be sent first
222
assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
223
assign wb_start_read  = i_wb_stb && !i_wb_we && !o_wb_ack;
224
 
225
always @( posedge i_clk )
226
    wb_start_read_d1 <= wb_start_read;
227
 
228
assign o_wb_dat = wb_rdata;
229
 
230
assign o_wb_err = 1'd0;
231
assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
232
 
233
 
234
// ======================================================
235
// UART 0 Receive FIFO
236
// ======================================================    
237
 
238
assign rx_fifo_pop           = wb_start_read && i_wb_adr[15:0] == AMBER_UART_DR;
239
assign rx_fifo_push_not_full = rx_fifo_push && !rx_fifo_full;
240
assign rx_fifo_pop_not_empty = rx_fifo_pop && !rx_fifo_empty;
241
assign rx_fifo_half_or_more  = rx_fifo_count >= 5'd8;
242
 
243
 
244
always @ ( posedge i_clk )
245
    begin
246
    if ( fifo_enable )
247
        begin
248
        // RX FIFO Push
249
        if ( rx_fifo_push_not_full )
250
            begin
251
            rx_fifo[rx_fifo_wp[3:0]]    <= rx_byte;
252
            rx_fifo_wp                  <= rx_fifo_wp + 1'd1;
253
            end
254
 
255
        if ( rx_fifo_pop_not_empty )
256
            begin
257
            rx_fifo_rp                  <= rx_fifo_rp + 1'd1;
258
            end
259
 
260
        if ( rx_fifo_push_not_full && !rx_fifo_pop_not_empty )
261
            rx_fifo_count <= rx_fifo_count + 1'd1;
262
        else if ( rx_fifo_pop_not_empty  && !rx_fifo_push_not_full )
263
            rx_fifo_count <= rx_fifo_count - 1'd1;
264
 
265
        rx_fifo_full  <= rx_fifo_wp == {~rx_fifo_rp[4], rx_fifo_rp[3:0]};
266
        rx_fifo_empty <= rx_fifo_wp == rx_fifo_rp;
267
 
268
        if ( rx_fifo_empty || rx_fifo_pop )
269
            rx_int_timer     <= 'd0;
270
        else if ( rx_int_timer != RX_INTERRUPT_COUNT )
271
            rx_int_timer     <= rx_int_timer + 1'd1;
272
 
273
 
274
        end
275
    else    // No FIFO    
276
        begin
277
        rx_int_timer     <= 'd0;
278
 
279
        if ( rx_fifo_push )
280
            begin
281
            rx_fifo[0]         <= rx_byte;
282
            rx_fifo_empty      <= 1'd0;
283
            rx_fifo_full       <= 1'd1;
284
            end
285
        else if ( rx_fifo_pop )
286
            begin
287
            rx_fifo_empty      <= 1'd1;
288
            rx_fifo_full       <= 1'd0;
289
            end
290
        end
291
    end
292
 
293
 
294
// ======================================================
295
// Transmit Interrupts
296
// ======================================================    
297
 
298
 
299
// UART 0 Transmit Interrupt    
300
always @ ( posedge i_clk )
301
    begin
302
    // Clear the interrupt
303
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_UART_ICR )
304
        tx_interrupt <= 1'd0;
305
 
306
    // Set the interrupt    
307
    else if  ( fifo_enable )
308
        // This interrupt clears automatically as bytes are pushed into the tx fifo
309
        // cr bit 5 is Transmit Interrupt Enable
310
        tx_interrupt <= tx_fifo_half_or_less_full && uart_cr_reg[5];
311
    else
312
        // This interrupt clears automatically when a byte is written to tx
313
        // cr bit 5 is Transmit Interrupt Enable
314
        tx_interrupt <= tx_fifo_empty && uart_cr_reg[5];
315
    end
316
 
317
 
318
// ======================================================
319
// Receive Interrupts
320
// ======================================================    
321
 
322
always @ ( posedge i_clk )
323
    if (fifo_enable)
324
        rx_interrupt <=  rx_fifo_half_or_more || rx_int_timer == RX_INTERRUPT_COUNT;
325
    else
326
        rx_interrupt <=  rx_fifo_full;
327
 
328
 
329
assign o_uart_int   = ( tx_interrupt & uart_cr_reg[5] )  |  // UART transmit interrupt w/ enable
330
                      ( rx_interrupt & uart_cr_reg[4] )  ;  // UART receive  interrupt w/ enable
331
 
332
assign fifo_enable = uart_lcrh_reg[4];
333
 
334
 
335
 
336
// ========================================================
337
// UART Transmit
338
// ========================================================
339
 
340
assign   o_uart_txd                 = txd;
341
 
342 13 csantifort
assign   tx_fifo_full               = fifo_enable ? tx_fifo_count >= 5'd16 :  tx_fifo_full_flag;
343
assign   tx_fifo_empty              = fifo_enable ? tx_fifo_count == 5'd00 : !tx_fifo_full_flag;
344
assign   tx_fifo_half_or_less_full  =               tx_fifo_count <= 5'd8;
345 2 csantifort
assign   tx_byte                    = fifo_enable ? tx_fifo[tx_fifo_rp[3:0]] : tx_fifo[0] ;
346
 
347
assign   tx_fifo_push               = wb_start_write && i_wb_adr[15:0] == AMBER_UART_DR;
348
assign   tx_fifo_push_not_full      = tx_fifo_push && !tx_fifo_full;
349
assign   tx_fifo_pop_not_empty      = txd_state == TXD_STOP3 && tx_bit_pulse == 1'd1 && !tx_fifo_empty;
350
 
351
 
352
// Transmit FIFO
353
always @( posedge i_clk )
354
    begin
355
    // Use 8-entry FIFO
356
    if ( fifo_enable )
357
        begin
358
        // Push
359
        if ( tx_fifo_push_not_full )
360
            begin
361
            tx_fifo[tx_fifo_wp[3:0]] <= i_wb_dat[7:0];
362
            tx_fifo_wp <= tx_fifo_wp + 1'd1;
363
            end
364
 
365
 
366
        // Pop    
367
        if ( tx_fifo_pop_not_empty )
368
            tx_fifo_rp <= tx_fifo_rp + 1'd1;
369
 
370
        // Count up 
371
        if (tx_fifo_push_not_full && !tx_fifo_pop_not_empty)
372
            tx_fifo_count <= tx_fifo_count + 1'd1;
373
 
374
        // Count down 
375
        else if (tx_fifo_pop_not_empty  && !tx_fifo_push_not_full)
376
            tx_fifo_count <= tx_fifo_count - 1'd1;
377
        end
378
 
379
    // Do not use 8-entry FIFO, single entry register instead
380
    else
381
        begin
382
        // Clear FIFO values
383
        tx_fifo_wp    <= 'd0;
384
        tx_fifo_rp    <= 'd0;
385
        tx_fifo_count <= 'd0;
386
 
387
        // Push
388
        if ( tx_fifo_push_not_full )
389
            begin
390
            tx_fifo[0]          <= i_wb_dat[7:0];
391
            tx_fifo_full_flag   <= 1'd1;
392
            end
393
        // Pop    
394
        else if ( tx_fifo_pop_not_empty )
395
            tx_fifo_full_flag   <= 1'd0;
396
 
397
        end
398
    end
399
 
400
 
401
// ========================================================
402
// Register Clear to Send Input
403
// ========================================================
404
always @( posedge i_clk )
405
    uart0_cts_n_d <= {uart0_cts_n_d[2:0], i_uart_cts_n};
406
 
407
 
408
// ========================================================
409
// Transmit Pulse generater - matches baud rate      
410
// ========================================================
411
always @( posedge i_clk )
412
    if (( tx_bit_pulse_count == (TX_BITADJUST_COUNT-1) && txd_state == TXD_STOP2 ) ||
413
        ( tx_bit_pulse_count == (TX_BITPULSE_COUNT-1)  && txd_state != TXD_STOP2 )  )
414
        begin
415
        tx_bit_pulse_count <= 'd0;
416
        tx_bit_pulse       <= 1'd1;
417
        end
418
    else
419
        begin
420
        tx_bit_pulse_count <= tx_bit_pulse_count + 1'd1;
421
        tx_bit_pulse       <= 1'd0;
422
        end
423
 
424
 
425
// ========================================================
426
// Byte Transmitted
427
// ========================================================
428
    // Idle state, txd = 1
429
    // start bit, txd = 0
430
    // Data x 8, lsb first
431
    // stop bit, txd = 1
432
 
433
 
434
    // X = 0x58  = 01011000
435
always @( posedge i_clk )
436
    if ( tx_bit_pulse )
437
 
438 13 csantifort
        case ( txd_state )
439 2 csantifort
 
440
            TXD_IDLE :
441
                begin
442
                txd       <= 1'd1;
443
 
444
                if ( uart0_cts_n_d[3:1] == 3'b000 && !tx_fifo_empty )
445
                    txd_state <= TXD_START;
446
                end
447
 
448
            TXD_START :
449
                begin
450
                txd       <= 1'd0;
451
                txd_state <= TXD_DATA0;
452
                end
453
 
454
            TXD_DATA0 :
455
                begin
456
                txd       <= tx_byte[0];
457
                txd_state <= TXD_DATA1;
458
                end
459
 
460
            TXD_DATA1 :
461
                begin
462
                txd       <= tx_byte[1];
463
                txd_state <= TXD_DATA2;
464
                end
465
 
466
            TXD_DATA2 :
467
                begin
468
                txd       <= tx_byte[2];
469
                txd_state <= TXD_DATA3;
470
                end
471
 
472
            TXD_DATA3 :
473
                begin
474
                txd       <= tx_byte[3];
475
                txd_state <= TXD_DATA4;
476
                end
477
 
478
            TXD_DATA4 :
479
                begin
480
                txd       <= tx_byte[4];
481
                txd_state <= TXD_DATA5;
482
                end
483
 
484
            TXD_DATA5 :
485
                begin
486
                txd       <= tx_byte[5];
487
                txd_state <= TXD_DATA6;
488
                end
489
 
490
            TXD_DATA6 :
491
                begin
492
                txd       <= tx_byte[6];
493
                txd_state <= TXD_DATA7;
494
                end
495
 
496
            TXD_DATA7 :
497
                begin
498
                txd       <= tx_byte[7];
499
                txd_state <= TXD_STOP1;
500
                end
501
 
502
            TXD_STOP1 :
503
                begin
504
                txd       <= 1'd1;
505
                txd_state <= TXD_STOP2;
506
                end
507
 
508
            TXD_STOP2 :
509
                begin
510
                txd       <= 1'd1;
511
                txd_state <= TXD_STOP3;
512
                end
513
 
514
            TXD_STOP3 :
515
                begin
516
                txd       <= 1'd1;
517
                txd_state <= TXD_IDLE;
518
                end
519
 
520
            default :
521
                begin
522
                txd       <= 1'd1;
523
                end
524
 
525
        endcase
526
 
527
 
528
 
529
 
530
// ========================================================
531
// UART Receive
532
// ========================================================
533
 
534
assign o_uart_rts_n  = ~rxen;
535
 
536
assign rx_fifo_push  = rxd_state == RXD_STOP && rx_bit_pulse_count == 10'd0;
537
 
538
// ========================================================
539
// Receive bit pulse
540
// ========================================================
541
// Pulse generater - matches baud rate      
542
always @( posedge i_clk )
543
    if ( restart_rx_bit_count )
544
        rx_bit_pulse_count <= 'd0;
545
    else
546
        rx_bit_pulse_count <= rx_bit_pulse_count + 1'd1;
547
 
548
 
549
// ========================================================
550
// Detect 1->0 transition. Filter out glitches and jaggedy transitions
551
// ========================================================
552
always @( posedge i_clk )
553
    rxd_d[4:0] <= {rxd_d[3:0], i_uart_rxd};
554
 
555
assign rx_start = rxd_d[4:3] == 2'b11 && rxd_d[1:0] == 2'b00;
556
 
557
 
558
// ========================================================
559
// Receive state machine
560
// ========================================================
561
 
562
always @( posedge i_clk )
563
    case ( rxd_state )
564
 
565
        RXD_IDLE :
566
            if ( rx_fifo_full )
567
                rxen                    <= 1'd0;
568
            else
569
                begin
570
                rxd_state               <= RXD_START;
571
                rxen                    <= 1'd1;
572
                restart_rx_bit_count    <= 1'd1;
573
                rx_byte                 <= 'd0;
574
                end
575
 
576
        RXD_START :
577
            // Filter out glitches and jaggedy transitions
578
            if ( rx_start )
579
                begin
580 13 csantifort
                rxd_state               <= RXD_START_MID1;
581 2 csantifort
                restart_rx_bit_count    <= 1'd1;
582
                end
583
            else
584
                restart_rx_bit_count    <= 1'd0;
585 13 csantifort
 
586
        // This state just delays the check on the
587
        // rx_bit_pulse_count value by 1 clock cycle to
588
        // give it time to reset
589
        RXD_START_MID1 :
590
            rxd_state               <= RXD_START_MID;
591 2 csantifort
 
592
        RXD_START_MID :
593
            if ( rx_bit_pulse_count == RX_HALFPULSE_COUNT )
594
                begin
595
                rxd_state               <= RXD_DATA0;
596
                restart_rx_bit_count    <= 1'd1;
597
                end
598
            else
599
                restart_rx_bit_count    <= 1'd0;
600
 
601
        RXD_DATA0 :
602
            if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
603
                begin
604
                rxd_state               <= RXD_DATA1;
605
                restart_rx_bit_count    <= 1'd1;
606
                rx_byte[0]              <= i_uart_rxd;
607
                end
608
            else
609
                restart_rx_bit_count    <= 1'd0;
610
 
611
        RXD_DATA1 :
612
            if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
613
                begin
614
                rxd_state               <= RXD_DATA2;
615
                restart_rx_bit_count    <= 1'd1;
616
                rx_byte[1]              <= i_uart_rxd;
617
                end
618
            else
619
                restart_rx_bit_count    <= 1'd0;
620
 
621
        RXD_DATA2 :
622
            if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
623
                begin
624
                rxd_state               <= RXD_DATA3;
625
                restart_rx_bit_count    <= 1'd1;
626
                rx_byte[2]              <= i_uart_rxd;
627
                end
628
            else
629
                restart_rx_bit_count    <= 1'd0;
630
 
631
        RXD_DATA3 :
632
            if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
633
                begin
634
                rxd_state               <= RXD_DATA4;
635
                restart_rx_bit_count    <= 1'd1;
636
                rx_byte[3]              <= i_uart_rxd;
637
                end
638
            else
639
                restart_rx_bit_count    <= 1'd0;
640
 
641
        RXD_DATA4 :
642
            if ( rx_bit_pulse_count ==  RX_BITPULSE_COUNT )
643
                begin
644
                rxd_state               <= RXD_DATA5;
645
                restart_rx_bit_count    <= 1'd1;
646
                rx_byte[4]              <= i_uart_rxd;
647
                end
648
            else
649
                restart_rx_bit_count    <= 1'd0;
650
 
651
        RXD_DATA5 :
652
            if ( rx_bit_pulse_count ==  RX_BITPULSE_COUNT )
653
                begin
654
                rxd_state               <= RXD_DATA6;
655
                restart_rx_bit_count    <= 1'd1;
656
                rx_byte[5]              <= i_uart_rxd;
657
                end
658
            else
659
                restart_rx_bit_count    <= 1'd0;
660
 
661
        RXD_DATA6 :
662
            if ( rx_bit_pulse_count ==  RX_BITPULSE_COUNT )
663
                begin
664
                rxd_state               <= RXD_DATA7;
665
                restart_rx_bit_count    <= 1'd1;
666
                rx_byte[6]              <= i_uart_rxd;
667
                end
668
            else
669
                restart_rx_bit_count    <= 1'd0;
670
 
671
        RXD_DATA7 :
672
            if ( rx_bit_pulse_count ==  RX_BITPULSE_COUNT )
673
                begin
674
                rxd_state               <= RXD_STOP;
675
                restart_rx_bit_count    <= 1'd1;
676
                rx_byte[7]              <= i_uart_rxd;
677
                end
678
            else
679
                restart_rx_bit_count    <= 1'd0;
680
 
681
        RXD_STOP :
682
            if ( rx_bit_pulse_count ==  RX_BITPULSE_COUNT )  // half way through stop bit 
683
                begin
684
                rxd_state               <= RXD_IDLE;
685
                restart_rx_bit_count    <= 1'd1;
686
                end
687
            else
688
                restart_rx_bit_count    <= 1'd0;
689
 
690
        default :
691
            begin
692
            rxd_state       <= RXD_IDLE;
693
            end
694
 
695
    endcase
696
 
697
 
698
// ========================================================
699
// Register Writes
700
// ========================================================
701
always @( posedge i_clk )
702
    if ( wb_start_write )
703
        case ( i_wb_adr[15:0] )
704
            // Receive status, (Write) Error Clear
705
            AMBER_UART_RSR:  uart_rsr_reg      <= i_wb_dat[7:0];
706
            // Line Control High Byte    
707
            AMBER_UART_LCRH: uart_lcrh_reg     <= i_wb_dat[7:0];
708
            // Line Control Middle Byte    
709
            AMBER_UART_LCRM: uart_lcrm_reg     <= i_wb_dat[7:0];
710
            // Line Control Low Byte    
711
            AMBER_UART_LCRL: uart_lcrl_reg     <= i_wb_dat[7:0];
712
            // Control Register    
713
            AMBER_UART_CR:   uart_cr_reg       <= i_wb_dat[7:0];
714
        endcase
715
 
716
 
717
// ========================================================
718
// Register Reads
719
// ========================================================
720
always @( posedge i_clk )
721
    if ( wb_start_read )
722
        case ( i_wb_adr[15:0] )
723
 
724
            AMBER_UART_CID0:    wb_rdata <= 32'h0d;
725
            AMBER_UART_CID1:    wb_rdata <= 32'hf0;
726
            AMBER_UART_CID2:    wb_rdata <= 32'h05;
727
            AMBER_UART_CID3:    wb_rdata <= 32'hb1;
728
            AMBER_UART_PID0:    wb_rdata <= 32'h10;
729
            AMBER_UART_PID1:    wb_rdata <= 32'h10;
730
            AMBER_UART_PID2:    wb_rdata <= 32'h04;
731
            AMBER_UART_PID3:    wb_rdata <= 32'h00;
732
 
733
            AMBER_UART_DR:      // Rx data   
734
                    if ( fifo_enable )
735
                        wb_rdata <= {24'd0, rx_fifo[rx_fifo_rp[3:0]]};
736
                    else
737
                        wb_rdata <= {24'd0, rx_fifo[0]};
738
 
739
            AMBER_UART_RSR:     wb_rdata <= uart_rsr_reg;          // Receive status, (Write) Error Clear
740
            AMBER_UART_LCRH:    wb_rdata <= uart_lcrh_reg;         // Line Control High Byte
741
            AMBER_UART_LCRM:    wb_rdata <= uart_lcrm_reg;         // Line Control Middle Byte
742
            AMBER_UART_LCRL:    wb_rdata <= uart_lcrl_reg;         // Line Control Low Byte
743
            AMBER_UART_CR:      wb_rdata <= uart_cr_reg;           // Control Register
744
 
745
            // UART Tx/Rx Status
746
            AMBER_UART_FR:      wb_rdata <= {tx_fifo_empty,       // tx fifo empty
747
                                             rx_fifo_full,        // rx fifo full
748
                                             tx_fifo_full,        // tx fifo full
749
                                             rx_fifo_empty,       // rx fifo empty
750
                                             !tx_fifo_empty,      // uart busy
751
                                             1'd1,                 // !Data Carrier Detect
752
                                             1'd1,                 // !Data Set Ready
753
                                             !uart0_cts_n_d[3]     // !Clear to Send
754
                                             };                    // Flag Register
755
 
756
            // Interrupt Status                                                    
757
            AMBER_UART_IIR:     wb_rdata <= {5'd0,
758
                                             1'd0,                 // RTIS  - receive timeout interrupt
759
                                             tx_interrupt,         // TIS   - transmit interrupt status
760
                                             rx_interrupt,         // RIS   - receive interrupt status
761
                                             1'd0                  // Modem interrupt status
762
                                            };                     // (Write) Clear Int
763
 
764
            default:            wb_rdata <= 32'h00c0ffee;
765
 
766
        endcase
767
 
768
 
769
 
770
 
771
// =======================================================================================
772
// =======================================================================================
773
// =======================================================================================
774
// Non-synthesizable debug code
775
// =======================================================================================
776
 
777
 
778
//synopsys translate_off
779
 
780
// ========================================================
781
// Report UART Register accesses
782
// ========================================================
783
 
784
`ifndef Veritak
785
// Check in case UART approximate period
786
// is too far off
787
initial
788
    begin
789
    if ((( TX_BITPULSE_COUNT * CLK_PERIOD ) > (UART_BIT_PERIOD * 1.03) ) ||
790
        (( TX_BITPULSE_COUNT * CLK_PERIOD ) < (UART_BIT_PERIOD * 0.97) ) )
791
        begin
792
        `TB_ERROR_MESSAGE
793
        $display("UART TX bit period, %.1f, is too big. UART will not work!", TX_BITPULSE_COUNT * CLK_PERIOD);
794
        $display("Baud rate is %d, and baud bit period is %.1f", UART_BAUD, UART_BIT_PERIOD);
795
        $display("Either reduce the baud rate, or increase the system clock frequency");
796
        $display("------");
797
        end
798
    end
799
`endif
800
 
801
 
802
`ifdef AMBER_UART_DEBUG
803
wire            wb_read_ack;
804
reg             uart0_rx_int_d1 = 'd0;
805
 
806
assign wb_read_ack = i_wb_stb && !i_wb_we &&  o_wb_ack;
807
 
808
`ifndef Veritak
809
initial
810
    begin
811
    $display("%m UART period = %f nS, want %f nS, %d, %d",
812
             (TX_BITPULSE_COUNT*11 + TX_BITADJUST_COUNT) * CLK_PERIOD,
813
             UART_WORD_PERIOD,
814
             TX_BITPULSE_COUNT, TX_BITADJUST_COUNT);
815
    end
816
`endif
817
 
818
 
819
// Transmit Interrupts
820
always @ ( posedge i_clk )
821
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_UART_ICR )
822
            ;
823
    else if ( fifo_enable )
824
        begin
825
        if (tx_interrupt == 1'd0 && tx_fifo_half_or_less_full && uart_cr_reg[5])
826
            $display("%m: tx_interrupt Interrupt Set with FIFO enabled");
827
        if (tx_interrupt == 1'd1 && !(tx_fifo_half_or_less_full && uart_cr_reg[5]))
828
            $display("%m: tx_interrupt Interrupt Cleared with FIFO enabled");
829
        end
830
    else
831
        begin
832
        if (tx_interrupt == 1'd0 && tx_fifo_empty && uart_cr_reg[5])
833
            $display("%m: tx_interrupt Interrupt Set with FIFO disabled");
834
        if (tx_interrupt == 1'd1 && !(tx_fifo_empty && uart_cr_reg[5]))
835
            $display("%m: tx_interrupt Interrupt Cleared with FIFO disabled");
836
        end
837
 
838
 
839
// Receive Interrupts
840
always @ ( posedge i_clk )
841
    begin
842
    uart0_rx_int_d1 <= rx_interrupt;
843
 
844
    if ( rx_interrupt && !uart0_rx_int_d1 )
845
        begin
846
        `TB_DEBUG_MESSAGE
847
        $display("rx_interrupt Interrupt fifo_enable %d, rx_fifo_full %d",
848
                 fifo_enable, rx_fifo_full);
849
        $display("rx_fifo_half_or_more %d, rx_int_timer 0x%08h, rx_fifo_count %d",
850
                 rx_fifo_half_or_more, rx_int_timer, rx_fifo_count);
851
        end
852
 
853
    if ( !rx_interrupt && uart0_rx_int_d1 )
854
        begin
855
        `TB_DEBUG_MESSAGE
856
        $display("rx_interrupt Interrupt Cleared fifo_enable %d, rx_fifo_full %d",
857
                 fifo_enable, rx_fifo_full);
858
        $display("    rx_fifo_half_or_more %d, rx_int_timer 0x%08h, rx_fifo_count %d",
859
                 rx_fifo_half_or_more, rx_int_timer, rx_fifo_count);
860
        end
861
    end
862
 
863
 
864
always @( posedge i_clk )
865
    if ( wb_read_ack || wb_start_write )
866
        begin
867
        `TB_DEBUG_MESSAGE
868
 
869
        if ( wb_start_write )
870
            $write("Write 0x%08x to   ", i_wb_dat);
871
        else
872
            $write("Read  0x%08x from ", o_wb_dat);
873
 
874
        case ( i_wb_adr[15:0] )
875
            AMBER_UART_PID0:    $write("UART PID0 register");
876
            AMBER_UART_PID1:    $write("UART PID1 register");
877
            AMBER_UART_PID2:    $write("UART PID2 register");
878
            AMBER_UART_PID3:    $write("UART PID3 register");
879
            AMBER_UART_CID0:    $write("UART CID0 register");
880
            AMBER_UART_CID1:    $write("UART CID1 register");
881
            AMBER_UART_CID2:    $write("UART CID2 register");
882
            AMBER_UART_CID3:    $write("UART CID3 register");
883
            AMBER_UART_DR:      $write("UART Tx/Rx char %c", wb_start_write ? i_wb_dat[7:0] : o_wb_dat[7:0] );
884
            AMBER_UART_RSR:     $write("UART (Read) Receive status, (Write) Error Clear");
885
            AMBER_UART_LCRH:    $write("UART Line Control High Byte");
886
            AMBER_UART_LCRM:    $write("UART Line Control Middle Byte");
887
            AMBER_UART_LCRL:    $write("UART Line Control Low Byte");
888
            AMBER_UART_CR:      $write("UART Control Register");
889
            AMBER_UART_FR:      $write("UART Flag Register");
890
            AMBER_UART_IIR:     $write("UART (Read) Interrupt Identification Register");
891
 
892
            default:
893
                begin
894
                `TB_ERROR_MESSAGE
895
                $write("Unknown UART Register region");
896
                end
897
        endcase
898
 
899
        $write(", Address 0x%08h\n", i_wb_adr);
900
        end
901
`endif
902
 
903
 
904
// ========================================================
905
// Assertions
906
// ========================================================
907
always @ ( posedge i_clk )
908
    begin
909
    if ( rx_fifo_pop  && !rx_fifo_push && rx_fifo_empty )
910
        begin
911
        `TB_WARNING_MESSAGE
912
        $write("UART rx FIFO underflow\n");
913
        end
914
    if ( !rx_fifo_pop  && rx_fifo_push && rx_fifo_full )
915
        begin
916
        `TB_WARNING_MESSAGE
917
        $write("UART rx FIFO overflow\n");
918
        end
919
 
920
    if ( tx_fifo_push && tx_fifo_full )
921
        begin
922
        `TB_WARNING_MESSAGE
923
        $display("UART tx FIFO overflow - char = %c", i_wb_dat[7:0]);
924
        end
925
    end
926
 
927
 
928
// ========================================================
929
// Debug State Machines
930
// ========================================================
931
 
932
wire    [(10*8)-1:0]    xTXD_STATE;
933
wire    [(14*8)-1:0]    xRXD_STATE;
934
 
935
 
936 13 csantifort
assign xTXD_STATE      = txd_state == TXD_IDLE       ? "TXD_IDLE"   :
937
                         txd_state == TXD_START      ? "TXD_START"  :
938
                         txd_state == TXD_DATA0      ? "TXD_DATA0"  :
939
                         txd_state == TXD_DATA1      ? "TXD_DATA1"  :
940
                         txd_state == TXD_DATA2      ? "TXD_DATA2"  :
941
                         txd_state == TXD_DATA3      ? "TXD_DATA3"  :
942
                         txd_state == TXD_DATA4      ? "TXD_DATA4"  :
943
                         txd_state == TXD_DATA5      ? "TXD_DATA5"  :
944
                         txd_state == TXD_DATA6      ? "TXD_DATA6"  :
945
                         txd_state == TXD_DATA7      ? "TXD_DATA7"  :
946
                         txd_state == TXD_STOP1      ? "TXD_STOP1"  :
947
                         txd_state == TXD_STOP2      ? "TXD_STOP2"  :
948
                         txd_state == TXD_STOP3      ? "TXD_STOP3"  :
949
                                                       "UNKNOWN"    ;
950 2 csantifort
 
951 13 csantifort
assign xRXD_STATE      = rxd_state == RXD_IDLE       ? "RXD_IDLE"      :
952
                         rxd_state == RXD_START      ? "RXD_START"     :
953
                         rxd_state == RXD_START_MID1 ? "RXD_START_MID1":
954
                         rxd_state == RXD_START_MID  ? "RXD_START_MID" :
955
                         rxd_state == RXD_DATA0      ? "RXD_DATA0"     :
956
                         rxd_state == RXD_DATA1      ? "RXD_DATA1"     :
957
                         rxd_state == RXD_DATA2      ? "RXD_DATA2"     :
958
                         rxd_state == RXD_DATA3      ? "RXD_DATA3"     :
959
                         rxd_state == RXD_DATA4      ? "RXD_DATA4"     :
960
                         rxd_state == RXD_DATA5      ? "RXD_DATA5"     :
961
                         rxd_state == RXD_DATA6      ? "RXD_DATA6"     :
962
                         rxd_state == RXD_DATA7      ? "RXD_DATA7"     :
963
                         rxd_state == RXD_STOP       ? "RXD_STOP"      :
964
                                                       "UNKNOWN"       ;
965 2 csantifort
 
966
//synopsys translate_on
967
 
968
 
969
endmodule
970
 

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