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[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [wb_ddr3_bridge.v] - Blame information for rev 49

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1 2 csantifort
//////////////////////////////////////////////////////////////////
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//                                                              //
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//  Wishbone Slave to Xilinx MCB (DDR3 controller) Bridge       //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Converts wishbone read and write accesses to the signalling //
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//  used by the Xilinx DDR3 Controller in Spartan-6 FPGAs.      //
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//                                                              //
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//  The MCB is confgiured with a single 128-bit port.           //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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module wb_ddr3_bridge
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(
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input                          i_clk,
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// MBus Ports
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input       [31:0]             i_wb_adr,
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input       [3:0]              i_wb_sel,
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input                          i_wb_we,
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output reg  [31:0]             o_wb_dat         = 'd0,
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input       [31:0]             i_wb_dat,
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input                          i_wb_cyc,
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input                          i_wb_stb,
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output                         o_wb_ack,
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output                         o_wb_err,
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output reg                     o_cmd_en         = 'd0,  // Command Enable
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output reg [2:0]               o_cmd_instr      = 'd0,  // write = 000, read = 001
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output reg [29:0]              o_cmd_byte_addr  = 'd0,  // Memory address
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input                          i_cmd_full,              // DDR3 I/F Command FIFO is full
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input                          i_wr_full,               // DDR3 I/F Write Data FIFO is full
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output reg                     o_wr_en          = 'd0,  // Write data enable
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output reg [15:0]              o_wr_mask        = 'd0,  // 1 bit per byte
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output reg [127:0]             o_wr_data        = 'd0,  // 16 bytes write data
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input      [127:0]             i_rd_data,               // 16 bytes of read data
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input                          i_rd_empty               // low when read data is valid
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);
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wire            start_write;
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wire            start_read;
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reg             start_write_d1;
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reg             start_read_d1;
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reg             start_read_hold = 'd0;
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reg  [31:0]     wb_adr_d1;
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wire            ddr3_busy;
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reg             read_ack = 'd0;
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reg             read_ready = 1'd1;
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assign start_write = i_wb_stb && i_wb_we && !start_read_d1;
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assign start_read  = i_wb_stb && !i_wb_we && read_ready;
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assign ddr3_busy   = i_cmd_full || i_wr_full;
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assign o_wb_err = 'd0;
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// ------------------------------------------------------
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// Outputs
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// ------------------------------------------------------
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// Command FIFO
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always @( posedge i_clk )
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    begin
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    o_cmd_byte_addr  <= {wb_adr_d1[29:4], 4'd0};
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    o_cmd_en         <= !ddr3_busy && ( start_write_d1 || start_read_d1 );
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    o_cmd_instr      <= start_write_d1 ? 3'd0 : 3'd1;
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    end
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// ------------------------------------------------------
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// Write
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// ------------------------------------------------------
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always @( posedge i_clk )
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    begin
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    o_wr_en          <= start_write;
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    `ifdef XILINX_VIRTEX6_FPGA
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        o_wr_mask        <= i_wb_adr[2] == 2'd2 ? { 8'h0, 4'hf,  ~i_wb_sel        } :
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                                                  { 8'h0,        ~i_wb_sel, 4'hf  } ;
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    `else
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        o_wr_mask        <= i_wb_adr[3:2] == 2'd0 ? { 12'hfff, ~i_wb_sel          } :
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                            i_wb_adr[3:2] == 2'd1 ? { 8'hff,   ~i_wb_sel, 4'hf    } :
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                            i_wb_adr[3:2] == 2'd2 ? { 4'hf,    ~i_wb_sel, 8'hff   } :
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                                                    {          ~i_wb_sel, 12'hfff } ;
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    `endif
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    o_wr_data        <= {4{i_wb_dat}};
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    end
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// ------------------------------------------------------
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// Read
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// ------------------------------------------------------
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always @( posedge i_clk )
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    begin
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    if ( read_ack )
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        read_ready <= 1'd1;
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    else if ( start_read )
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        read_ready <= 1'd0;
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    start_write_d1  <= start_write;
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    start_read_d1   <= start_read;
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    wb_adr_d1       <= i_wb_adr;
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    if ( start_read  )
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        start_read_hold <= 1'd1;
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    else if ( read_ack )
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        start_read_hold <= 1'd0;
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    if ( i_rd_empty == 1'd0 && start_read_hold )
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        begin
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        `ifdef XILINX_VIRTEX6_FPGA
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            o_wb_dat  <= i_wb_adr[2] == 2'd2   ? i_rd_data[  31:0] :
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                                                 i_rd_data[ 63:32] ;
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        `else
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            o_wb_dat  <= i_wb_adr[3:2] == 2'd0 ? i_rd_data[ 31: 0] :
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                         i_wb_adr[3:2] == 2'd1 ? i_rd_data[ 63:32] :
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                         i_wb_adr[3:2] == 2'd2 ? i_rd_data[ 95:64] :
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                                                 i_rd_data[127:96] ;
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        `endif
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        read_ack  <= 1'd1;
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        end
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    else
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        read_ack  <= 1'd0;
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    end
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assign o_wb_ack = i_wb_stb && ( start_write || read_ack );
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// Debug DDR3 - Wishbone Bridge  - not synthesizable
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// ========================================================
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//synopsys translate_off
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`ifdef LP_MEMIF_DEBUG
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    always @( posedge i_clk )
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        begin
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        if (start_write)
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            $display("DDR3 Write Addr 0x%08x Data 0x%08h %08h %08h %08h, BE %d%d%d%d %d%d%d%d %d%d%d%d %d%d%d%d",
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                     i_i_wb_adr, i_mwdata[127:96], i_mwdata[95:64], i_mwdata[63:32], i_mwdata[31:0],
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                     i_mwben[15], i_mwben[14], i_mwben[13], i_mwben[12],
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                     i_mwben[11], i_mwben[10], i_mwben[9],  i_mwben[8],
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                     i_mwben[7],  i_mwben[6],  i_mwben[5],  i_mwben[4],
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                     i_mwben[3],  i_mwben[2],  i_mwben[1],  i_mwben[0]
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                     );
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        if (i_rd_empty == 1'd0)
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            $display("DDR3 Read  Addr 0x%08x Data 0x%08h %08h %08h %08h",
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                     i_i_wb_adr, i_rd_data[127:96], i_rd_data [95:64], i_rd_data [63:32], i_rd_data [31:0]);
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        end
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`endif
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//synopsys translate_on
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endmodule
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