| 1 |
2 |
csantifort |
//////////////////////////////////////////////////////////////////
|
| 2 |
|
|
// //
|
| 3 |
|
|
// Wishbone Slave to Xilinx Spartan-6 MCB (DDR3 controller) //
|
| 4 |
|
|
// Bridge //
|
| 5 |
|
|
// //
|
| 6 |
|
|
// This file is part of the Amber project //
|
| 7 |
|
|
// http://www.opencores.org/project,amber //
|
| 8 |
|
|
// //
|
| 9 |
|
|
// Description //
|
| 10 |
|
|
// Converts wishbone read and write accesses to the signalling //
|
| 11 |
|
|
// used by the Xilinx DDR3 Controller in Spartan-6 FPGAs. //
|
| 12 |
|
|
// //
|
| 13 |
|
|
// The MCB is configured with a single 128-bit port. //
|
| 14 |
|
|
// //
|
| 15 |
|
|
// Author(s): //
|
| 16 |
|
|
// - Conor Santifort, csantifort.amber@gmail.com //
|
| 17 |
|
|
// //
|
| 18 |
|
|
//////////////////////////////////////////////////////////////////
|
| 19 |
|
|
// //
|
| 20 |
|
|
// Copyright (C) 2010 Authors and OPENCORES.ORG //
|
| 21 |
|
|
// //
|
| 22 |
|
|
// This source file may be used and distributed without //
|
| 23 |
|
|
// restriction provided that this copyright statement is not //
|
| 24 |
|
|
// removed from the file and that any derivative work contains //
|
| 25 |
|
|
// the original copyright notice and the associated disclaimer. //
|
| 26 |
|
|
// //
|
| 27 |
|
|
// This source file is free software; you can redistribute it //
|
| 28 |
|
|
// and/or modify it under the terms of the GNU Lesser General //
|
| 29 |
|
|
// Public License as published by the Free Software Foundation; //
|
| 30 |
|
|
// either version 2.1 of the License, or (at your option) any //
|
| 31 |
|
|
// later version. //
|
| 32 |
|
|
// //
|
| 33 |
|
|
// This source is distributed in the hope that it will be //
|
| 34 |
|
|
// useful, but WITHOUT ANY WARRANTY; without even the implied //
|
| 35 |
|
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
|
| 36 |
|
|
// PURPOSE. See the GNU Lesser General Public License for more //
|
| 37 |
|
|
// details. //
|
| 38 |
|
|
// //
|
| 39 |
|
|
// You should have received a copy of the GNU Lesser General //
|
| 40 |
|
|
// Public License along with this source; if not, download it //
|
| 41 |
|
|
// from http://www.opencores.org/lgpl.shtml //
|
| 42 |
|
|
// //
|
| 43 |
|
|
//////////////////////////////////////////////////////////////////
|
| 44 |
|
|
|
| 45 |
|
|
|
| 46 |
|
|
module wb_xs6_ddr3_bridge
|
| 47 |
|
|
(
|
| 48 |
|
|
input i_clk,
|
| 49 |
|
|
|
| 50 |
|
|
// Wishbone Bus
|
| 51 |
|
|
input [31:0] i_wb_adr,
|
| 52 |
|
|
input [3:0] i_wb_sel,
|
| 53 |
|
|
input i_wb_we,
|
| 54 |
|
|
output reg [31:0] o_wb_dat = 'd0,
|
| 55 |
|
|
input [31:0] i_wb_dat,
|
| 56 |
|
|
input i_wb_cyc,
|
| 57 |
|
|
input i_wb_stb,
|
| 58 |
|
|
output o_wb_ack,
|
| 59 |
|
|
output o_wb_err,
|
| 60 |
|
|
|
| 61 |
|
|
output reg o_cmd_en = 'd0, // Command Enable
|
| 62 |
|
|
output reg [2:0] o_cmd_instr = 'd0, // write = 000, read = 001
|
| 63 |
|
|
output reg [29:0] o_cmd_byte_addr = 'd0, // Memory address
|
| 64 |
|
|
input i_cmd_full, // DDR3 I/F Command FIFO is full
|
| 65 |
|
|
|
| 66 |
|
|
input i_wr_full, // DDR3 I/F Write Data FIFO is full
|
| 67 |
|
|
output reg o_wr_en = 'd0, // Write data enable
|
| 68 |
|
|
output reg [15:0] o_wr_mask = 'd0, // 1 bit per byte
|
| 69 |
|
|
output reg [127:0] o_wr_data = 'd0, // 16 bytes write data
|
| 70 |
|
|
input [127:0] i_rd_data, // 16 bytes of read data
|
| 71 |
|
|
input i_rd_empty // low when read data is valid
|
| 72 |
|
|
|
| 73 |
|
|
);
|
| 74 |
|
|
|
| 75 |
|
|
wire start_write;
|
| 76 |
|
|
wire start_read;
|
| 77 |
|
|
reg start_write_d1;
|
| 78 |
|
|
reg start_read_d1;
|
| 79 |
|
|
reg start_read_hold = 'd0;
|
| 80 |
|
|
reg [31:0] wb_adr_d1;
|
| 81 |
|
|
wire ddr3_busy;
|
| 82 |
|
|
reg read_ack = 'd0;
|
| 83 |
|
|
reg read_ready = 1'd1;
|
| 84 |
|
|
|
| 85 |
|
|
|
| 86 |
|
|
assign start_write = i_wb_stb && i_wb_we && !start_read_d1;
|
| 87 |
|
|
assign start_read = i_wb_stb && !i_wb_we && read_ready;
|
| 88 |
|
|
assign ddr3_busy = i_cmd_full || i_wr_full;
|
| 89 |
|
|
|
| 90 |
|
|
assign o_wb_err = 'd0;
|
| 91 |
|
|
|
| 92 |
|
|
// ------------------------------------------------------
|
| 93 |
|
|
// Outputs
|
| 94 |
|
|
// ------------------------------------------------------
|
| 95 |
|
|
|
| 96 |
|
|
// Command FIFO
|
| 97 |
|
|
always @( posedge i_clk )
|
| 98 |
|
|
begin
|
| 99 |
|
|
o_cmd_byte_addr <= {wb_adr_d1[29:4], 4'd0};
|
| 100 |
|
|
o_cmd_en <= !ddr3_busy && ( start_write_d1 || start_read_d1 );
|
| 101 |
|
|
o_cmd_instr <= start_write_d1 ? 3'd0 : 3'd1;
|
| 102 |
|
|
end
|
| 103 |
|
|
|
| 104 |
|
|
|
| 105 |
|
|
// ------------------------------------------------------
|
| 106 |
|
|
// Write
|
| 107 |
|
|
// ------------------------------------------------------
|
| 108 |
|
|
always @( posedge i_clk )
|
| 109 |
|
|
begin
|
| 110 |
|
|
o_wr_en <= start_write;
|
| 111 |
|
|
|
| 112 |
|
|
o_wr_mask <= i_wb_adr[3:2] == 2'd0 ? { 12'hfff, ~i_wb_sel } :
|
| 113 |
|
|
i_wb_adr[3:2] == 2'd1 ? { 8'hff, ~i_wb_sel, 4'hf } :
|
| 114 |
|
|
i_wb_adr[3:2] == 2'd2 ? { 4'hf, ~i_wb_sel, 8'hff } :
|
| 115 |
|
|
{ ~i_wb_sel, 12'hfff } ;
|
| 116 |
|
|
|
| 117 |
|
|
o_wr_data <= {4{i_wb_dat}};
|
| 118 |
|
|
end
|
| 119 |
|
|
|
| 120 |
|
|
|
| 121 |
|
|
// ------------------------------------------------------
|
| 122 |
|
|
// Read
|
| 123 |
|
|
// ------------------------------------------------------
|
| 124 |
|
|
always @( posedge i_clk )
|
| 125 |
|
|
begin
|
| 126 |
|
|
if ( read_ack )
|
| 127 |
|
|
read_ready <= 1'd1;
|
| 128 |
|
|
else if ( start_read )
|
| 129 |
|
|
read_ready <= 1'd0;
|
| 130 |
|
|
|
| 131 |
|
|
start_write_d1 <= start_write;
|
| 132 |
|
|
start_read_d1 <= start_read;
|
| 133 |
|
|
wb_adr_d1 <= i_wb_adr;
|
| 134 |
|
|
|
| 135 |
|
|
if ( start_read )
|
| 136 |
|
|
start_read_hold <= 1'd1;
|
| 137 |
|
|
else if ( read_ack )
|
| 138 |
|
|
start_read_hold <= 1'd0;
|
| 139 |
|
|
|
| 140 |
|
|
if ( i_rd_empty == 1'd0 && start_read_hold )
|
| 141 |
|
|
begin
|
| 142 |
|
|
o_wb_dat <= i_wb_adr[3:2] == 2'd0 ? i_rd_data[ 31: 0] :
|
| 143 |
|
|
i_wb_adr[3:2] == 2'd1 ? i_rd_data[ 63:32] :
|
| 144 |
|
|
i_wb_adr[3:2] == 2'd2 ? i_rd_data[ 95:64] :
|
| 145 |
|
|
i_rd_data[127:96] ;
|
| 146 |
|
|
read_ack <= 1'd1;
|
| 147 |
|
|
end
|
| 148 |
|
|
else
|
| 149 |
|
|
read_ack <= 1'd0;
|
| 150 |
|
|
end
|
| 151 |
|
|
|
| 152 |
|
|
assign o_wb_ack = i_wb_stb && ( start_write || read_ack );
|
| 153 |
|
|
|
| 154 |
|
|
|
| 155 |
|
|
endmodule
|
| 156 |
|
|
|
