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//////////////////////////////////////////////////////////////////
//                                                              //
//  Wishbone Slave to Xilinx Spartan-6 MCB (DDR3 controller)    //
//  Bridge                                                      //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Converts wishbone read and write accesses to the signalling //
//  used by the Xilinx DDR3 Controller in Spartan-6 FPGAs.      //
//                                                              //
//  The MCB is configured with a single 128-bit port.           //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
`include "global_defines.v"
 
module wb_xs6_ddr3_bridge #(
parameter WB_DWIDTH   = 32,
parameter WB_SWIDTH   = 4
)(
input                          i_clk,
 
input                          i_mem_ctrl,  // 0=128MB, 1=32MB
 
// Wishbone Bus
input       [31:0]             i_wb_adr,
input       [WB_SWIDTH-1:0]    i_wb_sel,
input                          i_wb_we,
output reg  [WB_DWIDTH-1:0]    o_wb_dat         = 'd0,
input       [WB_DWIDTH-1:0]    i_wb_dat,
input                          i_wb_cyc,
input                          i_wb_stb,
output                         o_wb_ack,
output                         o_wb_err,
 
output                         o_cmd_en,                // Command Enable
output reg [2:0]               o_cmd_instr      = 'd0,  // write = 000, read = 001
output reg [29:0]              o_cmd_byte_addr  = 'd0,  // Memory address
input                          i_cmd_full,              // DDR3 I/F Command FIFO is full
 
input                          i_wr_full,               // DDR3 I/F Write Data FIFO is full
output                         o_wr_en,                 // Write data enable
output reg [15:0]              o_wr_mask        = 'd0,  // 1 bit per byte
output reg [127:0]             o_wr_data        = 'd0,  // 16 bytes write data
input      [127:0]             i_rd_data,               // 16 bytes of read data
input                          i_rd_empty               // low when read data is valid
 
);
 
wire            write_request;
wire            read_request;
reg             write_request_r;
reg             read_request_r;
reg             read_active_r = 'd0;
reg  [29:0]     wb_adr_r;
reg             cmd_full_r = 1'd0;
reg             read_ack_r = 'd0;
reg             read_ready = 1'd1;
reg             cmd_en_r = 'd0;
reg             wr_en_r = 'd0;
wire            write_ack;
 
// Buffer 1 write request
reg                     write_buf_r = 1'd0;
reg     [WB_SWIDTH-1:0] wb_sel_buf_r = 'd0;
reg     [WB_DWIDTH-1:0] wb_dat_buf_r = 'd0;
reg     [31:0]          wb_adr_buf_r = 'd0;
wire    [WB_SWIDTH-1:0] wb_sel;
wire    [WB_DWIDTH-1:0] wb_dat;
wire    [31:0]          wb_adr;
 
 
assign write_request = i_wb_stb && i_wb_we && !read_request_r;
assign read_request  = i_wb_stb && !i_wb_we && read_ready;
 
assign o_wb_err      = 'd0;
 
// ------------------------------------------------------
// Outputs
// ------------------------------------------------------
always @( posedge i_clk )
    cmd_full_r       <= i_cmd_full;
 
// Command FIFO
always @( posedge i_clk )
    if ( !i_cmd_full )
        begin
        o_cmd_byte_addr  <= {wb_adr_r[29:4], 4'd0};
        cmd_en_r         <= ( write_request_r || read_request_r );
        o_cmd_instr      <= write_request_r ? 3'd0 : 3'd1;
        end
 
assign o_cmd_en = cmd_en_r && !i_cmd_full;
 
 
// ------------------------------------------------------
// Write Buffer
// ------------------------------------------------------
always @( posedge i_clk )
    if ( i_cmd_full && write_request )
        begin
        write_buf_r     <= 1'd1;
        wb_sel_buf_r    <= i_wb_sel;
        wb_dat_buf_r    <= i_wb_dat;
        wb_adr_buf_r    <= i_wb_adr;
        end
    else if ( !i_cmd_full )
        write_buf_r     <= 1'd0;
 
// ------------------------------------------------------
// Write
// ------------------------------------------------------
 
// Select between incoming reqiests and the write request buffer
assign wb_sel = write_buf_r ? wb_sel_buf_r : i_wb_sel;
assign wb_dat = write_buf_r ? wb_dat_buf_r : i_wb_dat;
assign wb_adr = write_buf_r ? wb_adr_buf_r : i_wb_adr;
 
 
generate
if (WB_DWIDTH == 32) begin :wb32w
 
    always @( posedge i_clk )
        if ( !i_cmd_full )
            begin
            wr_en_r    <= write_request || write_buf_r;
 
            o_wr_mask  <= wb_adr[3:2] == 2'd0 ? { 12'hfff, ~wb_sel          } :
                          wb_adr[3:2] == 2'd1 ? { 8'hff,   ~wb_sel, 4'hf    } :
                          wb_adr[3:2] == 2'd2 ? { 4'hf,    ~wb_sel, 8'hff   } :
                                                {          ~wb_sel, 12'hfff } ;
 
            o_wr_data  <= {4{wb_dat}};
            end
 
end
else begin : wb128w
 
    always @( posedge i_clk )
        if ( !i_cmd_full )
            begin
            wr_en_r    <= write_request;
            o_wr_mask  <= ~wb_sel;
            o_wr_data  <= wb_dat;
            end
 
end
endgenerate
 
assign o_wr_en = wr_en_r && !i_cmd_full;
 
 
// ------------------------------------------------------
// Read
// ------------------------------------------------------
always @( posedge i_clk )
    begin
    if ( read_ack_r )
        read_ready <= 1'd1;
    else if ( read_request )
        read_ready <= 1'd0;
 
    if ( !i_cmd_full )
        begin
        write_request_r  <= write_request;
        read_request_r   <= read_request;
        wb_adr_r         <= i_mem_ctrl ? {5'd0, i_wb_adr[24:0]} : i_wb_adr[29:0];
        end
 
    if ( read_request  )
        read_active_r <= 1'd1;
    else if ( read_ack_r )
        read_active_r <= 1'd0;
 
    if ( i_rd_empty == 1'd0 && read_active_r )
        read_ack_r  <= 1'd1;
    else
        read_ack_r  <= 1'd0;
    end
 
 
generate
if (WB_DWIDTH == 32) begin :wb32r
 
    always @( posedge i_clk )
        if ( !i_rd_empty && read_active_r )
            o_wb_dat  <= i_wb_adr[3:2] == 2'd0 ? i_rd_data[ 31: 0] :
                         i_wb_adr[3:2] == 2'd1 ? i_rd_data[ 63:32] :
                         i_wb_adr[3:2] == 2'd2 ? i_rd_data[ 95:64] :
                                                 i_rd_data[127:96] ;
 
end
else begin : wb128r
 
    always @( posedge i_clk )
        if ( !i_rd_empty && read_active_r )
            o_wb_dat  <= i_rd_data;
 
end
endgenerate
 
assign write_ack = write_request && !write_buf_r;
assign o_wb_ack  = ( i_wb_stb && read_ack_r ) || write_ack;
 
 
endmodule
 

Line No.	Rev	Author	Line
1	2	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Wishbone Slave to Xilinx Spartan-6 MCB (DDR3 controller) //`
4			`// Bridge //`
5			`// //`
6			`// This file is part of the Amber project //`
7			`// http://www.opencores.org/project,amber //`
8			`// //`
9			`// Description //`
10			`// Converts wishbone read and write accesses to the signalling //`
11			`// used by the Xilinx DDR3 Controller in Spartan-6 FPGAs. //`
12			`// //`
13			`// The MCB is configured with a single 128-bit port. //`
14			`// //`
15			`// Author(s): //`
16			`// - Conor Santifort, csantifort.amber@gmail.com //`
17			`// //`
18			`//////////////////////////////////////////////////////////////////`
19			`// //`
20			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
21			`// //`
22			`// This source file may be used and distributed without //`
23			`// restriction provided that this copyright statement is not //`
24			`// removed from the file and that any derivative work contains //`
25			`// the original copyright notice and the associated disclaimer. //`
26			`// //`
27			`// This source file is free software; you can redistribute it //`
28			`// and/or modify it under the terms of the GNU Lesser General //`
29			`// Public License as published by the Free Software Foundation; //`
30			`// either version 2.1 of the License, or (at your option) any //`
31			`// later version. //`
32			`// //`
33			`// This source is distributed in the hope that it will be //`
34			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
35			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
36			`// PURPOSE. See the GNU Lesser General Public License for more //`
37			`// details. //`
38			`// //`
39			`// You should have received a copy of the GNU Lesser General //`
40			`// Public License along with this source; if not, download it //`
41			`// from http://www.opencores.org/lgpl.shtml //`
42			`// //`
43			`//////////////////////////////////////////////////////////////////`
44	63	csantifort	`include "global_defines.v"
45	2	csantifort
46	36	csantifort	`module wb_xs6_ddr3_bridge #(`
47			`parameter WB_DWIDTH = 32,`
48			`parameter WB_SWIDTH = 4`
49			`)(`
50	2	csantifort	`input i_clk,`
51
52	11	csantifort	`input i_mem_ctrl, // 0=128MB, 1=32MB`
53
54	2	csantifort	`// Wishbone Bus`
55			`input [31:0] i_wb_adr,`
56	36	csantifort	`input [WB_SWIDTH-1:0] i_wb_sel,`
57	2	csantifort	`input i_wb_we,`
58	36	csantifort	`output reg [WB_DWIDTH-1:0] o_wb_dat = 'd0,`
59			`input [WB_DWIDTH-1:0] i_wb_dat,`
60	2	csantifort	`input i_wb_cyc,`
61			`input i_wb_stb,`
62			`output o_wb_ack,`
63			`output o_wb_err,`
64
65	15	csantifort	`output o_cmd_en, // Command Enable`
66	2	csantifort	`output reg [2:0] o_cmd_instr = 'd0, // write = 000, read = 001`
67			`output reg [29:0] o_cmd_byte_addr = 'd0, // Memory address`
68			`input i_cmd_full, // DDR3 I/F Command FIFO is full`
69
70			`input i_wr_full, // DDR3 I/F Write Data FIFO is full`
71	15	csantifort	`output o_wr_en, // Write data enable`
72	2	csantifort	`output reg [15:0] o_wr_mask = 'd0, // 1 bit per byte`
73			`output reg [127:0] o_wr_data = 'd0, // 16 bytes write data`
74			`input [127:0] i_rd_data, // 16 bytes of read data`
75			`input i_rd_empty // low when read data is valid`
76
77			`);`
78
79	36	csantifort	`wire write_request;`
80			`wire read_request;`
81			`reg write_request_r;`
82			`reg read_request_r;`
83			`reg read_active_r = 'd0;`
84			`reg [29:0] wb_adr_r;`
85			`reg cmd_full_r = 1'd0;`
86			`reg read_ack_r = 'd0;`
87	2	csantifort	`reg read_ready = 1'd1;`
88	15	csantifort	`reg cmd_en_r = 'd0;`
89			`reg wr_en_r = 'd0;`
90	36	csantifort	`wire write_ack;`
91	2	csantifort
92	36	csantifort	`// Buffer 1 write request`
93			`reg write_buf_r = 1'd0;`
94			`reg [WB_SWIDTH-1:0] wb_sel_buf_r = 'd0;`
95			`reg [WB_DWIDTH-1:0] wb_dat_buf_r = 'd0;`
96			`reg [31:0] wb_adr_buf_r = 'd0;`
97			`wire [WB_SWIDTH-1:0] wb_sel;`
98			`wire [WB_DWIDTH-1:0] wb_dat;`
99			`wire [31:0] wb_adr;`
100	2	csantifort
101
102	36	csantifort	`assign write_request = i_wb_stb && i_wb_we && !read_request_r;`
103			`assign read_request = i_wb_stb && !i_wb_we && read_ready;`
104
105			`assign o_wb_err = 'd0;`
106
107	2	csantifort	`// ------------------------------------------------------`
108			`// Outputs`
109			`// ------------------------------------------------------`
110	36	csantifort	`always @( posedge i_clk )`
111			`cmd_full_r <= i_cmd_full;`
112	2	csantifort
113			`// Command FIFO`
114			`always @( posedge i_clk )`
115	36	csantifort	`if ( !i_cmd_full )`
116	15	csantifort	`begin`
117	36	csantifort	`o_cmd_byte_addr <= {wb_adr_r[29:4], 4'd0};`
118			`cmd_en_r <= ( write_request_r \|\| read_request_r );`
119			`o_cmd_instr <= write_request_r ? 3'd0 : 3'd1;`
120	15	csantifort	`end`
121	2	csantifort
122	15	csantifort	`assign o_cmd_en = cmd_en_r && !i_cmd_full;`
123	2	csantifort
124	36	csantifort
125	2	csantifort	`// ------------------------------------------------------`
126	36	csantifort	`// Write Buffer`
127	2	csantifort	`// ------------------------------------------------------`
128			`always @( posedge i_clk )`
129	36	csantifort	`if ( i_cmd_full && write_request )`
130	15	csantifort	`begin`
131	36	csantifort	`write_buf_r <= 1'd1;`
132			`wb_sel_buf_r <= i_wb_sel;`
133			`wb_dat_buf_r <= i_wb_dat;`
134			`wb_adr_buf_r <= i_wb_adr;`
135	15	csantifort	`end`
136	36	csantifort	`else if ( !i_cmd_full )`
137			`write_buf_r <= 1'd0;`
138	2	csantifort
139	36	csantifort	`// ------------------------------------------------------`
140			`// Write`
141			`// ------------------------------------------------------`
142
143			`// Select between incoming reqiests and the write request buffer`
144			`assign wb_sel = write_buf_r ? wb_sel_buf_r : i_wb_sel;`
145			`assign wb_dat = write_buf_r ? wb_dat_buf_r : i_wb_dat;`
146			`assign wb_adr = write_buf_r ? wb_adr_buf_r : i_wb_adr;`
147
148
149			`generate`
150			`if (WB_DWIDTH == 32) begin :wb32w`
151
152			`always @( posedge i_clk )`
153			`if ( !i_cmd_full )`
154			`begin`
155			`wr_en_r <= write_request \|\| write_buf_r;`
156
157			`o_wr_mask <= wb_adr[3:2] == 2'd0 ? { 12'hfff, ~wb_sel } :`
158			`wb_adr[3:2] == 2'd1 ? { 8'hff, ~wb_sel, 4'hf } :`
159			`wb_adr[3:2] == 2'd2 ? { 4'hf, ~wb_sel, 8'hff } :`
160			`{ ~wb_sel, 12'hfff } ;`
161
162			`o_wr_data <= {4{wb_dat}};`
163			`end`
164
165			`end`
166			`else begin : wb128w`
167
168			`always @( posedge i_clk )`
169			`if ( !i_cmd_full )`
170			`begin`
171			`wr_en_r <= write_request;`
172			`o_wr_mask <= ~wb_sel;`
173			`o_wr_data <= wb_dat;`
174			`end`
175
176			`end`
177			`endgenerate`
178
179	15	csantifort	`assign o_wr_en = wr_en_r && !i_cmd_full;`
180	36	csantifort
181
182	2	csantifort	`// ------------------------------------------------------`
183			`// Read`
184			`// ------------------------------------------------------`
185			`always @( posedge i_clk )`
186			`begin`
187	36	csantifort	`if ( read_ack_r )`
188	2	csantifort	`read_ready <= 1'd1;`
189	36	csantifort	`else if ( read_request )`
190	2	csantifort	`read_ready <= 1'd0;`
191
192	36	csantifort	`if ( !i_cmd_full )`
193	15	csantifort	`begin`
194	36	csantifort	`write_request_r <= write_request;`
195			`read_request_r <= read_request;`
196			`wb_adr_r <= i_mem_ctrl ? {5'd0, i_wb_adr[24:0]} : i_wb_adr[29:0];`
197	15	csantifort	`end`
198
199	36	csantifort	`if ( read_request )`
200			`read_active_r <= 1'd1;`
201			`else if ( read_ack_r )`
202			`read_active_r <= 1'd0;`
203	2	csantifort
204	36	csantifort	`if ( i_rd_empty == 1'd0 && read_active_r )`
205			`read_ack_r <= 1'd1;`
206	2	csantifort	`else`
207	36	csantifort	`read_ack_r <= 1'd0;`
208	2	csantifort	`end`
209
210	36	csantifort
211			`generate`
212			`if (WB_DWIDTH == 32) begin :wb32r`
213
214			`always @( posedge i_clk )`
215			`if ( !i_rd_empty && read_active_r )`
216			`o_wb_dat <= i_wb_adr[3:2] == 2'd0 ? i_rd_data[ 31: 0] :`
217			`i_wb_adr[3:2] == 2'd1 ? i_rd_data[ 63:32] :`
218			`i_wb_adr[3:2] == 2'd2 ? i_rd_data[ 95:64] :`
219			`i_rd_data[127:96] ;`
220
221			`end`
222			`else begin : wb128r`
223
224			`always @( posedge i_clk )`
225			`if ( !i_rd_empty && read_active_r )`
226			`o_wb_dat <= i_rd_data;`
227
228			`end`
229			`endgenerate`
230
231			`assign write_ack = write_request && !write_buf_r;`
232			`assign o_wb_ack = ( i_wb_stb && read_ack_r ) \|\| write_ack;`
233
234	2	csantifort
235			`endmodule`
236

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