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//////////////////////////////////////////////////////////////////
//                                                              //
//  Top-level module instantiating the entire Amber 2 system.   //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  This is the highest level synthesizable module in the       //
//  project. The ports in this module represent pins on the     //
//  FPGA.                                                       //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2012 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
`include "global_timescale.vh"
 
module eth_test
(
// MD interface - serial configuration of PHY
inout                       md_io,
input                       mdc_i,
 
// MAC interface - packet to DUT
input                       mtx_clk_i,
output reg [3:0]            mtxd_o,
output reg                  mtxdv_o,
output reg                  mtxerr_o,
 
 
// MAC interface - packet from DUT
input      [3:0]            mrxd_i,
input                       mrxdv_i
);
 
`include "debug_functions.vh"
`include "system_functions.vh"
 
// mxt state machine
localparam IDLE = 4'd0;
localparam TX_0 = 4'd1;
localparam TX_1 = 4'd2;
localparam WAIT = 4'd3;
localparam PREA = 4'd4;
localparam PREB = 4'd5;
localparam GAP  = 4'd6;
localparam CRC0 = 4'd7;
localparam CRCN = 4'd8;
localparam POLL = 4'd9;
 
 
// rx state machine
localparam RX_IDLE = 4'd0;
localparam RX_0    = 4'd1;
localparam RX_1    = 4'd2;
localparam RX_PRE  = 4'd3;
localparam RX_DONE = 4'd4;
 
 
// md state machine
localparam MD_REGADDR = 4'd0;
localparam MD_PHYADDR = 4'd1;
localparam MD_WRITE0  = 4'd2;
localparam MD_READ0   = 4'd3;
localparam MD_START1  = 4'd4;
localparam MD_START0  = 4'd5;
localparam MD_IDLE    = 4'd6;
localparam MD_TURN0   = 4'd7;
localparam MD_TURN1   = 4'd8;
localparam MD_RDATA   = 4'd9;
localparam MD_WDATA   = 4'd10;
localparam MD_WXFR    = 4'd11;
 
localparam MDREAD  = 1'd0;
localparam MDWRITE = 1'd1;
 
 
// MD register addresses        
localparam MII_BMCR     = 5'd0;        /* Basic mode control register */
localparam MII_BMSR     = 5'd1;        /* Basic mode status register  */
localparam MII_CTRL1000 = 5'd9;        /* 1000BASE-T control          */
 
 
reg [7:0]   mem [2**16-1:0];
reg [7:0]   eth [13:0];
 
reg [7:0]   rxm [2047:0];
 
reg [15:0]  line_r  = 16'd0;
reg [15:0]  rx_line_r;
 
reg [3:0]   state_r = IDLE;
reg [3:0]   md_state_r = MD_IDLE;
reg [3:0]   rx_state_r = RX_IDLE;
reg [15:0]  pkt_len_r;
reg [31:0]  wcount_r;
reg [15:0]  pkt_pos_r;
reg [3:0]   pcount_r;
 
reg         md_op_r = MDREAD;
reg [4:0]   md_count_r;
reg [4:0]   md_phy_addr_r;
reg [4:0]   md_reg_addr_r;
reg [15:0]  md_rdata_r;
reg [15:0]  md_wdata_r;
reg [15:0]  md_bmcr_r = 'd0;
reg [15:0]  md_ctrl1000_r = 16'hffff;
wire        init;
wire [31:0] crc;
wire [3:0]  crc_dinx;
reg  [3:0]  crc_din;
wire        enable;
reg  [3:0]  mrxd_r;
 
reg  [7:0]  last_pkt_num_r = 'd0;
 
 
integer             pkt_to_amber_file;
integer             pkt_to_amber_ack_file;
integer             pkt_from_amber_file;
 
reg [8*20-1:0]      pkt_to_amber     = "pkt_to_amber.mem";
reg [8*20-1:0]      pkt_to_amber_ack = "pkt_to_amber_ack.txt";
reg [8*20-1:0]      pkt_from_amber   = "pkt_from_amber.mem";
 
reg     [4*8-1:0]   line;
integer             fgets_return;
integer             pkt_to_amber_address;
reg [7:0]           pkt_to_amber_data;
 
integer             x;
reg [7:0]           pkt_from_amber_num = 8'd1;
 
 
// initializwe the ack file to 0
// this allows sim_socket to write the first packet
initial
    begin
    pkt_to_amber_ack_file = $fopen(pkt_to_amber_ack, "w");
    $fwrite(pkt_to_amber_ack_file, "0\n");
    $fclose(pkt_to_amber_ack_file);
    end
 
 
// ============================
// packet tx state machine
// ============================
always@(posedge mtx_clk_i)
    begin
    case (state_r)
        IDLE:
            begin
            mtxd_o    <= 'd0;
            mtxdv_o   <= 'd0;
            mtxerr_o  <= 'd0;
            wcount_r  <= 'd0;
 
            if (md_bmcr_r[9])  // autoneg bit set by software
                begin
                wcount_r  <= wcount_r + 1'd1;
                if (wcount_r == 32'd10000)
                    begin
                    state_r   <= POLL;
                    wcount_r  <= 'd0;
                    $display("Start polling for packets to send to amber");
                    end
                end
            end
 
 
 
        WAIT:
            begin
            wcount_r <= wcount_r + 1'd1;
            if (wcount_r == 32'd100)
                begin
                wcount_r <= 'd0;
                state_r  <= POLL;
                end
            end
 
 
        POLL: // scan for new packets
            begin
            mtxd_o    <= 'd0;
            mtxdv_o   <= 'd0;
            mtxerr_o  <= 'd0;
 
 
            pkt_to_amber_file               = $fopen(pkt_to_amber, "r");
            fgets_return                    = $fgets(line, pkt_to_amber_file);
            pkt_to_amber_address = 0;
            while (fgets_return)
                begin
                pkt_to_amber_data           = hex_chars_to_8bits (line[23:8]);
                mem[pkt_to_amber_address]   = pkt_to_amber_data[7:0];
                pkt_to_amber_address        = pkt_to_amber_address + 1;
                fgets_return                = $fgets(line, pkt_to_amber_file);
                end
            $fclose(pkt_to_amber_file);
 
 
            if (mem[0] != last_pkt_num_r)
                begin
                state_r         <= PREA;
                pkt_len_r       <= {mem[1], mem[2]} + 16'd14;
                last_pkt_num_r  <= mem[0];
                line_r          <= 'd0;
                pkt_pos_r       <= 'd0;
                pcount_r        <= 'd0;
                wcount_r        <= 'd0;
 
                pkt_to_amber_ack_file = $fopen(pkt_to_amber_ack, "w");
                $fwrite(pkt_to_amber_ack_file, "%d\n", mem[0]);
                $fclose(pkt_to_amber_ack_file);
                end
            else begin
                state_r   <= WAIT;
                end
 
            end
 
 
 
        PREA: // Preamble
            begin
            mtxd_o    <= 4'b0101;
            mtxdv_o   <= 1'd1;
            pcount_r  <= pcount_r + 1'd1;
            if (pcount_r == 4'd6)
                begin
                pcount_r  <= 'd0;
                state_r   <= PREB;
                end
            end
 
 
        PREB:
            begin
            mtxd_o    <= 4'b1101;
            mtxdv_o   <= 1'd1;
            state_r   <= TX_0;
 
            print_pkt(1'd1, line_r);
            end
 
 
        TX_0:  // low 4 bits
            begin
            mtxd_o    <= mem[line_r+3][3:0];
            mtxdv_o   <= 1'd1;
            state_r   <= TX_1;
            end
 
 
        TX_1:  // high 4 bits
            begin
            mtxd_o    <= mem[line_r+3][7:4];
            mtxdv_o   <= 1'd1;
            line_r    <= line_r + 1'd1;
 
            if (pkt_pos_r + 1'd1 == pkt_len_r)
                state_r     <= CRC0;
            else
                begin
                state_r     <= TX_0;
                pkt_pos_r   <= pkt_pos_r + 1'd1;
                end
            end
 
 
        CRC0:
            begin
            mtxd_o    <= {~crc[28], ~crc[29], ~crc[30], ~crc[31]};
            mtxdv_o   <= 1'd1;
            state_r   <= POLL;
            end
 
    endcase
    end
 
 
 
assign init    = state_r == PREB;
assign enable  = state_r != CRC0;
 
always @*
    begin
        crc_din = state_r == TX_0 ? mem[line_r+3][3:0] :
                  state_r == TX_1 ? mem[line_r+3][7:4] :
                                   32'd0               ;
    end
 
 
assign crc_dinx = {crc_din[0], crc_din[1], crc_din[2], crc_din[3]};
 
 
// Gen CRC, using the EthMac CRC generator
eth_crc eth_crc (
    .Clk        ( mtx_clk_i ),
    .Reset      ( 1'd0      ),
    .Data       ( crc_dinx  ),
    .Enable     ( enable    ),
    .Initialize ( init      ),
 
    .Crc        ( crc       ),
    .CrcError   (           )
);
 
 
// ============================
// packet rx state machine
// ============================
always@(posedge mtx_clk_i)
    begin
    case (rx_state_r)
        RX_IDLE:
            begin
            rx_line_r  <= 'd0;
            if (mrxdv_i)  // autoneg bit set by software
                begin
                rx_state_r   <= RX_PRE;
                end
            end
 
        RX_PRE:
            begin
            if (mrxd_i == 4'hd)
                rx_state_r   <= RX_0;
            end
 
        RX_0:  // low 4 bits
            begin
            mrxd_r <= mrxd_i;
 
            if (mrxdv_i)
                rx_state_r     <= RX_1;
            else
                rx_state_r     <= RX_DONE;
            end
 
 
        RX_1:  // high 4 bits
            begin
            rxm[rx_line_r]      <= {mrxd_i, mrxd_r};
            rx_line_r           <= rx_line_r + 1'd1;
 
            if (mrxdv_i)
                rx_state_r     <= RX_0;
            else
                rx_state_r     <= RX_DONE;
            end
 
 
        RX_DONE:
            begin
            print_pkt(1'd0, 16'd0);
            rx_state_r     <= RX_IDLE;
 
 
            pkt_from_amber_file     = $fopen(pkt_from_amber, "w");
            $fwrite(pkt_from_amber_file, "%02h\n", pkt_from_amber_num);
 
            for (x=0;x<rx_line_r;x=x+1)
                $fwrite(pkt_from_amber_file, "%02h\n", rxm[x]);
            $fclose(pkt_from_amber_file);
 
 
            if (pkt_from_amber_num == 8'd255)
                pkt_from_amber_num  <= 8'd1;
            else
                pkt_from_amber_num  <=  pkt_from_amber_num + 1'd1;
            end
 
 
    endcase
    end
 
 
 
 
// ============================
// management data state machine
// ============================
always@(posedge mdc_i)
    begin
    case (md_state_r)
 
        MD_IDLE:
            begin
            md_count_r <= 'd0;
            if (md_io == 1'd0)
                md_state_r   <= MD_START0;
            end
 
 
        MD_START0:
            begin
            if (md_io == 1'd1)
                md_state_r   <= MD_START1;
            else
                md_state_r   <= MD_IDLE;
            end
 
 
        MD_START1:
            begin
            if (md_io == 1'd1)
                md_state_r  <= MD_READ0;
            else
                md_state_r  <= MD_WRITE0;
            end
 
 
       MD_READ0:
            begin
            if (md_io == 1'd0)
                begin
                md_state_r  <= MD_PHYADDR;
                md_op_r     <= MDREAD;
                end
            else
                md_state_r  <= MD_IDLE;
            end
 
 
       MD_WRITE0:
            begin
            if (md_io == 1'd1)
                begin
                md_state_r  <= MD_PHYADDR;
                md_op_r     <= MDWRITE;
                end
            else
                md_state_r  <= MD_IDLE;
            end
 
        MD_PHYADDR:
            begin
            md_count_r      <= md_count_r + 1'd1;
            md_phy_addr_r   <= {md_phy_addr_r[3:0], md_io};
 
            if (md_count_r == 5'd4)
                begin
                md_state_r  <= MD_REGADDR;
                md_count_r  <= 'd0;
                end
            end
 
        MD_REGADDR:
            begin
            md_count_r      <= md_count_r + 1'd1;
            md_reg_addr_r   <= {md_reg_addr_r[3:0], md_io};
 
            if (md_count_r == 5'd4)
                begin
                md_count_r  <= 'd0;
                md_state_r  <= MD_TURN0;
                end
            end
 
 
        MD_TURN0:
            md_state_r  <= MD_TURN1;
 
        MD_TURN1:
            begin
            if (md_op_r == MDREAD)
                md_state_r  <= MD_RDATA;
            else
                md_state_r  <= MD_WDATA;
 
            case (md_reg_addr_r)
                MII_BMCR        : md_rdata_r <= md_bmcr_r;
                MII_BMSR        : md_rdata_r <= 16'hfe04;
                MII_CTRL1000    : md_rdata_r <= md_ctrl1000_r;
                default         : md_rdata_r <= 'd0;
            endcase
            end
 
 
        MD_RDATA:
            begin
            md_count_r  <= md_count_r + 1'd1;
            md_rdata_r  <= {md_rdata_r[14:0], 1'd0};
 
            if (md_count_r == 5'd15)
                md_state_r  <= MD_IDLE;
 
            end
 
 
        MD_WDATA:
            begin
            md_count_r  <= md_count_r + 1'd1;
            md_wdata_r  <= {md_wdata_r[14:0], md_io};
 
            if (md_count_r == 5'd15)
                begin
                md_state_r  <= MD_WXFR;
                md_count_r  <= 'd0;
                end
            end
 
 
        MD_WXFR:
            begin
            case (md_reg_addr_r)
                MII_BMCR        : md_bmcr_r     <= md_wdata_r;
                MII_CTRL1000    : md_ctrl1000_r <= md_wdata_r;
            endcase
            md_state_r  <= MD_IDLE;
            end
 
 
    endcase
    end
 
 
assign md_io = md_state_r == MD_RDATA ? md_rdata_r[15] : 1'bz;
 
 
 
task print_pkt;
input        tx;   /* 1 for tx, 0 for rx */
input [31:0] start;
reg   [15:0] eth_type;
reg   [7:0]  proto;
reg   [31:0] frame;
reg   [3:0]  ip_hdr_len;
reg   [15:0] ip_len;
reg   [3:0]  tcp_hdr_len;
reg   [15:0] tcp_bdy_len;
reg   [7:0]  tmp;
reg   [15:0] arp_op;
 
integer      i;
begin
    frame = start;
 
    if (tx) $write("%6d pkt to   amber ", tb.clk_count);
    else    $write("%6d pkt from amber ", tb.clk_count);
 
    $display("mac-dst %h:%h:%h:%h:%h:%h, mac-src %h:%h:%h:%h:%h:%h, type %h%h",
        rmem(tx,frame+0), rmem(tx,frame+1),rmem(tx,frame+2),rmem(tx,frame+3),rmem(tx,frame+4),rmem(tx,frame+5),
        rmem(tx,frame+6), rmem(tx,frame+7),rmem(tx,frame+8),rmem(tx,frame+9),rmem(tx,frame+10),rmem(tx,frame+11),
        rmem(tx,frame+12),rmem(tx,frame+13));
 
    eth_type = {rmem(tx,frame+12),rmem(tx,frame+13)};
 
    if (eth_type == 16'h0806) // arp
        begin
        frame       = frame + 14;
        arp_op      = rmem(tx,frame+6) << 8 | rmem(tx,frame+7);
 
        $write("ARP operation %0d", arp_op);
 
        if (arp_op == 16'd1)
            $write(" look for ip %0d.%0d.%0d.%0d",
                rmem(tx,frame+24), rmem(tx,frame+25),rmem(tx,frame+26),rmem(tx,frame+27));
        $write("\n");
        end
 
    if (eth_type == 16'h0800) // ip
        begin
        frame       = frame + 14;
        proto       = rmem(tx,frame+9);
        tmp         = rmem(tx,frame+0);
        ip_hdr_len  = tmp[3:0];
        ip_len      = {rmem(tx,frame+2), rmem(tx,frame+3)};
 
        $display("   ip-dst %0d.%0d.%0d.%0d, ip-src %0d.%0d.%0d.%0d, proto %0d, ip_len %0d, ihl %0d",
            rmem(tx,frame+16), rmem(tx,frame+17),rmem(tx,frame+18),rmem(tx,frame+19),
            rmem(tx,frame+12), rmem(tx,frame+13),rmem(tx,frame+14),rmem(tx,frame+15),
            proto, ip_len, ip_hdr_len*4);
 
        if (proto == 8'd6) // TCP
            begin
            frame       = frame + ip_hdr_len*4;
            tmp         = rmem(tx,frame+12);
            tcp_hdr_len = tmp[7:4];
            tcp_bdy_len = ip_len - ({ip_hdr_len,2'd0} + {tcp_hdr_len,2'd0});
 
            $display("   tcp-dst %0d, tcp-src %0d, tcp hdr len %0d, tcp bdy len %0d",
                {rmem(tx,frame+2), rmem(tx,frame+3)},
                {rmem(tx,frame+0), rmem(tx,frame+1)}, tcp_hdr_len*4, tcp_bdy_len);
            $display("   tcp-seq %0d, tcp-ack %0d",
                {rmem(tx,frame+4), rmem(tx,frame+5), rmem(tx,frame+6), rmem(tx,frame+7)},
                {rmem(tx,frame+8), rmem(tx,frame+9), rmem(tx,frame+10), rmem(tx,frame+11)});
 
            if (tcp_bdy_len != 16'd0)
                begin
                for (i=0;i<tcp_bdy_len;i=i+1)
                    if ((rmem(tx,frame+tcp_hdr_len*4+i) > 31 && rmem(tx,frame+tcp_hdr_len*4+i) < 128) ||
                        (rmem(tx,frame+tcp_hdr_len*4+i) == "\n"))
                        $write("%c",  rmem(tx,frame+tcp_hdr_len*4+i));
                end
 
            end
        end
    $display("----");
end
endtask
 
 
function [7:0] rmem;
input        tx;   /* 1 for tx, 0 for rx */
input [31:0] addr;
begin
    if (tx)
        rmem = mem[addr+3];
    else
        rmem = rxm[addr];
end
endfunction
 
 
wire [8*6-1:0] XSTATE =
    state_r == IDLE ? "IDLE"    :
    state_r == WAIT ? "WAIT"    :
    state_r == TX_0 ? "TX_0"    :
    state_r == TX_1 ? "TX_1"    :
    state_r == PREA ? "PREA"    :
    state_r == PREB ? "PREB"    :
    state_r == GAP  ? "GAP"     :
    state_r == CRC0 ? "CRC0"    :
    state_r == CRCN ? "CRCN"    :
    state_r == POLL ? "POLL"    :
                      "UNKNOWN" ;
 
wire [8*12-1:0] XRXSTATE =
    state_r == RX_IDLE  ? "RX_IDLE" :
    state_r == RX_0     ? "RX_0"    :
    state_r == RX_1     ? "RX_1"    :
    state_r == RX_PRE   ? "RX_PRE"  :
    state_r == RX_DONE  ? "RX_DONE" :
                          "UNKNOWN" ;
 
wire [8*12-1:0] XMDSTATE =
    md_state_r == MD_WXFR    ?  "MD_WXFR"    :
    md_state_r == MD_WDATA   ?  "MD_WDATA"   :
    md_state_r == MD_RDATA   ?  "MD_RDATA"   :
    md_state_r == MD_TURN1   ?  "MD_TURN1"   :
    md_state_r == MD_TURN0   ?  "MD_TURN0"   :
    md_state_r == MD_REGADDR ?  "MD_REGADDR" :
    md_state_r == MD_PHYADDR ?  "MD_PHYADDR" :
    md_state_r == MD_WRITE0  ?  "MD_WRITE0"  :
    md_state_r == MD_READ0   ?  "MD_READ0"   :
    md_state_r == MD_START1  ?  "MD_START1"  :
    md_state_r == MD_START0  ?  "MD_START0"  :
    md_state_r == MD_IDLE    ?  "MD_IDLE"    :
                                "UNKNOWN"    ;
 
endmodule
 
 

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[/] [amber/] [trunk/] [hw/] [vlog/] [tb/] [eth_test.v] - Blame information for rev 82

Line No.	Rev	Author	Line
1	61	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Top-level module instantiating the entire Amber 2 system. //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// This is the highest level synthesizable module in the //`
10			`// project. The ports in this module represent pins on the //`
11			`// FPGA. //`
12			`// //`
13			`// Author(s): //`
14			`// - Conor Santifort, csantifort.amber@gmail.com //`
15			`// //`
16			`//////////////////////////////////////////////////////////////////`
17			`// //`
18			`// Copyright (C) 2012 Authors and OPENCORES.ORG //`
19			`// //`
20			`// This source file may be used and distributed without //`
21			`// restriction provided that this copyright statement is not //`
22			`// removed from the file and that any derivative work contains //`
23			`// the original copyright notice and the associated disclaimer. //`
24			`// //`
25			`// This source file is free software; you can redistribute it //`
26			`// and/or modify it under the terms of the GNU Lesser General //`
27			`// Public License as published by the Free Software Foundation; //`
28			`// either version 2.1 of the License, or (at your option) any //`
29			`// later version. //`
30			`// //`
31			`// This source is distributed in the hope that it will be //`
32			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
33			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
34			`// PURPOSE. See the GNU Lesser General Public License for more //`
35			`// details. //`
36			`// //`
37			`// You should have received a copy of the GNU Lesser General //`
38			`// Public License along with this source; if not, download it //`
39			`// from http://www.opencores.org/lgpl.shtml //`
40			`// //`
41			`//////////////////////////////////////////////////////////////////`
42	82	csantifort	`include "global_timescale.vh"
43	61	csantifort
44			`module eth_test`
45			`(`
46			`// MD interface - serial configuration of PHY`
47			`inout md_io,`
48			`input mdc_i,`
49
50			`// MAC interface - packet to DUT`
51			`input mtx_clk_i,`
52			`output reg [3:0] mtxd_o,`
53			`output reg mtxdv_o,`
54			`output reg mtxerr_o,`
55
56
57			`// MAC interface - packet from DUT`
58			`input [3:0] mrxd_i,`
59			`input mrxdv_i`
60			`);`
61
62	82	csantifort	`include "debug_functions.vh"
63			`include "system_functions.vh"
64	61	csantifort
65			`// mxt state machine`
66			`localparam IDLE = 4'd0;`
67			`localparam TX_0 = 4'd1;`
68			`localparam TX_1 = 4'd2;`
69			`localparam WAIT = 4'd3;`
70			`localparam PREA = 4'd4;`
71			`localparam PREB = 4'd5;`
72			`localparam GAP = 4'd6;`
73			`localparam CRC0 = 4'd7;`
74			`localparam CRCN = 4'd8;`
75			`localparam POLL = 4'd9;`
76
77
78			`// rx state machine`
79			`localparam RX_IDLE = 4'd0;`
80			`localparam RX_0 = 4'd1;`
81			`localparam RX_1 = 4'd2;`
82			`localparam RX_PRE = 4'd3;`
83			`localparam RX_DONE = 4'd4;`
84
85
86			`// md state machine`
87			`localparam MD_REGADDR = 4'd0;`
88			`localparam MD_PHYADDR = 4'd1;`
89			`localparam MD_WRITE0 = 4'd2;`
90			`localparam MD_READ0 = 4'd3;`
91			`localparam MD_START1 = 4'd4;`
92			`localparam MD_START0 = 4'd5;`
93			`localparam MD_IDLE = 4'd6;`
94			`localparam MD_TURN0 = 4'd7;`
95			`localparam MD_TURN1 = 4'd8;`
96			`localparam MD_RDATA = 4'd9;`
97			`localparam MD_WDATA = 4'd10;`
98			`localparam MD_WXFR = 4'd11;`
99
100			`localparam MDREAD = 1'd0;`
101			`localparam MDWRITE = 1'd1;`
102
103
104			`// MD register addresses`
105			`localparam MII_BMCR = 5'd0; /* Basic mode control register */`
106			`localparam MII_BMSR = 5'd1; /* Basic mode status register */`
107			`localparam MII_CTRL1000 = 5'd9; /* 1000BASE-T control */`
108
109
110			`reg [7:0] mem [2**16-1:0];`
111			`reg [7:0] eth [13:0];`
112
113			`reg [7:0] rxm [2047:0];`
114
115			`reg [15:0] line_r = 16'd0;`
116			`reg [15:0] rx_line_r;`
117
118			`reg [3:0] state_r = IDLE;`
119			`reg [3:0] md_state_r = MD_IDLE;`
120			`reg [3:0] rx_state_r = RX_IDLE;`
121			`reg [15:0] pkt_len_r;`
122			`reg [31:0] wcount_r;`
123			`reg [15:0] pkt_pos_r;`
124			`reg [3:0] pcount_r;`
125
126			`reg md_op_r = MDREAD;`
127			`reg [4:0] md_count_r;`
128			`reg [4:0] md_phy_addr_r;`
129			`reg [4:0] md_reg_addr_r;`
130			`reg [15:0] md_rdata_r;`
131			`reg [15:0] md_wdata_r;`
132			`reg [15:0] md_bmcr_r = 'd0;`
133			`reg [15:0] md_ctrl1000_r = 16'hffff;`
134			`wire init;`
135			`wire [31:0] crc;`
136			`wire [3:0] crc_dinx;`
137			`reg [3:0] crc_din;`
138			`wire enable;`
139			`reg [3:0] mrxd_r;`
140
141			`reg [7:0] last_pkt_num_r = 'd0;`
142
143
144			`integer pkt_to_amber_file;`
145			`integer pkt_to_amber_ack_file;`
146			`integer pkt_from_amber_file;`
147
148			`reg [8*20-1:0] pkt_to_amber = "pkt_to_amber.mem";`
149			`reg [8*20-1:0] pkt_to_amber_ack = "pkt_to_amber_ack.txt";`
150			`reg [8*20-1:0] pkt_from_amber = "pkt_from_amber.mem";`
151
152			`reg [4*8-1:0] line;`
153			`integer fgets_return;`
154			`integer pkt_to_amber_address;`
155			`reg [7:0] pkt_to_amber_data;`
156
157			`integer x;`
158			`reg [7:0] pkt_from_amber_num = 8'd1;`
159
160
161			`// initializwe the ack file to 0`
162			`// this allows sim_socket to write the first packet`
163			`initial`
164			`begin`
165			`pkt_to_amber_ack_file = $fopen(pkt_to_amber_ack, "w");`
166			`$fwrite(pkt_to_amber_ack_file, "0\n");`
167			`$fclose(pkt_to_amber_ack_file);`
168			`end`
169
170
171			`// ============================`
172			`// packet tx state machine`
173			`// ============================`
174			`always@(posedge mtx_clk_i)`
175			`begin`
176			`case (state_r)`
177			`IDLE:`
178			`begin`
179			`mtxd_o <= 'd0;`
180			`mtxdv_o <= 'd0;`
181			`mtxerr_o <= 'd0;`
182			`wcount_r <= 'd0;`
183
184			`if (md_bmcr_r[9]) // autoneg bit set by software`
185			`begin`
186			`wcount_r <= wcount_r + 1'd1;`
187			`if (wcount_r == 32'd10000)`
188			`begin`
189			`state_r <= POLL;`
190			`wcount_r <= 'd0;`
191			`$display("Start polling for packets to send to amber");`
192			`end`
193			`end`
194			`end`
195
196
197
198			`WAIT:`
199			`begin`
200			`wcount_r <= wcount_r + 1'd1;`
201			`if (wcount_r == 32'd100)`
202			`begin`
203			`wcount_r <= 'd0;`
204			`state_r <= POLL;`
205			`end`
206			`end`
207
208
209			`POLL: // scan for new packets`
210			`begin`
211			`mtxd_o <= 'd0;`
212			`mtxdv_o <= 'd0;`
213			`mtxerr_o <= 'd0;`
214
215
216			`pkt_to_amber_file = $fopen(pkt_to_amber, "r");`
217			`fgets_return = $fgets(line, pkt_to_amber_file);`
218			`pkt_to_amber_address = 0;`
219			`while (fgets_return)`
220			`begin`
221			`pkt_to_amber_data = hex_chars_to_8bits (line[23:8]);`
222			`mem[pkt_to_amber_address] = pkt_to_amber_data[7:0];`
223			`pkt_to_amber_address = pkt_to_amber_address + 1;`
224			`fgets_return = $fgets(line, pkt_to_amber_file);`
225			`end`
226			`$fclose(pkt_to_amber_file);`
227
228
229			`if (mem[0] != last_pkt_num_r)`
230			`begin`
231			`state_r <= PREA;`
232			`pkt_len_r <= {mem[1], mem[2]} + 16'd14;`
233			`last_pkt_num_r <= mem[0];`
234			`line_r <= 'd0;`
235			`pkt_pos_r <= 'd0;`
236			`pcount_r <= 'd0;`
237			`wcount_r <= 'd0;`
238
239			`pkt_to_amber_ack_file = $fopen(pkt_to_amber_ack, "w");`
240			`$fwrite(pkt_to_amber_ack_file, "%d\n", mem[0]);`
241			`$fclose(pkt_to_amber_ack_file);`
242			`end`
243			`else begin`
244			`state_r <= WAIT;`
245			`end`
246
247			`end`
248
249
250
251			`PREA: // Preamble`
252			`begin`
253			`mtxd_o <= 4'b0101;`
254			`mtxdv_o <= 1'd1;`
255			`pcount_r <= pcount_r + 1'd1;`
256			`if (pcount_r == 4'd6)`
257			`begin`
258			`pcount_r <= 'd0;`
259			`state_r <= PREB;`
260			`end`
261			`end`
262
263
264			`PREB:`
265			`begin`
266			`mtxd_o <= 4'b1101;`
267			`mtxdv_o <= 1'd1;`
268			`state_r <= TX_0;`
269
270			`print_pkt(1'd1, line_r);`
271			`end`
272
273
274			`TX_0: // low 4 bits`
275			`begin`
276			`mtxd_o <= mem[line_r+3][3:0];`
277			`mtxdv_o <= 1'd1;`
278			`state_r <= TX_1;`
279			`end`
280
281
282			`TX_1: // high 4 bits`
283			`begin`
284			`mtxd_o <= mem[line_r+3][7:4];`
285			`mtxdv_o <= 1'd1;`
286			`line_r <= line_r + 1'd1;`
287
288			`if (pkt_pos_r + 1'd1 == pkt_len_r)`
289			`state_r <= CRC0;`
290			`else`
291			`begin`
292			`state_r <= TX_0;`
293			`pkt_pos_r <= pkt_pos_r + 1'd1;`
294			`end`
295			`end`
296
297
298			`CRC0:`
299			`begin`
300			`mtxd_o <= {~crc[28], ~crc[29], ~crc[30], ~crc[31]};`
301			`mtxdv_o <= 1'd1;`
302			`state_r <= POLL;`
303			`end`
304
305			`endcase`
306			`end`
307
308
309
310			`assign init = state_r == PREB;`
311			`assign enable = state_r != CRC0;`
312
313			`always @*`
314			`begin`
315			`crc_din = state_r == TX_0 ? mem[line_r+3][3:0] :`
316			`state_r == TX_1 ? mem[line_r+3][7:4] :`
317			`32'd0 ;`
318			`end`
319
320
321			`assign crc_dinx = {crc_din[0], crc_din[1], crc_din[2], crc_din[3]};`
322
323
324			`// Gen CRC, using the EthMac CRC generator`
325			`eth_crc eth_crc (`
326			`.Clk ( mtx_clk_i ),`
327			`.Reset ( 1'd0 ),`
328			`.Data ( crc_dinx ),`
329			`.Enable ( enable ),`
330			`.Initialize ( init ),`
331
332			`.Crc ( crc ),`
333			`.CrcError ( )`
334			`);`
335
336
337			`// ============================`
338			`// packet rx state machine`
339			`// ============================`
340			`always@(posedge mtx_clk_i)`
341			`begin`
342			`case (rx_state_r)`
343			`RX_IDLE:`
344			`begin`
345			`rx_line_r <= 'd0;`
346			`if (mrxdv_i) // autoneg bit set by software`
347			`begin`
348			`rx_state_r <= RX_PRE;`
349			`end`
350			`end`
351
352			`RX_PRE:`
353			`begin`
354			`if (mrxd_i == 4'hd)`
355			`rx_state_r <= RX_0;`
356			`end`
357
358			`RX_0: // low 4 bits`
359			`begin`
360			`mrxd_r <= mrxd_i;`
361
362			`if (mrxdv_i)`
363			`rx_state_r <= RX_1;`
364			`else`
365			`rx_state_r <= RX_DONE;`
366			`end`
367
368
369			`RX_1: // high 4 bits`
370			`begin`
371			`rxm[rx_line_r] <= {mrxd_i, mrxd_r};`
372			`rx_line_r <= rx_line_r + 1'd1;`
373
374			`if (mrxdv_i)`
375			`rx_state_r <= RX_0;`
376			`else`
377			`rx_state_r <= RX_DONE;`
378			`end`
379
380
381			`RX_DONE:`
382			`begin`
383			`print_pkt(1'd0, 16'd0);`
384			`rx_state_r <= RX_IDLE;`
385
386
387			`pkt_from_amber_file = $fopen(pkt_from_amber, "w");`
388			`$fwrite(pkt_from_amber_file, "%02h\n", pkt_from_amber_num);`
389
390			`for (x=0;x<rx_line_r;x=x+1)`
391			`$fwrite(pkt_from_amber_file, "%02h\n", rxm[x]);`
392			`$fclose(pkt_from_amber_file);`
393
394
395			`if (pkt_from_amber_num == 8'd255)`
396			`pkt_from_amber_num <= 8'd1;`
397			`else`
398			`pkt_from_amber_num <= pkt_from_amber_num + 1'd1;`
399			`end`
400
401
402			`endcase`
403			`end`
404
405
406
407
408			`// ============================`
409			`// management data state machine`
410			`// ============================`
411			`always@(posedge mdc_i)`
412			`begin`
413			`case (md_state_r)`
414
415			`MD_IDLE:`
416			`begin`
417			`md_count_r <= 'd0;`
418			`if (md_io == 1'd0)`
419			`md_state_r <= MD_START0;`
420			`end`
421
422
423			`MD_START0:`
424			`begin`
425			`if (md_io == 1'd1)`
426			`md_state_r <= MD_START1;`
427			`else`
428			`md_state_r <= MD_IDLE;`
429			`end`
430
431
432			`MD_START1:`
433			`begin`
434			`if (md_io == 1'd1)`
435			`md_state_r <= MD_READ0;`
436			`else`
437			`md_state_r <= MD_WRITE0;`
438			`end`
439
440
441			`MD_READ0:`
442			`begin`
443			`if (md_io == 1'd0)`
444			`begin`
445			`md_state_r <= MD_PHYADDR;`
446			`md_op_r <= MDREAD;`
447			`end`
448			`else`
449			`md_state_r <= MD_IDLE;`
450			`end`
451
452
453			`MD_WRITE0:`
454			`begin`
455			`if (md_io == 1'd1)`
456			`begin`
457			`md_state_r <= MD_PHYADDR;`
458			`md_op_r <= MDWRITE;`
459			`end`
460			`else`
461			`md_state_r <= MD_IDLE;`
462			`end`
463
464			`MD_PHYADDR:`
465			`begin`
466			`md_count_r <= md_count_r + 1'd1;`
467			`md_phy_addr_r <= {md_phy_addr_r[3:0], md_io};`
468
469			`if (md_count_r == 5'd4)`
470			`begin`
471			`md_state_r <= MD_REGADDR;`
472			`md_count_r <= 'd0;`
473			`end`
474			`end`
475
476			`MD_REGADDR:`
477			`begin`
478			`md_count_r <= md_count_r + 1'd1;`
479			`md_reg_addr_r <= {md_reg_addr_r[3:0], md_io};`
480
481			`if (md_count_r == 5'd4)`
482			`begin`
483			`md_count_r <= 'd0;`
484			`md_state_r <= MD_TURN0;`
485			`end`
486			`end`
487
488
489			`MD_TURN0:`
490			`md_state_r <= MD_TURN1;`
491
492			`MD_TURN1:`
493			`begin`
494			`if (md_op_r == MDREAD)`
495			`md_state_r <= MD_RDATA;`
496			`else`
497			`md_state_r <= MD_WDATA;`
498
499			`case (md_reg_addr_r)`
500			`MII_BMCR : md_rdata_r <= md_bmcr_r;`
501			`MII_BMSR : md_rdata_r <= 16'hfe04;`
502			`MII_CTRL1000 : md_rdata_r <= md_ctrl1000_r;`
503			`default : md_rdata_r <= 'd0;`
504			`endcase`
505			`end`
506
507
508			`MD_RDATA:`
509			`begin`
510			`md_count_r <= md_count_r + 1'd1;`
511			`md_rdata_r <= {md_rdata_r[14:0], 1'd0};`
512
513			`if (md_count_r == 5'd15)`
514			`md_state_r <= MD_IDLE;`
515
516			`end`
517
518
519			`MD_WDATA:`
520			`begin`
521			`md_count_r <= md_count_r + 1'd1;`
522			`md_wdata_r <= {md_wdata_r[14:0], md_io};`
523
524			`if (md_count_r == 5'd15)`
525			`begin`
526			`md_state_r <= MD_WXFR;`
527			`md_count_r <= 'd0;`
528			`end`
529			`end`
530
531
532			`MD_WXFR:`
533			`begin`
534			`case (md_reg_addr_r)`
535			`MII_BMCR : md_bmcr_r <= md_wdata_r;`
536			`MII_CTRL1000 : md_ctrl1000_r <= md_wdata_r;`
537			`endcase`
538			`md_state_r <= MD_IDLE;`
539			`end`
540
541
542			`endcase`
543			`end`
544
545
546			`assign md_io = md_state_r == MD_RDATA ? md_rdata_r[15] : 1'bz;`
547
548
549
550			`task print_pkt;`
551			`input tx; /* 1 for tx, 0 for rx */`
552			`input [31:0] start;`
553			`reg [15:0] eth_type;`
554			`reg [7:0] proto;`
555			`reg [31:0] frame;`
556			`reg [3:0] ip_hdr_len;`
557			`reg [15:0] ip_len;`
558			`reg [3:0] tcp_hdr_len;`
559			`reg [15:0] tcp_bdy_len;`
560			`reg [7:0] tmp;`
561			`reg [15:0] arp_op;`
562
563			`integer i;`
564			`begin`
565			`frame = start;`
566
567			`if (tx) $write("%6d pkt to amber ", tb.clk_count);`
568			`else $write("%6d pkt from amber ", tb.clk_count);`
569
570			`$display("mac-dst %h:%h:%h:%h:%h:%h, mac-src %h:%h:%h:%h:%h:%h, type %h%h",`
571			`rmem(tx,frame+0), rmem(tx,frame+1),rmem(tx,frame+2),rmem(tx,frame+3),rmem(tx,frame+4),rmem(tx,frame+5),`
572			`rmem(tx,frame+6), rmem(tx,frame+7),rmem(tx,frame+8),rmem(tx,frame+9),rmem(tx,frame+10),rmem(tx,frame+11),`
573			`rmem(tx,frame+12),rmem(tx,frame+13));`
574
575			`eth_type = {rmem(tx,frame+12),rmem(tx,frame+13)};`
576
577			`if (eth_type == 16'h0806) // arp`
578			`begin`
579			`frame = frame + 14;`
580			`arp_op = rmem(tx,frame+6) << 8 \| rmem(tx,frame+7);`
581
582			`$write("ARP operation %0d", arp_op);`
583
584			`if (arp_op == 16'd1)`
585			`$write(" look for ip %0d.%0d.%0d.%0d",`
586			`rmem(tx,frame+24), rmem(tx,frame+25),rmem(tx,frame+26),rmem(tx,frame+27));`
587			`$write("\n");`
588			`end`
589
590			`if (eth_type == 16'h0800) // ip`
591			`begin`
592			`frame = frame + 14;`
593			`proto = rmem(tx,frame+9);`
594			`tmp = rmem(tx,frame+0);`
595			`ip_hdr_len = tmp[3:0];`
596			`ip_len = {rmem(tx,frame+2), rmem(tx,frame+3)};`
597
598			`$display(" ip-dst %0d.%0d.%0d.%0d, ip-src %0d.%0d.%0d.%0d, proto %0d, ip_len %0d, ihl %0d",`
599			`rmem(tx,frame+16), rmem(tx,frame+17),rmem(tx,frame+18),rmem(tx,frame+19),`
600			`rmem(tx,frame+12), rmem(tx,frame+13),rmem(tx,frame+14),rmem(tx,frame+15),`
601			`proto, ip_len, ip_hdr_len*4);`
602
603			`if (proto == 8'd6) // TCP`
604			`begin`
605			`frame = frame + ip_hdr_len*4;`
606			`tmp = rmem(tx,frame+12);`
607			`tcp_hdr_len = tmp[7:4];`
608			`tcp_bdy_len = ip_len - ({ip_hdr_len,2'd0} + {tcp_hdr_len,2'd0});`
609
610			`$display(" tcp-dst %0d, tcp-src %0d, tcp hdr len %0d, tcp bdy len %0d",`
611			`{rmem(tx,frame+2), rmem(tx,frame+3)},`
612			`{rmem(tx,frame+0), rmem(tx,frame+1)}, tcp_hdr_len*4, tcp_bdy_len);`
613			`$display(" tcp-seq %0d, tcp-ack %0d",`
614			`{rmem(tx,frame+4), rmem(tx,frame+5), rmem(tx,frame+6), rmem(tx,frame+7)},`
615			`{rmem(tx,frame+8), rmem(tx,frame+9), rmem(tx,frame+10), rmem(tx,frame+11)});`
616
617			`if (tcp_bdy_len != 16'd0)`
618			`begin`
619			`for (i=0;i<tcp_bdy_len;i=i+1)`
620			`if ((rmem(tx,frame+tcp_hdr_len4+i) > 31 && rmem(tx,frame+tcp_hdr_len4+i) < 128) \|\|`
621			`(rmem(tx,frame+tcp_hdr_len*4+i) == "\n"))`
622			`$write("%c", rmem(tx,frame+tcp_hdr_len*4+i));`
623			`end`
624
625			`end`
626			`end`
627			`$display("----");`
628			`end`
629			`endtask`
630
631
632			`function [7:0] rmem;`
633			`input tx; /* 1 for tx, 0 for rx */`
634			`input [31:0] addr;`
635			`begin`
636			`if (tx)`
637			`rmem = mem[addr+3];`
638			`else`
639			`rmem = rxm[addr];`
640			`end`
641			`endfunction`
642
643
644			`wire [8*6-1:0] XSTATE =`
645			`state_r == IDLE ? "IDLE" :`
646			`state_r == WAIT ? "WAIT" :`
647			`state_r == TX_0 ? "TX_0" :`
648			`state_r == TX_1 ? "TX_1" :`
649			`state_r == PREA ? "PREA" :`
650			`state_r == PREB ? "PREB" :`
651			`state_r == GAP ? "GAP" :`
652			`state_r == CRC0 ? "CRC0" :`
653			`state_r == CRCN ? "CRCN" :`
654			`state_r == POLL ? "POLL" :`
655			`"UNKNOWN" ;`
656
657			`wire [8*12-1:0] XRXSTATE =`
658			`state_r == RX_IDLE ? "RX_IDLE" :`
659			`state_r == RX_0 ? "RX_0" :`
660			`state_r == RX_1 ? "RX_1" :`
661			`state_r == RX_PRE ? "RX_PRE" :`
662			`state_r == RX_DONE ? "RX_DONE" :`
663			`"UNKNOWN" ;`
664
665			`wire [8*12-1:0] XMDSTATE =`
666			`md_state_r == MD_WXFR ? "MD_WXFR" :`
667			`md_state_r == MD_WDATA ? "MD_WDATA" :`
668			`md_state_r == MD_RDATA ? "MD_RDATA" :`
669			`md_state_r == MD_TURN1 ? "MD_TURN1" :`
670			`md_state_r == MD_TURN0 ? "MD_TURN0" :`
671			`md_state_r == MD_REGADDR ? "MD_REGADDR" :`
672			`md_state_r == MD_PHYADDR ? "MD_PHYADDR" :`
673			`md_state_r == MD_WRITE0 ? "MD_WRITE0" :`
674			`md_state_r == MD_READ0 ? "MD_READ0" :`
675			`md_state_r == MD_START1 ? "MD_START1" :`
676			`md_state_r == MD_START0 ? "MD_START0" :`
677			`md_state_r == MD_IDLE ? "MD_IDLE" :`
678			`"UNKNOWN" ;`
679
680			`endmodule`
681
682