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//////////////////////////////////////////////////////////////////
//                                                              //
//  Top Level testbench                                         //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Instantiates the system, ddr3 memory model and tb_uart      //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
`timescale  1 ps / 1 ps
 
`include "system_config_defines.v"
`include "global_defines.v"
 
 
module tb();
 
`include "debug_functions.v"
`include "system_functions.v"
 
reg                     sysrst;
`ifdef XILINX_VIRTEX6_FPGA
reg                     clk_533mhz;
`endif
reg                     clk_200mhz;
reg                     clk_25mhz;
reg [31:0]              clk_count = 'd0;
 
integer                 log_file;
 
`ifdef AMBER_LOAD_MAIN_MEM
integer                 main_mem_file;
reg     [31:0]          main_mem_file_address;
reg     [31:0]          main_mem_file_data;
reg     [127:0]         main_mem_file_data_128;
integer                 main_mem_line_count;
reg     [22:0]          mm_ddr3_addr;
`endif
 
integer                 boot_mem_file;
reg     [31:0]          boot_mem_file_address;
reg     [31:0]          boot_mem_file_data;
integer                 boot_mem_line_count;
integer                 fgets_return;
reg     [120*8-1:0]     line;
reg     [120*8-1:0]     aligned_line;
reg     [8*16-1:0]      test_name;
integer                 timeout = 0;
 
wire [12:0]             ddr3_addr;
wire [2:0]              ddr3_ba;
wire                    ddr3_ck_p;
wire                    ddr3_ck_n;
wire [15:0]             ddr3_dq;
wire [1:0]              ddr3_dqs_p;
wire [1:0]              ddr3_dqs_n;
wire [1:0]              ddr3_dm;
wire                    ddr3_ras_n;
wire                    ddr3_cas_n;
wire                    ddr3_we_n;
wire                    ddr3_cke;
wire                    ddr3_odt;
wire                    ddr3_reset_n;
 
 
`ifdef XILINX_SPARTAN6_FPGA
wire                    mcb3_rzq;
wire                    mcb3_zio;
`endif
 
tri1                    md_pad_io;
 
wire                    uart0_cts;
wire                    uart0_rx;
wire                    uart0_rts;
wire                    uart0_tx;
 
 
// ======================================
// Instantiate FPGA
// ======================================
system u_system (
    // Clocks and resets
    .brd_rst            ( sysrst            ),
    .brd_clk_p          ( clk_200mhz        ),
    .brd_clk_n          ( ~clk_200mhz       ),
 
    `ifdef XILINX_VIRTEX6_FPGA
    .sys_clk_p          ( clk_533mhz        ),
    .sys_clk_n          ( ~clk_533mhz       ),
    `endif
 
    // UART 0 signals
    .o_uart0_cts        ( uart0_cts         ),
    .o_uart0_rx         ( uart0_rx          ),
    .i_uart0_rts        ( uart0_rts         ),
    .i_uart0_tx         ( uart0_tx          ),
 
    // DDR3 signals
    .ddr3_dq            ( ddr3_dq           ),
    .ddr3_addr          ( ddr3_addr         ),
    .ddr3_ba            ( ddr3_ba           ),
    .ddr3_ras_n         ( ddr3_ras_n        ),
    .ddr3_cas_n         ( ddr3_cas_n        ),
    .ddr3_we_n          ( ddr3_we_n         ),
    .ddr3_odt           ( ddr3_odt          ),
    .ddr3_reset_n       ( ddr3_reset_n      ),
    .ddr3_cke           ( ddr3_cke          ),
    .ddr3_dm            ( ddr3_dm           ),
    .ddr3_dqs_p         ( ddr3_dqs_p        ),
    .ddr3_dqs_n         ( ddr3_dqs_n        ),
    .ddr3_ck_p          ( ddr3_ck_p         ),
    .ddr3_ck_n          ( ddr3_ck_n         ),
    `ifdef XILINX_VIRTEX6_FPGA
    .ddr3_cs_n          ( ddr3_cs_n         ),
    `endif
    `ifdef XILINX_SPARTAN6_FPGA
    .mcb3_rzq           ( mcb3_rzq          ),
    .mcb3_zio           ( mcb3_zio          ),
    `endif
 
    // Ethernet MII signals
    .mtx_clk_pad_i      ( clk_25mhz         ),
    .mtxd_pad_o         (                   ),
    .mtxen_pad_o        (                   ),
    .mtxerr_pad_o       (                   ),
    .mrx_clk_pad_i      ( clk_25mhz         ),
    .mrxd_pad_i         ( 4'd0              ),
    .mrxdv_pad_i        ( 1'd0              ),
    .mrxerr_pad_i       ( 1'd0              ),
    .mcoll_pad_i        ( 1'd0              ),
    .mcrs_pad_i         ( 1'd0              ),  // Assert Carrier Sense from PHY
    .phy_reset_n        (                   ),
 
    // Ethernet MD signals
    .md_pad_io          ( md_pad_io         ),
    .mdc_pad_o          (                   )
 
);
 
 
// ======================================
// Instantiate DDR3 Memory Model
// ======================================
`ifdef XILINX_FPGA
    ddr3_model_c3 #(
          .DEBUG      ( 0                   )   // Set to 1 to enable debug messages
          )
    u_ddr3_model (
          .ck         ( ddr3_ck_p           ),
          .ck_n       ( ddr3_ck_n           ),
          .cke        ( ddr3_cke            ),
          `ifdef XILINX_VIRTEX6_FPGA
          .cs_n       ( ddr3_cs_n           ),
          `else
          .cs_n       ( 1'b0                ),
          `endif
          .ras_n      ( ddr3_ras_n          ),
          .cas_n      ( ddr3_cas_n          ),
          .we_n       ( ddr3_we_n           ),
          .dm_tdqs    ( ddr3_dm             ),
          .ba         ( ddr3_ba             ),
          .addr       ( {1'd0, ddr3_addr}   ),
          .dq         ( ddr3_dq             ),
          .dqs        ( ddr3_dqs_p          ),
          .dqs_n      ( ddr3_dqs_n          ),
          .tdqs_n     (                     ),
          .odt        ( ddr3_odt            ),
          .rst_n      ( ddr3_reset_n        )
          );
`endif
 
 
// ======================================
// Instantiate Testbench UART
// ======================================
tb_uart u_tb_uart (
    .i_uart_cts_n   ( uart0_cts ),          // Clear To Send
    .i_uart_rxd     ( uart0_rx  ),
    .o_uart_rts_n   ( uart0_rts ),          // Request to Send
    .o_uart_txd     ( uart0_tx  )
 
);
 
 
// ======================================
// Global module for xilinx hardware simulations
// ======================================
`ifdef XILINX_FPGA
    `define GLBL
    glbl glbl();
`endif
 
 
// ======================================
// Clock and Reset
// ======================================
 
// 200 MHz clock
initial
    begin
    clk_200mhz = 1'd0;
    // Time unit is pico-seconds
    forever #2500 clk_200mhz = ~clk_200mhz;
    end
 
 
`ifdef XILINX_VIRTEX6_FPGA
// 400 MHz clock
initial
    begin
    clk_533mhz = 1'd0;
    // Time unit is pico-seconds
    forever #938 clk_533mhz = ~clk_533mhz;
    end
`endif
 
 
// 25 MHz clock
initial
    begin
    clk_25mhz = 1'd0;
    forever #20000 clk_25mhz = ~clk_25mhz;
    end
 
initial
    begin
    sysrst = 1'd1;
    #40000
    sysrst = 1'd0;
    end
 
 
// ======================================
// Counter of system clock ticks        
// ======================================
always @ ( posedge `U_SYSTEM.sys_clk )
    clk_count <= clk_count + 1'd1;
 
 
 
// ======================================
// Initialize Boot Memory
// ======================================
`ifndef XILINX_FPGA
    initial
        begin
        $display("Load boot memory from %s", `BOOT_MEM_FILE);
        boot_mem_line_count   = 0;
        boot_mem_file         = $fopen(`BOOT_MEM_FILE,    "r");
        if (boot_mem_file == 0)
            begin
            `TB_ERROR_MESSAGE
            $display("ERROR: Can't open input file %s", `BOOT_MEM_FILE);
            end
 
        if (boot_mem_file != 0)
            begin
            fgets_return = 1;
            while (fgets_return != 0)
                begin
                fgets_return        = $fgets(line, boot_mem_file);
                boot_mem_line_count = boot_mem_line_count + 1;
                aligned_line        = align_line(line);
 
                // if the line does not start with a comment
                if (aligned_line[120*8-1:118*8] != 16'h2f2f)
                    begin
                    // check that line doesnt start with a '@' or a blank
                    if (aligned_line[120*8-1:119*8] != 8'h40 && aligned_line[120*8-1:119*8] != 8'h00)
                        begin
                        $display("Format ERROR in input file %s, line %1d. Line must start with a @, not %08x",
                                 `BOOT_MEM_FILE, boot_mem_line_count, aligned_line[118*8-1:117*8]);
                        `TB_ERROR_MESSAGE
                        end
 
                    if (aligned_line[120*8-1:119*8] != 8'h00)
                        begin
                        boot_mem_file_address  =   hex_chars_to_32bits (aligned_line[119*8-1:111*8]);
                        boot_mem_file_data     =   hex_chars_to_32bits (aligned_line[110*8-1:102*8]);
 
                        tb.u_system.u_boot_mem.u_mem.mem [boot_mem_file_address[12:2]] = boot_mem_file_data;
 
                        `ifdef AMBER_LOAD_MEM_DEBUG
                            $display ("Load Boot Mem: PAddr: 0x%08x, Data 0x%08x",
                                        boot_mem_file_address, boot_mem_file_data);
                        `endif
                        end
                    end
                end
 
            $display("Read in %1d lines", boot_mem_line_count);
            end
 
        // Grab the test name from memory    
        timeout   =              tb.u_system.u_boot_mem.u_mem.mem [11'h7fb];
        test_name = { endian_x32(tb.u_system.u_boot_mem.u_mem.mem [11'h7fc]),
                      endian_x32(tb.u_system.u_boot_mem.u_mem.mem [11'h7fd]),
                      endian_x32(tb.u_system.u_boot_mem.u_mem.mem [11'h7fe]),
                      endian_x32(tb.u_system.u_boot_mem.u_mem.mem [11'h7ff])};
        $display("log file %s, timeout %0d, test name %0s ", `AMBER_LOG_FILE, timeout, test_name);
        log_file = $fopen(`AMBER_LOG_FILE, "a");
        end
 
`endif
 
 
// ======================================
// Initialize Main Memory
// ======================================
`ifdef AMBER_LOAD_MAIN_MEM
    initial
        begin
        $display("Load main memory from %s", `MAIN_MEM_FILE);
        `ifdef XILINX_FPGA
        // Wait for DDR3 initialization to complete
        $display("Wait for DDR3 initialization to complete before loading main memory");
        #70000000
        $display("Done waiting at %d ticks", `U_TB.clk_count);
        `endif
        main_mem_file   = $fopen(`MAIN_MEM_FILE, "r");
 
        // Read RAM File
        main_mem_line_count   = 0;
 
        if (main_mem_file == 0)
            begin
            $display("ERROR: Can't open input file %s", `MAIN_MEM_FILE);
            `TB_ERROR_MESSAGE
            end
 
 
        if (main_mem_file != 0)
            begin
            fgets_return = 1;
            while (fgets_return != 0)
                begin
                fgets_return        = $fgets(line, main_mem_file);
                main_mem_line_count = main_mem_line_count + 1;
                aligned_line        = align_line(line);
 
                // if the line does not start with a comment
                if (aligned_line[120*8-1:118*8] != 16'h2f2f)
                    begin
                    // check that line doesnt start with a '@' or a blank
                    if (aligned_line[120*8-1:119*8] != 8'h40 && aligned_line[120*8-1:119*8] != 8'h00)
                        begin
                        $display("Format ERROR in input file %s, line %1d. Line must start with a @, not %08x",
                                 `MAIN_MEM_FILE, main_mem_line_count, aligned_line[118*8-1:117*8]);
                        `TB_ERROR_MESSAGE
                        end
 
                    if (aligned_line[120*8-1:119*8] != 8'h00)
                        begin
                        main_mem_file_address =   hex_chars_to_32bits (aligned_line[119*8-1:111*8]);
                        main_mem_file_data    =   hex_chars_to_32bits (aligned_line[110*8-1:102*8]);
 
                        `ifdef XILINX_FPGA
                            mm_ddr3_addr = {main_mem_file_address[13:11], main_mem_file_address[26:14], main_mem_file_address[10:4]};
 
                            main_mem_file_data_128 = tb.u_ddr3_model.memory [mm_ddr3_addr];
                            tb.u_ddr3_model.memory [mm_ddr3_addr] =
                                    insert_32_into_128 ( main_mem_file_address[3:2],
                                                         main_mem_file_data_128,
                                                         main_mem_file_data );
 
                            `ifdef AMBER_LOAD_MEM_DEBUG
                                main_mem_file_data_128 = tb.u_ddr3_model.memory [mm_ddr3_addr];
                                $display ("Load DDR3: PAddr: 0x%08x, DDR3 Addr 0x%08h, Data 0x%032x",
                                          main_mem_file_address, mm_ddr3_addr, main_mem_file_data_128);
                            `endif
 
                        `else
                            // Fast simulation model of main memory
 
                            // U_RAM - Can either point to simple or Xilinx DDR3 model. 
                            // Set in hierarchy_defines.v
 
                            main_mem_file_data_128 = `U_RAM [main_mem_file_address[31:4]];
                            `U_RAM [main_mem_file_address[31:4]] =
                                insert_32_into_128 ( main_mem_file_address[3:2],
                                                     main_mem_file_data_128,
                                                     main_mem_file_data );
 
                            `ifdef AMBER_LOAD_MEM_DEBUG
                                $display ("Load RAM: PAddr: 0x%08x, Data 0x%08x",
                                           main_mem_file_address, main_mem_file_data);
                            `endif
 
                        `endif
 
                        end
                    end
                end
 
            $display("Read in %1d lines", main_mem_line_count);
            end
        end
`endif
 
 
dumpvcd u_dumpvcd();
 
// ======================================
// Terminate Test  
// ======================================
`ifdef AMBER_A25_CORE
    `include "a25_localparams.v"
    `include "a25_functions.v"
`else
    `include "a23_localparams.v"
    `include "a23_functions.v"
`endif
 
reg             testfail;
wire            test_status_set;
wire [31:0]     test_status_reg;
 
initial
    begin
    testfail  = 1'd0;
    end
 
assign test_status_set = `U_TEST_MODULE.test_status_set;
assign test_status_reg = `U_TEST_MODULE.test_status_reg;
 
always @*
        begin
        if ( test_status_set || testfail )
            begin
            if ( test_status_reg == 32'd17 && !testfail )
                begin
                display_registers;
                $display("++++++++++++++++++++");
                $write("Passed %s %0d ticks\n", test_name, `U_TB.clk_count);
                $display("++++++++++++++++++++");
                $fwrite(`U_TB.log_file,"Passed %s %0d ticks\n", test_name, `U_TB.clk_count);
                $finish;
                end
            else
                begin
                display_registers;
                if ( testfail )
                    begin
                    $display("++++++++++++++++++++");
                    $write("Failed %s\n", test_name);
                    $display("++++++++++++++++++++");
                    $fwrite(`U_TB.log_file,"Failed %s\n", test_name);
                    $finish;
                    end
                else
                    begin
                    $display("++++++++++++++++++++");
                    if (test_status_reg >= 32'h8000)
                        $write("Failed %s - with error 0x%08x\n", test_name, test_status_reg);
                    else
                        $write("Failed %s - with error on line %1d\n", test_name, test_status_reg);
                    $display("++++++++++++++++++++");
                    if (test_status_reg >= 32'h8000)
                        $fwrite(`U_TB.log_file,"Failed %s - with error 0x%08h\n", test_name, test_status_reg);
                    else
                        $fwrite(`U_TB.log_file,"Failed %s - with error on line %1d\n", test_name, test_status_reg);
                    $finish;
                    end
                end
            end
        end
 
 
// ======================================
// Timeout
// ======================================
always @ ( posedge `U_SYSTEM.sys_clk )
    if ( timeout != 0 )
        if (`U_TB.clk_count >= timeout)
            begin
            `TB_ERROR_MESSAGE
            $display("Timeout Error");
            end
 
// ======================================
// Tasks
// ======================================
task display_registers;
begin
    $display("");
    $display("----------------------------------------------------------------------------");
    $display("Amber Core");
 
    case (`U_EXECUTE.status_bits_mode)
        FIRQ:    $display("         User       > FIRQ         IRQ          SVC");
        IRQ:     $display("         User         FIRQ       > IRQ          SVC");
        SVC:     $display("         User         FIRQ         IRQ        > SVC");
        default: $display("       > User         FIRQ         IRQ          SVC");
    endcase
 
    $display("r0       0x%08x", `U_REGISTER_BANK.r0);
    $display("r1       0x%08x", `U_REGISTER_BANK.r1);
    $display("r2       0x%08x", `U_REGISTER_BANK.r2);
    $display("r3       0x%08x", `U_REGISTER_BANK.r3);
    $display("r4       0x%08x", `U_REGISTER_BANK.r4);
    $display("r5       0x%08x", `U_REGISTER_BANK.r5);
    $display("r6       0x%08x", `U_REGISTER_BANK.r6);
    $display("r7       0x%08x", `U_REGISTER_BANK.r7);
    $display("r8       0x%08x   0x%08x ", `U_REGISTER_BANK.r8,  `U_REGISTER_BANK.r8_firq);
    $display("r9       0x%08x   0x%08x ", `U_REGISTER_BANK.r9,  `U_REGISTER_BANK.r9_firq);
    $display("r10      0x%08x   0x%08x ", `U_REGISTER_BANK.r10, `U_REGISTER_BANK.r10_firq);
    $display("r11      0x%08x   0x%08x ", `U_REGISTER_BANK.r11, `U_REGISTER_BANK.r11_firq);
    $display("r12      0x%08x   0x%08x ", `U_REGISTER_BANK.r12, `U_REGISTER_BANK.r12_firq);
 
    $display("r13      0x%08x   0x%08x   0x%08x   0x%08x",
                                               `U_REGISTER_BANK.r13,
                                               `U_REGISTER_BANK.r13_firq,
                                               `U_REGISTER_BANK.r13_irq,
                                               `U_REGISTER_BANK.r13_svc);
    $display("r14 (lr) 0x%08x   0x%08x   0x%08x   0x%08x",
                                               `U_REGISTER_BANK.r14,
                                               `U_REGISTER_BANK.r14_firq,
                                               `U_REGISTER_BANK.r14_irq,
                                               `U_REGISTER_BANK.r14_svc);
 
 
    $display("r15 (pc) 0x%08x", {6'd0,`U_REGISTER_BANK.r15,2'd0});
    $display("");
    $display("Status Bits: N=%d, Z=%d, C=%d, V=%d, IRQ Mask %d, FIRQ Mask %d, Mode = %s",
       `U_EXECUTE.status_bits_flags[3],
       `U_EXECUTE.status_bits_flags[2],
       `U_EXECUTE.status_bits_flags[1],
       `U_EXECUTE.status_bits_flags[0],
       `U_EXECUTE.status_bits_irq_mask,
       `U_EXECUTE.status_bits_firq_mask,
       mode_name (`U_EXECUTE.status_bits_mode) );
    $display("----------------------------------------------------------------------------");
    $display("");
 
end
endtask
 
 
// ======================================
// Functions
// ======================================
function [127:0] insert_32_into_128;
input [1:0]   pos;
input [127:0] word128;
input [31:0]  word32;
begin
     case (pos)
         2'd0: insert_32_into_128 = {word128[127:32], word32};
         2'd1: insert_32_into_128 = {word128[127:64], word32, word128[31:0]};
         2'd2: insert_32_into_128 = {word128[127:96], word32, word128[63:0]};
         2'd3: insert_32_into_128 = {word32, word128[95:0]};
     endcase
end
endfunction
 
 
endmodule
 

Line No.	Rev	Author	Line
1	2	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Top Level testbench //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Instantiates the system, ddr3 memory model and tb_uart //`
10			`// //`
11			`// Author(s): //`
12			`// - Conor Santifort, csantifort.amber@gmail.com //`
13			`// //`
14			`//////////////////////////////////////////////////////////////////`
15			`// //`
16			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
17			`// //`
18			`// This source file may be used and distributed without //`
19			`// restriction provided that this copyright statement is not //`
20			`// removed from the file and that any derivative work contains //`
21			`// the original copyright notice and the associated disclaimer. //`
22			`// //`
23			`// This source file is free software; you can redistribute it //`
24			`// and/or modify it under the terms of the GNU Lesser General //`
25			`// Public License as published by the Free Software Foundation; //`
26			`// either version 2.1 of the License, or (at your option) any //`
27			`// later version. //`
28			`// //`
29			`// This source is distributed in the hope that it will be //`
30			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
31			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
32			`// PURPOSE. See the GNU Lesser General Public License for more //`
33			`// details. //`
34			`// //`
35			`// You should have received a copy of the GNU Lesser General //`
36			`// Public License along with this source; if not, download it //`
37			`// from http://www.opencores.org/lgpl.shtml //`
38			`// //`
39			`//////////////////////////////////////////////////////////////////`
40
41			`timescale 1 ps / 1 ps
42
43			`include "system_config_defines.v"
44			`include "global_defines.v"
45
46
47			`module tb();`
48
49			`include "debug_functions.v"
50	35	csantifort	`include "system_functions.v"
51	2	csantifort
52			`reg sysrst;`
53			`ifdef XILINX_VIRTEX6_FPGA
54			`reg clk_533mhz;`
55			`endif
56			`reg clk_200mhz;`
57			`reg clk_25mhz;`
58	15	csantifort	`reg [31:0] clk_count = 'd0;`
59	2	csantifort
60			`integer log_file;`
61
62			`ifdef AMBER_LOAD_MAIN_MEM
63			`integer main_mem_file;`
64			`reg [31:0] main_mem_file_address;`
65			`reg [31:0] main_mem_file_data;`
66			`reg [127:0] main_mem_file_data_128;`
67			`integer main_mem_line_count;`
68			`reg [22:0] mm_ddr3_addr;`
69			`endif
70
71			`integer boot_mem_file;`
72			`reg [31:0] boot_mem_file_address;`
73			`reg [31:0] boot_mem_file_data;`
74			`integer boot_mem_line_count;`
75			`integer fgets_return;`
76			`reg [120*8-1:0] line;`
77			`reg [120*8-1:0] aligned_line;`
78	35	csantifort	`reg [8*16-1:0] test_name;`
79			`integer timeout = 0;`
80	2	csantifort
81			`wire [12:0] ddr3_addr;`
82			`wire [2:0] ddr3_ba;`
83			`wire ddr3_ck_p;`
84			`wire ddr3_ck_n;`
85			`wire [15:0] ddr3_dq;`
86			`wire [1:0] ddr3_dqs_p;`
87			`wire [1:0] ddr3_dqs_n;`
88			`wire [1:0] ddr3_dm;`
89			`wire ddr3_ras_n;`
90			`wire ddr3_cas_n;`
91			`wire ddr3_we_n;`
92			`wire ddr3_cke;`
93			`wire ddr3_odt;`
94			`wire ddr3_reset_n;`
95
96
97			`ifdef XILINX_SPARTAN6_FPGA
98			`wire mcb3_rzq;`
99			`wire mcb3_zio;`
100			`endif
101
102			`tri1 md_pad_io;`
103
104			`wire uart0_cts;`
105			`wire uart0_rx;`
106			`wire uart0_rts;`
107			`wire uart0_tx;`
108
109
110			`// ======================================`
111			`// Instantiate FPGA`
112			`// ======================================`
113			`system u_system (`
114			`// Clocks and resets`
115			`.brd_rst ( sysrst ),`
116			`.brd_clk_p ( clk_200mhz ),`
117			`.brd_clk_n ( ~clk_200mhz ),`
118
119			`ifdef XILINX_VIRTEX6_FPGA
120			`.sys_clk_p ( clk_533mhz ),`
121			`.sys_clk_n ( ~clk_533mhz ),`
122			`endif
123
124			`// UART 0 signals`
125			`.o_uart0_cts ( uart0_cts ),`
126			`.o_uart0_rx ( uart0_rx ),`
127			`.i_uart0_rts ( uart0_rts ),`
128			`.i_uart0_tx ( uart0_tx ),`
129
130			`// DDR3 signals`
131			`.ddr3_dq ( ddr3_dq ),`
132			`.ddr3_addr ( ddr3_addr ),`
133			`.ddr3_ba ( ddr3_ba ),`
134			`.ddr3_ras_n ( ddr3_ras_n ),`
135			`.ddr3_cas_n ( ddr3_cas_n ),`
136			`.ddr3_we_n ( ddr3_we_n ),`
137			`.ddr3_odt ( ddr3_odt ),`
138			`.ddr3_reset_n ( ddr3_reset_n ),`
139			`.ddr3_cke ( ddr3_cke ),`
140			`.ddr3_dm ( ddr3_dm ),`
141			`.ddr3_dqs_p ( ddr3_dqs_p ),`
142			`.ddr3_dqs_n ( ddr3_dqs_n ),`
143			`.ddr3_ck_p ( ddr3_ck_p ),`
144			`.ddr3_ck_n ( ddr3_ck_n ),`
145			`ifdef XILINX_VIRTEX6_FPGA
146			`.ddr3_cs_n ( ddr3_cs_n ),`
147			`endif
148			`ifdef XILINX_SPARTAN6_FPGA
149			`.mcb3_rzq ( mcb3_rzq ),`
150			`.mcb3_zio ( mcb3_zio ),`
151			`endif
152
153			`// Ethernet MII signals`
154			`.mtx_clk_pad_i ( clk_25mhz ),`
155			`.mtxd_pad_o ( ),`
156			`.mtxen_pad_o ( ),`
157			`.mtxerr_pad_o ( ),`
158			`.mrx_clk_pad_i ( clk_25mhz ),`
159			`.mrxd_pad_i ( 4'd0 ),`
160			`.mrxdv_pad_i ( 1'd0 ),`
161			`.mrxerr_pad_i ( 1'd0 ),`
162			`.mcoll_pad_i ( 1'd0 ),`
163			`.mcrs_pad_i ( 1'd0 ), // Assert Carrier Sense from PHY`
164			`.phy_reset_n ( ),`
165
166			`// Ethernet MD signals`
167			`.md_pad_io ( md_pad_io ),`
168			`.mdc_pad_o ( )`
169
170			`);`
171
172
173			`// ======================================`
174			`// Instantiate DDR3 Memory Model`
175			`// ======================================`
176			`ifdef XILINX_FPGA
177			`ddr3_model_c3 #(`
178			`.DEBUG ( 0 ) // Set to 1 to enable debug messages`
179			`)`
180			`u_ddr3_model (`
181			`.ck ( ddr3_ck_p ),`
182			`.ck_n ( ddr3_ck_n ),`
183			`.cke ( ddr3_cke ),`
184			`ifdef XILINX_VIRTEX6_FPGA
185			`.cs_n ( ddr3_cs_n ),`
186			`else
187			`.cs_n ( 1'b0 ),`
188			`endif
189			`.ras_n ( ddr3_ras_n ),`
190			`.cas_n ( ddr3_cas_n ),`
191			`.we_n ( ddr3_we_n ),`
192			`.dm_tdqs ( ddr3_dm ),`
193			`.ba ( ddr3_ba ),`
194			`.addr ( {1'd0, ddr3_addr} ),`
195	11	csantifort	`.dq ( ddr3_dq ),`
196			`.dqs ( ddr3_dqs_p ),`
197			`.dqs_n ( ddr3_dqs_n ),`
198	2	csantifort	`.tdqs_n ( ),`
199			`.odt ( ddr3_odt ),`
200			`.rst_n ( ddr3_reset_n )`
201			`);`
202			`endif
203
204
205			`// ======================================`
206			`// Instantiate Testbench UART`
207			`// ======================================`
208			`tb_uart u_tb_uart (`
209			`.i_uart_cts_n ( uart0_cts ), // Clear To Send`
210			`.i_uart_rxd ( uart0_rx ),`
211			`.o_uart_rts_n ( uart0_rts ), // Request to Send`
212			`.o_uart_txd ( uart0_tx )`
213
214			`);`
215
216
217			`// ======================================`
218			`// Global module for xilinx hardware simulations`
219			`// ======================================`
220			`ifdef XILINX_FPGA
221			`define GLBL
222			`glbl glbl();`
223			`endif
224
225
226			`// ======================================`
227			`// Clock and Reset`
228			`// ======================================`
229
230			`// 200 MHz clock`
231			`initial`
232			`begin`
233			`clk_200mhz = 1'd0;`
234			`// Time unit is pico-seconds`
235			`forever #2500 clk_200mhz = ~clk_200mhz;`
236			`end`
237
238
239			`ifdef XILINX_VIRTEX6_FPGA
240			`// 400 MHz clock`
241			`initial`
242			`begin`
243			`clk_533mhz = 1'd0;`
244			`// Time unit is pico-seconds`
245			`forever #938 clk_533mhz = ~clk_533mhz;`
246			`end`
247			`endif
248
249
250			`// 25 MHz clock`
251			`initial`
252			`begin`
253			`clk_25mhz = 1'd0;`
254			`forever #20000 clk_25mhz = ~clk_25mhz;`
255			`end`
256
257			`initial`
258			`begin`
259			`sysrst = 1'd1;`
260	15	csantifort	`#40000`
261	2	csantifort	`sysrst = 1'd0;`
262			`end`
263
264
265			`// ======================================`
266			`// Counter of system clock ticks`
267			`// ======================================`
268			always @ ( posedge `U_SYSTEM.sys_clk )
269	15	csantifort	`clk_count <= clk_count + 1'd1;`
270	2	csantifort
271
272
273			`// ======================================`
274			`// Initialize Boot Memory`
275			`// ======================================`
276			`ifndef XILINX_FPGA
277			`initial`
278			`begin`
279			$display("Load boot memory from %s", `BOOT_MEM_FILE);
280			`boot_mem_line_count = 0;`
281			boot_mem_file = $fopen(`BOOT_MEM_FILE, "r");
282			`if (boot_mem_file == 0)`
283			`begin`
284			`TB_ERROR_MESSAGE
285			$display("ERROR: Can't open input file %s", `BOOT_MEM_FILE);
286			`end`
287
288			`if (boot_mem_file != 0)`
289			`begin`
290			`fgets_return = 1;`
291			`while (fgets_return != 0)`
292			`begin`
293			`fgets_return = $fgets(line, boot_mem_file);`
294			`boot_mem_line_count = boot_mem_line_count + 1;`
295			`aligned_line = align_line(line);`
296
297			`// if the line does not start with a comment`
298			`if (aligned_line[1208-1:1188] != 16'h2f2f)`
299			`begin`
300			`// check that line doesnt start with a '@' or a blank`
301			`if (aligned_line[1208-1:1198] != 8'h40 && aligned_line[1208-1:1198] != 8'h00)`
302			`begin`
303			`$display("Format ERROR in input file %s, line %1d. Line must start with a @, not %08x",`
304			`BOOT_MEM_FILE, boot_mem_line_count, aligned_line[1188-1:1178]);
305			`TB_ERROR_MESSAGE
306			`end`
307
308			`if (aligned_line[1208-1:1198] != 8'h00)`
309			`begin`
310			`boot_mem_file_address = hex_chars_to_32bits (aligned_line[1198-1:1118]);`
311			`boot_mem_file_data = hex_chars_to_32bits (aligned_line[1108-1:1028]);`
312
313			`tb.u_system.u_boot_mem.u_mem.mem [boot_mem_file_address[12:2]] = boot_mem_file_data;`
314
315			`ifdef AMBER_LOAD_MEM_DEBUG
316			`$display ("Load Boot Mem: PAddr: 0x%08x, Data 0x%08x",`
317			`boot_mem_file_address, boot_mem_file_data);`
318			`endif
319			`end`
320			`end`
321			`end`
322
323			`$display("Read in %1d lines", boot_mem_line_count);`
324			`end`
325	35	csantifort
326			`// Grab the test name from memory`
327			`timeout = tb.u_system.u_boot_mem.u_mem.mem [11'h7fb];`
328			`test_name = { endian_x32(tb.u_system.u_boot_mem.u_mem.mem [11'h7fc]),`
329			`endian_x32(tb.u_system.u_boot_mem.u_mem.mem [11'h7fd]),`
330			`endian_x32(tb.u_system.u_boot_mem.u_mem.mem [11'h7fe]),`
331			`endian_x32(tb.u_system.u_boot_mem.u_mem.mem [11'h7ff])};`
332			$display("log file %s, timeout %0d, test name %0s ", `AMBER_LOG_FILE, timeout, test_name);
333			log_file = $fopen(`AMBER_LOG_FILE, "a");
334	2	csantifort	`end`
335
336			`endif
337
338
339			`// ======================================`
340			`// Initialize Main Memory`
341			`// ======================================`
342			`ifdef AMBER_LOAD_MAIN_MEM
343			`initial`
344			`begin`
345			$display("Load main memory from %s", `MAIN_MEM_FILE);
346			`ifdef XILINX_FPGA
347			`// Wait for DDR3 initialization to complete`
348			`$display("Wait for DDR3 initialization to complete before loading main memory");`
349			`#70000000`
350			$display("Done waiting at %d ticks", `U_TB.clk_count);
351			`endif
352			main_mem_file = $fopen(`MAIN_MEM_FILE, "r");
353
354			`// Read RAM File`
355			`main_mem_line_count = 0;`
356
357			`if (main_mem_file == 0)`
358			`begin`
359			$display("ERROR: Can't open input file %s", `MAIN_MEM_FILE);
360			`TB_ERROR_MESSAGE
361			`end`
362
363
364			`if (main_mem_file != 0)`
365			`begin`
366			`fgets_return = 1;`
367			`while (fgets_return != 0)`
368			`begin`
369			`fgets_return = $fgets(line, main_mem_file);`
370			`main_mem_line_count = main_mem_line_count + 1;`
371			`aligned_line = align_line(line);`
372
373			`// if the line does not start with a comment`
374			`if (aligned_line[1208-1:1188] != 16'h2f2f)`
375			`begin`
376			`// check that line doesnt start with a '@' or a blank`
377			`if (aligned_line[1208-1:1198] != 8'h40 && aligned_line[1208-1:1198] != 8'h00)`
378			`begin`
379			`$display("Format ERROR in input file %s, line %1d. Line must start with a @, not %08x",`
380			`MAIN_MEM_FILE, main_mem_line_count, aligned_line[1188-1:1178]);
381			`TB_ERROR_MESSAGE
382			`end`
383
384			`if (aligned_line[1208-1:1198] != 8'h00)`
385			`begin`
386			`main_mem_file_address = hex_chars_to_32bits (aligned_line[1198-1:1118]);`
387			`main_mem_file_data = hex_chars_to_32bits (aligned_line[1108-1:1028]);`
388
389			`ifdef XILINX_FPGA
390			`mm_ddr3_addr = {main_mem_file_address[13:11], main_mem_file_address[26:14], main_mem_file_address[10:4]};`
391
392	11	csantifort	`main_mem_file_data_128 = tb.u_ddr3_model.memory [mm_ddr3_addr];`
393			`tb.u_ddr3_model.memory [mm_ddr3_addr] =`
394	2	csantifort	`insert_32_into_128 ( main_mem_file_address[3:2],`
395			`main_mem_file_data_128,`
396			`main_mem_file_data );`
397
398			`ifdef AMBER_LOAD_MEM_DEBUG
399	11	csantifort	`main_mem_file_data_128 = tb.u_ddr3_model.memory [mm_ddr3_addr];`
400	2	csantifort	`$display ("Load DDR3: PAddr: 0x%08x, DDR3 Addr 0x%08h, Data 0x%032x",`
401			`main_mem_file_address, mm_ddr3_addr, main_mem_file_data_128);`
402			`endif
403
404			`else
405			`// Fast simulation model of main memory`
406
407			`// U_RAM - Can either point to simple or Xilinx DDR3 model.`
408			`// Set in hierarchy_defines.v`
409
410			main_mem_file_data_128 = `U_RAM [main_mem_file_address[31:4]];
411			`U_RAM [main_mem_file_address[31:4]] =
412			`insert_32_into_128 ( main_mem_file_address[3:2],`
413			`main_mem_file_data_128,`
414			`main_mem_file_data );`
415
416			`ifdef AMBER_LOAD_MEM_DEBUG
417			`$display ("Load RAM: PAddr: 0x%08x, Data 0x%08x",`
418			`main_mem_file_address, main_mem_file_data);`
419			`endif
420
421			`endif
422
423			`end`
424			`end`
425			`end`
426
427			`$display("Read in %1d lines", main_mem_line_count);`
428			`end`
429			`end`
430			`endif
431
432
433			`dumpvcd u_dumpvcd();`
434
435			`// ======================================`
436			`// Terminate Test`
437			`// ======================================`
438	15	csantifort	`ifdef AMBER_A25_CORE
439			`include "a25_localparams.v"
440			`include "a25_functions.v"
441			`else
442			`include "a23_localparams.v"
443			`include "a23_functions.v"
444			`endif
445	2	csantifort
446	35	csantifort	`reg testfail;`
447			`wire test_status_set;`
448			`wire [31:0] test_status_reg;`
449	2	csantifort
450			`initial`
451	35	csantifort	`begin`
452			`testfail = 1'd0;`
453			`end`
454	2	csantifort
455			assign test_status_set = `U_TEST_MODULE.test_status_set;
456			assign test_status_reg = `U_TEST_MODULE.test_status_reg;
457
458			`always @*`
459			`begin`
460			`if ( test_status_set \|\| testfail )`
461			`begin`
462			`if ( test_status_reg == 32'd17 && !testfail )`
463			`begin`
464			`display_registers;`
465			`$display("++++++++++++++++++++");`
466	35	csantifort	$write("Passed %s %0d ticks\n", test_name, `U_TB.clk_count);
467	2	csantifort	`$display("++++++++++++++++++++");`
468	35	csantifort	$fwrite(`U_TB.log_file,"Passed %s %0d ticks\n", test_name, `U_TB.clk_count);
469	2	csantifort	`$finish;`
470			`end`
471			`else`
472			`begin`
473			`display_registers;`
474			`if ( testfail )`
475			`begin`
476			`$display("++++++++++++++++++++");`
477	35	csantifort	`$write("Failed %s\n", test_name);`
478	2	csantifort	`$display("++++++++++++++++++++");`
479	35	csantifort	$fwrite(`U_TB.log_file,"Failed %s\n", test_name);
480	2	csantifort	`$finish;`
481			`end`
482			`else`
483			`begin`
484			`$display("++++++++++++++++++++");`
485			`if (test_status_reg >= 32'h8000)`
486	35	csantifort	`$write("Failed %s - with error 0x%08x\n", test_name, test_status_reg);`
487	2	csantifort	`else`
488	35	csantifort	`$write("Failed %s - with error on line %1d\n", test_name, test_status_reg);`
489	2	csantifort	`$display("++++++++++++++++++++");`
490			`if (test_status_reg >= 32'h8000)`
491	35	csantifort	$fwrite(`U_TB.log_file,"Failed %s - with error 0x%08h\n", test_name, test_status_reg);
492	2	csantifort	`else`
493	35	csantifort	$fwrite(`U_TB.log_file,"Failed %s - with error on line %1d\n", test_name, test_status_reg);
494	2	csantifort	`$finish;`
495			`end`
496			`end`
497			`end`
498			`end`
499
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