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[/] [amber/] [trunk/] [hw/] [vlog/] [tb/] [tb.v] - Blame information for rev 36

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1 2 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  Top Level testbench                                         //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  Instantiates the system, ddr3 memory model and tb_uart      //
10
//                                                              //
11
//  Author(s):                                                  //
12
//      - Conor Santifort, csantifort.amber@gmail.com           //
13
//                                                              //
14
//////////////////////////////////////////////////////////////////
15
//                                                              //
16
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
17
//                                                              //
18
// This source file may be used and distributed without         //
19
// restriction provided that this copyright statement is not    //
20
// removed from the file and that any derivative work contains  //
21
// the original copyright notice and the associated disclaimer. //
22
//                                                              //
23
// This source file is free software; you can redistribute it   //
24
// and/or modify it under the terms of the GNU Lesser General   //
25
// Public License as published by the Free Software Foundation; //
26
// either version 2.1 of the License, or (at your option) any   //
27
// later version.                                               //
28
//                                                              //
29
// This source is distributed in the hope that it will be       //
30
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
31
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
32
// PURPOSE.  See the GNU Lesser General Public License for more //
33
// details.                                                     //
34
//                                                              //
35
// You should have received a copy of the GNU Lesser General    //
36
// Public License along with this source; if not, download it   //
37
// from http://www.opencores.org/lgpl.shtml                     //
38
//                                                              //
39
//////////////////////////////////////////////////////////////////
40
 
41
`timescale  1 ps / 1 ps
42
 
43
`include "system_config_defines.v"
44
`include "global_defines.v"
45
 
46
 
47
module tb();
48
 
49
`include "debug_functions.v"
50 35 csantifort
`include "system_functions.v"
51 2 csantifort
 
52
reg                     sysrst;
53
`ifdef XILINX_VIRTEX6_FPGA
54
reg                     clk_533mhz;
55
`endif
56
reg                     clk_200mhz;
57
reg                     clk_25mhz;
58 15 csantifort
reg [31:0]              clk_count = 'd0;
59 2 csantifort
 
60
integer                 log_file;
61
 
62
`ifdef AMBER_LOAD_MAIN_MEM
63
integer                 main_mem_file;
64
reg     [31:0]          main_mem_file_address;
65
reg     [31:0]          main_mem_file_data;
66
reg     [127:0]         main_mem_file_data_128;
67
integer                 main_mem_line_count;
68
reg     [22:0]          mm_ddr3_addr;
69
`endif
70
 
71
integer                 boot_mem_file;
72
reg     [31:0]          boot_mem_file_address;
73
reg     [31:0]          boot_mem_file_data;
74 36 csantifort
reg     [127:0]         boot_mem_file_data_128;
75 2 csantifort
integer                 boot_mem_line_count;
76
integer                 fgets_return;
77
reg     [120*8-1:0]     line;
78
reg     [120*8-1:0]     aligned_line;
79 35 csantifort
integer                 timeout = 0;
80 2 csantifort
 
81
wire [12:0]             ddr3_addr;
82
wire [2:0]              ddr3_ba;
83
wire                    ddr3_ck_p;
84
wire                    ddr3_ck_n;
85
wire [15:0]             ddr3_dq;
86
wire [1:0]              ddr3_dqs_p;
87
wire [1:0]              ddr3_dqs_n;
88
wire [1:0]              ddr3_dm;
89
wire                    ddr3_ras_n;
90
wire                    ddr3_cas_n;
91
wire                    ddr3_we_n;
92
wire                    ddr3_cke;
93
wire                    ddr3_odt;
94
wire                    ddr3_reset_n;
95
 
96
 
97
`ifdef XILINX_SPARTAN6_FPGA
98
wire                    mcb3_rzq;
99
wire                    mcb3_zio;
100
`endif
101
 
102
tri1                    md_pad_io;
103
 
104
wire                    uart0_cts;
105
wire                    uart0_rx;
106
wire                    uart0_rts;
107
wire                    uart0_tx;
108
 
109
 
110
// ======================================
111
// Instantiate FPGA
112
// ======================================
113
system u_system (
114
    // Clocks and resets
115
    .brd_rst            ( sysrst            ),
116
    .brd_clk_p          ( clk_200mhz        ),
117
    .brd_clk_n          ( ~clk_200mhz       ),
118
 
119
    `ifdef XILINX_VIRTEX6_FPGA
120
    .sys_clk_p          ( clk_533mhz        ),
121
    .sys_clk_n          ( ~clk_533mhz       ),
122
    `endif
123
 
124
    // UART 0 signals
125
    .o_uart0_cts        ( uart0_cts         ),
126
    .o_uart0_rx         ( uart0_rx          ),
127
    .i_uart0_rts        ( uart0_rts         ),
128
    .i_uart0_tx         ( uart0_tx          ),
129
 
130
    // DDR3 signals
131
    .ddr3_dq            ( ddr3_dq           ),
132
    .ddr3_addr          ( ddr3_addr         ),
133
    .ddr3_ba            ( ddr3_ba           ),
134
    .ddr3_ras_n         ( ddr3_ras_n        ),
135
    .ddr3_cas_n         ( ddr3_cas_n        ),
136
    .ddr3_we_n          ( ddr3_we_n         ),
137
    .ddr3_odt           ( ddr3_odt          ),
138
    .ddr3_reset_n       ( ddr3_reset_n      ),
139
    .ddr3_cke           ( ddr3_cke          ),
140
    .ddr3_dm            ( ddr3_dm           ),
141
    .ddr3_dqs_p         ( ddr3_dqs_p        ),
142
    .ddr3_dqs_n         ( ddr3_dqs_n        ),
143
    .ddr3_ck_p          ( ddr3_ck_p         ),
144
    .ddr3_ck_n          ( ddr3_ck_n         ),
145
    `ifdef XILINX_VIRTEX6_FPGA
146
    .ddr3_cs_n          ( ddr3_cs_n         ),
147
    `endif
148
    `ifdef XILINX_SPARTAN6_FPGA
149
    .mcb3_rzq           ( mcb3_rzq          ),
150
    .mcb3_zio           ( mcb3_zio          ),
151
    `endif
152
 
153
    // Ethernet MII signals
154
    .mtx_clk_pad_i      ( clk_25mhz         ),
155
    .mtxd_pad_o         (                   ),
156
    .mtxen_pad_o        (                   ),
157
    .mtxerr_pad_o       (                   ),
158
    .mrx_clk_pad_i      ( clk_25mhz         ),
159
    .mrxd_pad_i         ( 4'd0              ),
160
    .mrxdv_pad_i        ( 1'd0              ),
161
    .mrxerr_pad_i       ( 1'd0              ),
162
    .mcoll_pad_i        ( 1'd0              ),
163
    .mcrs_pad_i         ( 1'd0              ),  // Assert Carrier Sense from PHY
164
    .phy_reset_n        (                   ),
165
 
166
    // Ethernet MD signals
167
    .md_pad_io          ( md_pad_io         ),
168
    .mdc_pad_o          (                   )
169
 
170
);
171
 
172
 
173
// ======================================
174
// Instantiate DDR3 Memory Model
175
// ======================================
176
`ifdef XILINX_FPGA
177
    ddr3_model_c3 #(
178
          .DEBUG      ( 0                   )   // Set to 1 to enable debug messages
179
          )
180
    u_ddr3_model (
181
          .ck         ( ddr3_ck_p           ),
182
          .ck_n       ( ddr3_ck_n           ),
183
          .cke        ( ddr3_cke            ),
184
          `ifdef XILINX_VIRTEX6_FPGA
185
          .cs_n       ( ddr3_cs_n           ),
186
          `else
187
          .cs_n       ( 1'b0                ),
188
          `endif
189
          .ras_n      ( ddr3_ras_n          ),
190
          .cas_n      ( ddr3_cas_n          ),
191
          .we_n       ( ddr3_we_n           ),
192
          .dm_tdqs    ( ddr3_dm             ),
193
          .ba         ( ddr3_ba             ),
194
          .addr       ( {1'd0, ddr3_addr}   ),
195 11 csantifort
          .dq         ( ddr3_dq             ),
196
          .dqs        ( ddr3_dqs_p          ),
197
          .dqs_n      ( ddr3_dqs_n          ),
198 2 csantifort
          .tdqs_n     (                     ),
199
          .odt        ( ddr3_odt            ),
200
          .rst_n      ( ddr3_reset_n        )
201
          );
202
`endif
203
 
204
 
205
// ======================================
206
// Instantiate Testbench UART
207
// ======================================
208
tb_uart u_tb_uart (
209
    .i_uart_cts_n   ( uart0_cts ),          // Clear To Send
210
    .i_uart_rxd     ( uart0_rx  ),
211
    .o_uart_rts_n   ( uart0_rts ),          // Request to Send
212
    .o_uart_txd     ( uart0_tx  )
213
 
214
);
215
 
216
 
217
// ======================================
218
// Global module for xilinx hardware simulations
219
// ======================================
220
`ifdef XILINX_FPGA
221
    `define GLBL
222
    glbl glbl();
223
`endif
224
 
225
 
226
// ======================================
227
// Clock and Reset
228
// ======================================
229
 
230
// 200 MHz clock
231
initial
232
    begin
233
    clk_200mhz = 1'd0;
234
    // Time unit is pico-seconds
235
    forever #2500 clk_200mhz = ~clk_200mhz;
236
    end
237
 
238
 
239
`ifdef XILINX_VIRTEX6_FPGA
240
// 400 MHz clock
241
initial
242
    begin
243
    clk_533mhz = 1'd0;
244
    // Time unit is pico-seconds
245
    forever #938 clk_533mhz = ~clk_533mhz;
246
    end
247
`endif
248
 
249
 
250
// 25 MHz clock
251
initial
252
    begin
253
    clk_25mhz = 1'd0;
254
    forever #20000 clk_25mhz = ~clk_25mhz;
255
    end
256
 
257
initial
258
    begin
259
    sysrst = 1'd1;
260 15 csantifort
    #40000
261 2 csantifort
    sysrst = 1'd0;
262
    end
263
 
264
 
265
// ======================================
266
// Counter of system clock ticks        
267
// ======================================
268
always @ ( posedge `U_SYSTEM.sys_clk )
269 15 csantifort
    clk_count <= clk_count + 1'd1;
270 2 csantifort
 
271
 
272
 
273
// ======================================
274
// Initialize Boot Memory
275
// ======================================
276
    initial
277
        begin
278 36 csantifort
`ifndef XILINX_FPGA
279 2 csantifort
        $display("Load boot memory from %s", `BOOT_MEM_FILE);
280
        boot_mem_line_count   = 0;
281
        boot_mem_file         = $fopen(`BOOT_MEM_FILE,    "r");
282
        if (boot_mem_file == 0)
283
            begin
284
            `TB_ERROR_MESSAGE
285
            $display("ERROR: Can't open input file %s", `BOOT_MEM_FILE);
286
            end
287
 
288
        if (boot_mem_file != 0)
289
            begin
290
            fgets_return = 1;
291
            while (fgets_return != 0)
292
                begin
293
                fgets_return        = $fgets(line, boot_mem_file);
294
                boot_mem_line_count = boot_mem_line_count + 1;
295
                aligned_line        = align_line(line);
296
 
297
                // if the line does not start with a comment
298
                if (aligned_line[120*8-1:118*8] != 16'h2f2f)
299
                    begin
300
                    // check that line doesnt start with a '@' or a blank
301
                    if (aligned_line[120*8-1:119*8] != 8'h40 && aligned_line[120*8-1:119*8] != 8'h00)
302
                        begin
303
                        $display("Format ERROR in input file %s, line %1d. Line must start with a @, not %08x",
304
                                 `BOOT_MEM_FILE, boot_mem_line_count, aligned_line[118*8-1:117*8]);
305
                        `TB_ERROR_MESSAGE
306
                        end
307
 
308
                    if (aligned_line[120*8-1:119*8] != 8'h00)
309
                        begin
310
                        boot_mem_file_address  =   hex_chars_to_32bits (aligned_line[119*8-1:111*8]);
311
                        boot_mem_file_data     =   hex_chars_to_32bits (aligned_line[110*8-1:102*8]);
312
 
313 36 csantifort
                        `ifdef AMBER_A25_CORE
314
                            boot_mem_file_data_128 = `U_BOOT_MEM.u_mem.mem[boot_mem_file_address[12:4]];
315
                            `U_BOOT_MEM.u_mem.mem[boot_mem_file_address[12:4]] =
316
                                    insert_32_into_128 ( boot_mem_file_address[3:2],
317
                                                         boot_mem_file_data_128,
318
                                                         boot_mem_file_data );
319
                        `else
320
                            `U_BOOT_MEM.u_mem.mem[boot_mem_file_address[12:2]] = boot_mem_file_data;
321
                        `endif
322
 
323 2 csantifort
                        `ifdef AMBER_LOAD_MEM_DEBUG
324
                            $display ("Load Boot Mem: PAddr: 0x%08x, Data 0x%08x",
325
                                        boot_mem_file_address, boot_mem_file_data);
326
                        `endif
327
                        end
328
                    end
329
                end
330
 
331
            $display("Read in %1d lines", boot_mem_line_count);
332
            end
333 36 csantifort
`endif
334 35 csantifort
 
335
        // Grab the test name from memory    
336 36 csantifort
        timeout   = `AMBER_TIMEOUT   ;
337
        $display("log file %s, timeout %0d, test name %0s ", `AMBER_LOG_FILE, timeout, `AMBER_TEST_NAME );
338 35 csantifort
        log_file = $fopen(`AMBER_LOG_FILE, "a");
339 2 csantifort
        end
340
 
341
 
342
 
343
// ======================================
344
// Initialize Main Memory
345
// ======================================
346
`ifdef AMBER_LOAD_MAIN_MEM
347
    initial
348
        begin
349
        $display("Load main memory from %s", `MAIN_MEM_FILE);
350
        `ifdef XILINX_FPGA
351
        // Wait for DDR3 initialization to complete
352
        $display("Wait for DDR3 initialization to complete before loading main memory");
353
        #70000000
354
        $display("Done waiting at %d ticks", `U_TB.clk_count);
355
        `endif
356
        main_mem_file   = $fopen(`MAIN_MEM_FILE, "r");
357
 
358
        // Read RAM File
359
        main_mem_line_count   = 0;
360
 
361
        if (main_mem_file == 0)
362
            begin
363
            $display("ERROR: Can't open input file %s", `MAIN_MEM_FILE);
364
            `TB_ERROR_MESSAGE
365
            end
366
 
367
 
368
        if (main_mem_file != 0)
369
            begin
370
            fgets_return = 1;
371
            while (fgets_return != 0)
372
                begin
373
                fgets_return        = $fgets(line, main_mem_file);
374
                main_mem_line_count = main_mem_line_count + 1;
375
                aligned_line        = align_line(line);
376
 
377
                // if the line does not start with a comment
378
                if (aligned_line[120*8-1:118*8] != 16'h2f2f)
379
                    begin
380
                    // check that line doesnt start with a '@' or a blank
381
                    if (aligned_line[120*8-1:119*8] != 8'h40 && aligned_line[120*8-1:119*8] != 8'h00)
382
                        begin
383
                        $display("Format ERROR in input file %s, line %1d. Line must start with a @, not %08x",
384
                                 `MAIN_MEM_FILE, main_mem_line_count, aligned_line[118*8-1:117*8]);
385
                        `TB_ERROR_MESSAGE
386
                        end
387
 
388
                    if (aligned_line[120*8-1:119*8] != 8'h00)
389
                        begin
390
                        main_mem_file_address =   hex_chars_to_32bits (aligned_line[119*8-1:111*8]);
391
                        main_mem_file_data    =   hex_chars_to_32bits (aligned_line[110*8-1:102*8]);
392
 
393
                        `ifdef XILINX_FPGA
394
                            mm_ddr3_addr = {main_mem_file_address[13:11], main_mem_file_address[26:14], main_mem_file_address[10:4]};
395
 
396 11 csantifort
                            main_mem_file_data_128 = tb.u_ddr3_model.memory [mm_ddr3_addr];
397
                            tb.u_ddr3_model.memory [mm_ddr3_addr] =
398 2 csantifort
                                    insert_32_into_128 ( main_mem_file_address[3:2],
399
                                                         main_mem_file_data_128,
400
                                                         main_mem_file_data );
401
 
402
                            `ifdef AMBER_LOAD_MEM_DEBUG
403 11 csantifort
                                main_mem_file_data_128 = tb.u_ddr3_model.memory [mm_ddr3_addr];
404 2 csantifort
                                $display ("Load DDR3: PAddr: 0x%08x, DDR3 Addr 0x%08h, Data 0x%032x",
405
                                          main_mem_file_address, mm_ddr3_addr, main_mem_file_data_128);
406
                            `endif
407
 
408
                        `else
409
                            // Fast simulation model of main memory
410
 
411
                            // U_RAM - Can either point to simple or Xilinx DDR3 model. 
412
                            // Set in hierarchy_defines.v
413
 
414
                            main_mem_file_data_128 = `U_RAM [main_mem_file_address[31:4]];
415
                            `U_RAM [main_mem_file_address[31:4]] =
416
                                insert_32_into_128 ( main_mem_file_address[3:2],
417
                                                     main_mem_file_data_128,
418
                                                     main_mem_file_data );
419
 
420
                            `ifdef AMBER_LOAD_MEM_DEBUG
421
                                $display ("Load RAM: PAddr: 0x%08x, Data 0x%08x",
422
                                           main_mem_file_address, main_mem_file_data);
423
                            `endif
424
 
425
                        `endif
426
 
427
                        end
428
                    end
429
                end
430
 
431
            $display("Read in %1d lines", main_mem_line_count);
432
            end
433
        end
434
`endif
435
 
436
 
437
dumpvcd u_dumpvcd();
438
 
439
// ======================================
440
// Terminate Test  
441
// ======================================
442 15 csantifort
`ifdef AMBER_A25_CORE
443
    `include "a25_localparams.v"
444
    `include "a25_functions.v"
445
`else
446
    `include "a23_localparams.v"
447
    `include "a23_functions.v"
448
`endif
449 2 csantifort
 
450 35 csantifort
reg             testfail;
451
wire            test_status_set;
452
wire [31:0]     test_status_reg;
453 2 csantifort
 
454
initial
455 35 csantifort
    begin
456
    testfail  = 1'd0;
457
    end
458 2 csantifort
 
459
assign test_status_set = `U_TEST_MODULE.test_status_set;
460
assign test_status_reg = `U_TEST_MODULE.test_status_reg;
461
 
462
always @*
463
        begin
464
        if ( test_status_set || testfail )
465
            begin
466
            if ( test_status_reg == 32'd17 && !testfail )
467
                begin
468
                display_registers;
469
                $display("++++++++++++++++++++");
470 36 csantifort
                $write("Passed %s %0d ticks\n", `AMBER_TEST_NAME, `U_TB.clk_count);
471 2 csantifort
                $display("++++++++++++++++++++");
472 36 csantifort
                $fwrite(`U_TB.log_file,"Passed %s %0d ticks\n", `AMBER_TEST_NAME, `U_TB.clk_count);
473 2 csantifort
                $finish;
474
                end
475
            else
476
                begin
477
                display_registers;
478
                if ( testfail )
479
                    begin
480
                    $display("++++++++++++++++++++");
481 36 csantifort
                    $write("Failed %s\n", `AMBER_TEST_NAME);
482 2 csantifort
                    $display("++++++++++++++++++++");
483 36 csantifort
                    $fwrite(`U_TB.log_file,"Failed %s\n", `AMBER_TEST_NAME);
484 2 csantifort
                    $finish;
485
                    end
486
                else
487
                    begin
488
                    $display("++++++++++++++++++++");
489
                    if (test_status_reg >= 32'h8000)
490 36 csantifort
                        $write("Failed %s - with error 0x%08x\n", `AMBER_TEST_NAME, test_status_reg);
491 2 csantifort
                    else
492 36 csantifort
                        $write("Failed %s - with error on line %1d\n", `AMBER_TEST_NAME, test_status_reg);
493 2 csantifort
                    $display("++++++++++++++++++++");
494
                    if (test_status_reg >= 32'h8000)
495 36 csantifort
                        $fwrite(`U_TB.log_file,"Failed %s - with error 0x%08h\n", `AMBER_TEST_NAME, test_status_reg);
496 2 csantifort
                    else
497 36 csantifort
                        $fwrite(`U_TB.log_file,"Failed %s - with error on line %1d\n", `AMBER_TEST_NAME, test_status_reg);
498 2 csantifort
                    $finish;
499
                    end
500
                end
501
            end
502
        end
503
 
504
 
505
// ======================================
506 15 csantifort
// Timeout
507
// ======================================
508
always @ ( posedge `U_SYSTEM.sys_clk )
509 35 csantifort
    if ( timeout != 0 )
510
        if (`U_TB.clk_count >= timeout)
511 15 csantifort
            begin
512
            `TB_ERROR_MESSAGE
513
            $display("Timeout Error");
514
            end
515
 
516
// ======================================
517 2 csantifort
// Tasks
518
// ======================================
519
task display_registers;
520
begin
521
    $display("");
522
    $display("----------------------------------------------------------------------------");
523
    $display("Amber Core");
524
 
525
    case (`U_EXECUTE.status_bits_mode)
526
        FIRQ:    $display("         User       > FIRQ         IRQ          SVC");
527
        IRQ:     $display("         User         FIRQ       > IRQ          SVC");
528
        SVC:     $display("         User         FIRQ         IRQ        > SVC");
529
        default: $display("       > User         FIRQ         IRQ          SVC");
530
    endcase
531
 
532
    $display("r0       0x%08x", `U_REGISTER_BANK.r0);
533
    $display("r1       0x%08x", `U_REGISTER_BANK.r1);
534
    $display("r2       0x%08x", `U_REGISTER_BANK.r2);
535
    $display("r3       0x%08x", `U_REGISTER_BANK.r3);
536
    $display("r4       0x%08x", `U_REGISTER_BANK.r4);
537
    $display("r5       0x%08x", `U_REGISTER_BANK.r5);
538
    $display("r6       0x%08x", `U_REGISTER_BANK.r6);
539
    $display("r7       0x%08x", `U_REGISTER_BANK.r7);
540
    $display("r8       0x%08x   0x%08x ", `U_REGISTER_BANK.r8,  `U_REGISTER_BANK.r8_firq);
541
    $display("r9       0x%08x   0x%08x ", `U_REGISTER_BANK.r9,  `U_REGISTER_BANK.r9_firq);
542
    $display("r10      0x%08x   0x%08x ", `U_REGISTER_BANK.r10, `U_REGISTER_BANK.r10_firq);
543
    $display("r11      0x%08x   0x%08x ", `U_REGISTER_BANK.r11, `U_REGISTER_BANK.r11_firq);
544
    $display("r12      0x%08x   0x%08x ", `U_REGISTER_BANK.r12, `U_REGISTER_BANK.r12_firq);
545
 
546
    $display("r13      0x%08x   0x%08x   0x%08x   0x%08x",
547
                                               `U_REGISTER_BANK.r13,
548
                                               `U_REGISTER_BANK.r13_firq,
549
                                               `U_REGISTER_BANK.r13_irq,
550
                                               `U_REGISTER_BANK.r13_svc);
551
    $display("r14 (lr) 0x%08x   0x%08x   0x%08x   0x%08x",
552
                                               `U_REGISTER_BANK.r14,
553
                                               `U_REGISTER_BANK.r14_firq,
554
                                               `U_REGISTER_BANK.r14_irq,
555
                                               `U_REGISTER_BANK.r14_svc);
556
 
557
 
558
    $display("r15 (pc) 0x%08x", {6'd0,`U_REGISTER_BANK.r15,2'd0});
559
    $display("");
560
    $display("Status Bits: N=%d, Z=%d, C=%d, V=%d, IRQ Mask %d, FIRQ Mask %d, Mode = %s",
561
       `U_EXECUTE.status_bits_flags[3],
562
       `U_EXECUTE.status_bits_flags[2],
563
       `U_EXECUTE.status_bits_flags[1],
564
       `U_EXECUTE.status_bits_flags[0],
565
       `U_EXECUTE.status_bits_irq_mask,
566
       `U_EXECUTE.status_bits_firq_mask,
567
       mode_name (`U_EXECUTE.status_bits_mode) );
568
    $display("----------------------------------------------------------------------------");
569
    $display("");
570
 
571
end
572
endtask
573
 
574
 
575
// ======================================
576
// Functions
577
// ======================================
578
function [127:0] insert_32_into_128;
579
input [1:0]   pos;
580
input [127:0] word128;
581
input [31:0]  word32;
582
begin
583
     case (pos)
584
         2'd0: insert_32_into_128 = {word128[127:32], word32};
585
         2'd1: insert_32_into_128 = {word128[127:64], word32, word128[31:0]};
586
         2'd2: insert_32_into_128 = {word128[127:96], word32, word128[63:0]};
587
         2'd3: insert_32_into_128 = {word32, word128[95:0]};
588
     endcase
589
end
590
endfunction
591
 
592
 
593 15 csantifort
endmodule
594 2 csantifort
 

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