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csantifort |
//////////////////////////////////////////////////////////////////
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// //
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// Top Level testbench //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// Instantiates the system, ddr3 memory model and tb_uart //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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`timescale 1 ps / 1 ps
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`include "system_config_defines.v"
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`include "global_defines.v"
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module tb();
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`include "debug_functions.v"
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35 |
csantifort |
`include "system_functions.v"
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2 |
csantifort |
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reg sysrst;
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`ifdef XILINX_VIRTEX6_FPGA
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reg clk_533mhz;
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`endif
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reg clk_200mhz;
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reg clk_25mhz;
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15 |
csantifort |
reg [31:0] clk_count = 'd0;
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2 |
csantifort |
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integer log_file;
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`ifdef AMBER_LOAD_MAIN_MEM
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integer main_mem_file;
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reg [31:0] main_mem_file_address;
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reg [31:0] main_mem_file_data;
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reg [127:0] main_mem_file_data_128;
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integer main_mem_line_count;
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reg [22:0] mm_ddr3_addr;
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`endif
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integer boot_mem_file;
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reg [31:0] boot_mem_file_address;
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reg [31:0] boot_mem_file_data;
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csantifort |
reg [127:0] boot_mem_file_data_128;
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csantifort |
integer boot_mem_line_count;
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integer fgets_return;
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reg [120*8-1:0] line;
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reg [120*8-1:0] aligned_line;
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csantifort |
integer timeout = 0;
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2 |
csantifort |
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wire [12:0] ddr3_addr;
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wire [2:0] ddr3_ba;
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wire ddr3_ck_p;
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wire ddr3_ck_n;
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wire [15:0] ddr3_dq;
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wire [1:0] ddr3_dqs_p;
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wire [1:0] ddr3_dqs_n;
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wire [1:0] ddr3_dm;
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wire ddr3_ras_n;
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wire ddr3_cas_n;
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wire ddr3_we_n;
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wire ddr3_cke;
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wire ddr3_odt;
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wire ddr3_reset_n;
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`ifdef XILINX_SPARTAN6_FPGA
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wire mcb3_rzq;
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wire mcb3_zio;
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`endif
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tri1 md_pad_io;
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wire uart0_cts;
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wire uart0_rx;
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wire uart0_rts;
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wire uart0_tx;
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// ======================================
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// Instantiate FPGA
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// ======================================
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system u_system (
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// Clocks and resets
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.brd_rst ( sysrst ),
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.brd_clk_p ( clk_200mhz ),
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.brd_clk_n ( ~clk_200mhz ),
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`ifdef XILINX_VIRTEX6_FPGA
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.sys_clk_p ( clk_533mhz ),
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.sys_clk_n ( ~clk_533mhz ),
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`endif
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// UART 0 signals
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.o_uart0_cts ( uart0_cts ),
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.o_uart0_rx ( uart0_rx ),
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.i_uart0_rts ( uart0_rts ),
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.i_uart0_tx ( uart0_tx ),
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// DDR3 signals
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.ddr3_dq ( ddr3_dq ),
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.ddr3_addr ( ddr3_addr ),
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.ddr3_ba ( ddr3_ba ),
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.ddr3_ras_n ( ddr3_ras_n ),
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.ddr3_cas_n ( ddr3_cas_n ),
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.ddr3_we_n ( ddr3_we_n ),
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.ddr3_odt ( ddr3_odt ),
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.ddr3_reset_n ( ddr3_reset_n ),
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.ddr3_cke ( ddr3_cke ),
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.ddr3_dm ( ddr3_dm ),
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.ddr3_dqs_p ( ddr3_dqs_p ),
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.ddr3_dqs_n ( ddr3_dqs_n ),
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.ddr3_ck_p ( ddr3_ck_p ),
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.ddr3_ck_n ( ddr3_ck_n ),
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`ifdef XILINX_VIRTEX6_FPGA
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.ddr3_cs_n ( ddr3_cs_n ),
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`endif
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`ifdef XILINX_SPARTAN6_FPGA
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.mcb3_rzq ( mcb3_rzq ),
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.mcb3_zio ( mcb3_zio ),
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`endif
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// Ethernet MII signals
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.mtx_clk_pad_i ( clk_25mhz ),
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.mtxd_pad_o ( ),
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.mtxen_pad_o ( ),
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.mtxerr_pad_o ( ),
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.mrx_clk_pad_i ( clk_25mhz ),
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.mrxd_pad_i ( 4'd0 ),
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.mrxdv_pad_i ( 1'd0 ),
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.mrxerr_pad_i ( 1'd0 ),
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.mcoll_pad_i ( 1'd0 ),
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.mcrs_pad_i ( 1'd0 ), // Assert Carrier Sense from PHY
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.phy_reset_n ( ),
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// Ethernet MD signals
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.md_pad_io ( md_pad_io ),
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.mdc_pad_o ( )
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);
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// ======================================
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// Instantiate DDR3 Memory Model
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// ======================================
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`ifdef XILINX_FPGA
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ddr3_model_c3 #(
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.DEBUG ( 0 ) // Set to 1 to enable debug messages
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)
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u_ddr3_model (
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.ck ( ddr3_ck_p ),
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.ck_n ( ddr3_ck_n ),
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.cke ( ddr3_cke ),
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`ifdef XILINX_VIRTEX6_FPGA
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.cs_n ( ddr3_cs_n ),
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`else
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.cs_n ( 1'b0 ),
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`endif
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.ras_n ( ddr3_ras_n ),
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.cas_n ( ddr3_cas_n ),
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.we_n ( ddr3_we_n ),
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.dm_tdqs ( ddr3_dm ),
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.ba ( ddr3_ba ),
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.addr ( {1'd0, ddr3_addr} ),
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11 |
csantifort |
.dq ( ddr3_dq ),
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.dqs ( ddr3_dqs_p ),
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.dqs_n ( ddr3_dqs_n ),
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2 |
csantifort |
.tdqs_n ( ),
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.odt ( ddr3_odt ),
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.rst_n ( ddr3_reset_n )
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);
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`endif
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// ======================================
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// Instantiate Testbench UART
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// ======================================
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tb_uart u_tb_uart (
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.i_uart_cts_n ( uart0_cts ), // Clear To Send
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.i_uart_rxd ( uart0_rx ),
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.o_uart_rts_n ( uart0_rts ), // Request to Send
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.o_uart_txd ( uart0_tx )
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);
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// ======================================
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// Global module for xilinx hardware simulations
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// ======================================
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`ifdef XILINX_FPGA
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`define GLBL
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glbl glbl();
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`endif
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// ======================================
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// Clock and Reset
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// ======================================
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// 200 MHz clock
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initial
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begin
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clk_200mhz = 1'd0;
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// Time unit is pico-seconds
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forever #2500 clk_200mhz = ~clk_200mhz;
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end
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`ifdef XILINX_VIRTEX6_FPGA
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// 400 MHz clock
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initial
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begin
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clk_533mhz = 1'd0;
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// Time unit is pico-seconds
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forever #938 clk_533mhz = ~clk_533mhz;
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end
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`endif
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// 25 MHz clock
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initial
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begin
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clk_25mhz = 1'd0;
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forever #20000 clk_25mhz = ~clk_25mhz;
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end
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initial
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begin
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sysrst = 1'd1;
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15 |
csantifort |
#40000
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2 |
csantifort |
sysrst = 1'd0;
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end
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// ======================================
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// Counter of system clock ticks
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// ======================================
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always @ ( posedge `U_SYSTEM.sys_clk )
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15 |
csantifort |
clk_count <= clk_count + 1'd1;
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2 |
csantifort |
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// ======================================
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// Initialize Boot Memory
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// ======================================
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initial
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begin
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36 |
csantifort |
`ifndef XILINX_FPGA
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2 |
csantifort |
$display("Load boot memory from %s", `BOOT_MEM_FILE);
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boot_mem_line_count = 0;
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boot_mem_file = $fopen(`BOOT_MEM_FILE, "r");
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if (boot_mem_file == 0)
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begin
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`TB_ERROR_MESSAGE
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$display("ERROR: Can't open input file %s", `BOOT_MEM_FILE);
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end
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if (boot_mem_file != 0)
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begin
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fgets_return = 1;
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while (fgets_return != 0)
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begin
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fgets_return = $fgets(line, boot_mem_file);
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boot_mem_line_count = boot_mem_line_count + 1;
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aligned_line = align_line(line);
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// if the line does not start with a comment
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if (aligned_line[120*8-1:118*8] != 16'h2f2f)
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begin
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// check that line doesnt start with a '@' or a blank
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if (aligned_line[120*8-1:119*8] != 8'h40 && aligned_line[120*8-1:119*8] != 8'h00)
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begin
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$display("Format ERROR in input file %s, line %1d. Line must start with a @, not %08x",
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`BOOT_MEM_FILE, boot_mem_line_count, aligned_line[118*8-1:117*8]);
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`TB_ERROR_MESSAGE
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end
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if (aligned_line[120*8-1:119*8] != 8'h00)
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begin
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boot_mem_file_address = hex_chars_to_32bits (aligned_line[119*8-1:111*8]);
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boot_mem_file_data = hex_chars_to_32bits (aligned_line[110*8-1:102*8]);
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36 |
csantifort |
`ifdef AMBER_A25_CORE
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boot_mem_file_data_128 = `U_BOOT_MEM.u_mem.mem[boot_mem_file_address[12:4]];
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`U_BOOT_MEM.u_mem.mem[boot_mem_file_address[12:4]] =
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insert_32_into_128 ( boot_mem_file_address[3:2],
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boot_mem_file_data_128,
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boot_mem_file_data );
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`else
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`U_BOOT_MEM.u_mem.mem[boot_mem_file_address[12:2]] = boot_mem_file_data;
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`endif
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2 |
csantifort |
`ifdef AMBER_LOAD_MEM_DEBUG
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$display ("Load Boot Mem: PAddr: 0x%08x, Data 0x%08x",
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boot_mem_file_address, boot_mem_file_data);
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`endif
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end
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end
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end
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| 330 |
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$display("Read in %1d lines", boot_mem_line_count);
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end
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| 333 |
36 |
csantifort |
`endif
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| 334 |
35 |
csantifort |
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| 335 |
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// Grab the test name from memory
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| 336 |
36 |
csantifort |
timeout = `AMBER_TIMEOUT ;
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| 337 |
|
|
$display("log file %s, timeout %0d, test name %0s ", `AMBER_LOG_FILE, timeout, `AMBER_TEST_NAME );
|
| 338 |
35 |
csantifort |
log_file = $fopen(`AMBER_LOG_FILE, "a");
|
| 339 |
2 |
csantifort |
end
|
| 340 |
|
|
|
| 341 |
|
|
|
| 342 |
|
|
|
| 343 |
|
|
// ======================================
|
| 344 |
|
|
// Initialize Main Memory
|
| 345 |
|
|
// ======================================
|
| 346 |
|
|
`ifdef AMBER_LOAD_MAIN_MEM
|
| 347 |
|
|
initial
|
| 348 |
|
|
begin
|
| 349 |
|
|
$display("Load main memory from %s", `MAIN_MEM_FILE);
|
| 350 |
|
|
`ifdef XILINX_FPGA
|
| 351 |
|
|
// Wait for DDR3 initialization to complete
|
| 352 |
|
|
$display("Wait for DDR3 initialization to complete before loading main memory");
|
| 353 |
|
|
#70000000
|
| 354 |
|
|
$display("Done waiting at %d ticks", `U_TB.clk_count);
|
| 355 |
|
|
`endif
|
| 356 |
|
|
main_mem_file = $fopen(`MAIN_MEM_FILE, "r");
|
| 357 |
|
|
|
| 358 |
|
|
// Read RAM File
|
| 359 |
|
|
main_mem_line_count = 0;
|
| 360 |
|
|
|
| 361 |
|
|
if (main_mem_file == 0)
|
| 362 |
|
|
begin
|
| 363 |
|
|
$display("ERROR: Can't open input file %s", `MAIN_MEM_FILE);
|
| 364 |
|
|
`TB_ERROR_MESSAGE
|
| 365 |
|
|
end
|
| 366 |
|
|
|
| 367 |
|
|
|
| 368 |
|
|
if (main_mem_file != 0)
|
| 369 |
|
|
begin
|
| 370 |
|
|
fgets_return = 1;
|
| 371 |
|
|
while (fgets_return != 0)
|
| 372 |
|
|
begin
|
| 373 |
|
|
fgets_return = $fgets(line, main_mem_file);
|
| 374 |
|
|
main_mem_line_count = main_mem_line_count + 1;
|
| 375 |
|
|
aligned_line = align_line(line);
|
| 376 |
|
|
|
| 377 |
|
|
// if the line does not start with a comment
|
| 378 |
|
|
if (aligned_line[120*8-1:118*8] != 16'h2f2f)
|
| 379 |
|
|
begin
|
| 380 |
|
|
// check that line doesnt start with a '@' or a blank
|
| 381 |
|
|
if (aligned_line[120*8-1:119*8] != 8'h40 && aligned_line[120*8-1:119*8] != 8'h00)
|
| 382 |
|
|
begin
|
| 383 |
|
|
$display("Format ERROR in input file %s, line %1d. Line must start with a @, not %08x",
|
| 384 |
|
|
`MAIN_MEM_FILE, main_mem_line_count, aligned_line[118*8-1:117*8]);
|
| 385 |
|
|
`TB_ERROR_MESSAGE
|
| 386 |
|
|
end
|
| 387 |
|
|
|
| 388 |
|
|
if (aligned_line[120*8-1:119*8] != 8'h00)
|
| 389 |
|
|
begin
|
| 390 |
|
|
main_mem_file_address = hex_chars_to_32bits (aligned_line[119*8-1:111*8]);
|
| 391 |
|
|
main_mem_file_data = hex_chars_to_32bits (aligned_line[110*8-1:102*8]);
|
| 392 |
|
|
|
| 393 |
|
|
`ifdef XILINX_FPGA
|
| 394 |
|
|
mm_ddr3_addr = {main_mem_file_address[13:11], main_mem_file_address[26:14], main_mem_file_address[10:4]};
|
| 395 |
|
|
|
| 396 |
11 |
csantifort |
main_mem_file_data_128 = tb.u_ddr3_model.memory [mm_ddr3_addr];
|
| 397 |
|
|
tb.u_ddr3_model.memory [mm_ddr3_addr] =
|
| 398 |
2 |
csantifort |
insert_32_into_128 ( main_mem_file_address[3:2],
|
| 399 |
|
|
main_mem_file_data_128,
|
| 400 |
|
|
main_mem_file_data );
|
| 401 |
|
|
|
| 402 |
|
|
`ifdef AMBER_LOAD_MEM_DEBUG
|
| 403 |
11 |
csantifort |
main_mem_file_data_128 = tb.u_ddr3_model.memory [mm_ddr3_addr];
|
| 404 |
2 |
csantifort |
$display ("Load DDR3: PAddr: 0x%08x, DDR3 Addr 0x%08h, Data 0x%032x",
|
| 405 |
|
|
main_mem_file_address, mm_ddr3_addr, main_mem_file_data_128);
|
| 406 |
|
|
`endif
|
| 407 |
|
|
|
| 408 |
|
|
`else
|
| 409 |
|
|
// Fast simulation model of main memory
|
| 410 |
|
|
|
| 411 |
|
|
// U_RAM - Can either point to simple or Xilinx DDR3 model.
|
| 412 |
|
|
// Set in hierarchy_defines.v
|
| 413 |
|
|
|
| 414 |
|
|
main_mem_file_data_128 = `U_RAM [main_mem_file_address[31:4]];
|
| 415 |
|
|
`U_RAM [main_mem_file_address[31:4]] =
|
| 416 |
|
|
insert_32_into_128 ( main_mem_file_address[3:2],
|
| 417 |
|
|
main_mem_file_data_128,
|
| 418 |
|
|
main_mem_file_data );
|
| 419 |
|
|
|
| 420 |
|
|
`ifdef AMBER_LOAD_MEM_DEBUG
|
| 421 |
|
|
$display ("Load RAM: PAddr: 0x%08x, Data 0x%08x",
|
| 422 |
|
|
main_mem_file_address, main_mem_file_data);
|
| 423 |
|
|
`endif
|
| 424 |
|
|
|
| 425 |
|
|
`endif
|
| 426 |
|
|
|
| 427 |
|
|
end
|
| 428 |
|
|
end
|
| 429 |
|
|
end
|
| 430 |
|
|
|
| 431 |
|
|
$display("Read in %1d lines", main_mem_line_count);
|
| 432 |
|
|
end
|
| 433 |
|
|
end
|
| 434 |
|
|
`endif
|
| 435 |
|
|
|
| 436 |
|
|
|
| 437 |
|
|
dumpvcd u_dumpvcd();
|
| 438 |
|
|
|
| 439 |
|
|
// ======================================
|
| 440 |
|
|
// Terminate Test
|
| 441 |
|
|
// ======================================
|
| 442 |
15 |
csantifort |
`ifdef AMBER_A25_CORE
|
| 443 |
|
|
`include "a25_localparams.v"
|
| 444 |
|
|
`include "a25_functions.v"
|
| 445 |
|
|
`else
|
| 446 |
|
|
`include "a23_localparams.v"
|
| 447 |
|
|
`include "a23_functions.v"
|
| 448 |
|
|
`endif
|
| 449 |
2 |
csantifort |
|
| 450 |
35 |
csantifort |
reg testfail;
|
| 451 |
|
|
wire test_status_set;
|
| 452 |
|
|
wire [31:0] test_status_reg;
|
| 453 |
2 |
csantifort |
|
| 454 |
|
|
initial
|
| 455 |
35 |
csantifort |
begin
|
| 456 |
|
|
testfail = 1'd0;
|
| 457 |
|
|
end
|
| 458 |
2 |
csantifort |
|
| 459 |
|
|
assign test_status_set = `U_TEST_MODULE.test_status_set;
|
| 460 |
|
|
assign test_status_reg = `U_TEST_MODULE.test_status_reg;
|
| 461 |
|
|
|
| 462 |
|
|
always @*
|
| 463 |
|
|
begin
|
| 464 |
|
|
if ( test_status_set || testfail )
|
| 465 |
|
|
begin
|
| 466 |
|
|
if ( test_status_reg == 32'd17 && !testfail )
|
| 467 |
|
|
begin
|
| 468 |
|
|
display_registers;
|
| 469 |
|
|
$display("++++++++++++++++++++");
|
| 470 |
36 |
csantifort |
$write("Passed %s %0d ticks\n", `AMBER_TEST_NAME, `U_TB.clk_count);
|
| 471 |
2 |
csantifort |
$display("++++++++++++++++++++");
|
| 472 |
36 |
csantifort |
$fwrite(`U_TB.log_file,"Passed %s %0d ticks\n", `AMBER_TEST_NAME, `U_TB.clk_count);
|
| 473 |
2 |
csantifort |
$finish;
|
| 474 |
|
|
end
|
| 475 |
|
|
else
|
| 476 |
|
|
begin
|
| 477 |
|
|
display_registers;
|
| 478 |
|
|
if ( testfail )
|
| 479 |
|
|
begin
|
| 480 |
|
|
$display("++++++++++++++++++++");
|
| 481 |
36 |
csantifort |
$write("Failed %s\n", `AMBER_TEST_NAME);
|
| 482 |
2 |
csantifort |
$display("++++++++++++++++++++");
|
| 483 |
36 |
csantifort |
$fwrite(`U_TB.log_file,"Failed %s\n", `AMBER_TEST_NAME);
|
| 484 |
2 |
csantifort |
$finish;
|
| 485 |
|
|
end
|
| 486 |
|
|
else
|
| 487 |
|
|
begin
|
| 488 |
|
|
$display("++++++++++++++++++++");
|
| 489 |
|
|
if (test_status_reg >= 32'h8000)
|
| 490 |
36 |
csantifort |
$write("Failed %s - with error 0x%08x\n", `AMBER_TEST_NAME, test_status_reg);
|
| 491 |
2 |
csantifort |
else
|
| 492 |
36 |
csantifort |
$write("Failed %s - with error on line %1d\n", `AMBER_TEST_NAME, test_status_reg);
|
| 493 |
2 |
csantifort |
$display("++++++++++++++++++++");
|
| 494 |
|
|
if (test_status_reg >= 32'h8000)
|
| 495 |
36 |
csantifort |
$fwrite(`U_TB.log_file,"Failed %s - with error 0x%08h\n", `AMBER_TEST_NAME, test_status_reg);
|
| 496 |
2 |
csantifort |
else
|
| 497 |
36 |
csantifort |
$fwrite(`U_TB.log_file,"Failed %s - with error on line %1d\n", `AMBER_TEST_NAME, test_status_reg);
|
| 498 |
2 |
csantifort |
$finish;
|
| 499 |
|
|
end
|
| 500 |
|
|
end
|
| 501 |
|
|
end
|
| 502 |
|
|
end
|
| 503 |
|
|
|
| 504 |
|
|
|
| 505 |
|
|
// ======================================
|
| 506 |
15 |
csantifort |
// Timeout
|
| 507 |
|
|
// ======================================
|
| 508 |
|
|
always @ ( posedge `U_SYSTEM.sys_clk )
|
| 509 |
35 |
csantifort |
if ( timeout != 0 )
|
| 510 |
|
|
if (`U_TB.clk_count >= timeout)
|
| 511 |
15 |
csantifort |
begin
|
| 512 |
|
|
`TB_ERROR_MESSAGE
|
| 513 |
49 |
csantifort |
$display("Timeout Error. Edit $AMBER_BASE/hw/tests/timeouts.txt to change the timeout");
|
| 514 |
15 |
csantifort |
end
|
| 515 |
|
|
|
| 516 |
|
|
// ======================================
|
| 517 |
2 |
csantifort |
// Tasks
|
| 518 |
|
|
// ======================================
|
| 519 |
|
|
task display_registers;
|
| 520 |
|
|
begin
|
| 521 |
|
|
$display("");
|
| 522 |
|
|
$display("----------------------------------------------------------------------------");
|
| 523 |
|
|
$display("Amber Core");
|
| 524 |
|
|
|
| 525 |
|
|
case (`U_EXECUTE.status_bits_mode)
|
| 526 |
|
|
FIRQ: $display(" User > FIRQ IRQ SVC");
|
| 527 |
|
|
IRQ: $display(" User FIRQ > IRQ SVC");
|
| 528 |
|
|
SVC: $display(" User FIRQ IRQ > SVC");
|
| 529 |
|
|
default: $display(" > User FIRQ IRQ SVC");
|
| 530 |
|
|
endcase
|
| 531 |
|
|
|
| 532 |
|
|
$display("r0 0x%08x", `U_REGISTER_BANK.r0);
|
| 533 |
|
|
$display("r1 0x%08x", `U_REGISTER_BANK.r1);
|
| 534 |
|
|
$display("r2 0x%08x", `U_REGISTER_BANK.r2);
|
| 535 |
|
|
$display("r3 0x%08x", `U_REGISTER_BANK.r3);
|
| 536 |
|
|
$display("r4 0x%08x", `U_REGISTER_BANK.r4);
|
| 537 |
|
|
$display("r5 0x%08x", `U_REGISTER_BANK.r5);
|
| 538 |
|
|
$display("r6 0x%08x", `U_REGISTER_BANK.r6);
|
| 539 |
|
|
$display("r7 0x%08x", `U_REGISTER_BANK.r7);
|
| 540 |
|
|
$display("r8 0x%08x 0x%08x ", `U_REGISTER_BANK.r8, `U_REGISTER_BANK.r8_firq);
|
| 541 |
|
|
$display("r9 0x%08x 0x%08x ", `U_REGISTER_BANK.r9, `U_REGISTER_BANK.r9_firq);
|
| 542 |
|
|
$display("r10 0x%08x 0x%08x ", `U_REGISTER_BANK.r10, `U_REGISTER_BANK.r10_firq);
|
| 543 |
|
|
$display("r11 0x%08x 0x%08x ", `U_REGISTER_BANK.r11, `U_REGISTER_BANK.r11_firq);
|
| 544 |
|
|
$display("r12 0x%08x 0x%08x ", `U_REGISTER_BANK.r12, `U_REGISTER_BANK.r12_firq);
|
| 545 |
|
|
|
| 546 |
|
|
$display("r13 0x%08x 0x%08x 0x%08x 0x%08x",
|
| 547 |
|
|
`U_REGISTER_BANK.r13,
|
| 548 |
|
|
`U_REGISTER_BANK.r13_firq,
|
| 549 |
|
|
`U_REGISTER_BANK.r13_irq,
|
| 550 |
|
|
`U_REGISTER_BANK.r13_svc);
|
| 551 |
|
|
$display("r14 (lr) 0x%08x 0x%08x 0x%08x 0x%08x",
|
| 552 |
|
|
`U_REGISTER_BANK.r14,
|
| 553 |
|
|
`U_REGISTER_BANK.r14_firq,
|
| 554 |
|
|
`U_REGISTER_BANK.r14_irq,
|
| 555 |
|
|
`U_REGISTER_BANK.r14_svc);
|
| 556 |
|
|
|
| 557 |
|
|
|
| 558 |
|
|
$display("r15 (pc) 0x%08x", {6'd0,`U_REGISTER_BANK.r15,2'd0});
|
| 559 |
|
|
$display("");
|
| 560 |
|
|
$display("Status Bits: N=%d, Z=%d, C=%d, V=%d, IRQ Mask %d, FIRQ Mask %d, Mode = %s",
|
| 561 |
|
|
`U_EXECUTE.status_bits_flags[3],
|
| 562 |
|
|
`U_EXECUTE.status_bits_flags[2],
|
| 563 |
|
|
`U_EXECUTE.status_bits_flags[1],
|
| 564 |
|
|
`U_EXECUTE.status_bits_flags[0],
|
| 565 |
|
|
`U_EXECUTE.status_bits_irq_mask,
|
| 566 |
|
|
`U_EXECUTE.status_bits_firq_mask,
|
| 567 |
|
|
mode_name (`U_EXECUTE.status_bits_mode) );
|
| 568 |
|
|
$display("----------------------------------------------------------------------------");
|
| 569 |
|
|
$display("");
|
| 570 |
|
|
|
| 571 |
|
|
end
|
| 572 |
|
|
endtask
|
| 573 |
|
|
|
| 574 |
|
|
|
| 575 |
|
|
// ======================================
|
| 576 |
|
|
// Functions
|
| 577 |
|
|
// ======================================
|
| 578 |
|
|
function [127:0] insert_32_into_128;
|
| 579 |
|
|
input [1:0] pos;
|
| 580 |
|
|
input [127:0] word128;
|
| 581 |
|
|
input [31:0] word32;
|
| 582 |
|
|
begin
|
| 583 |
|
|
case (pos)
|
| 584 |
|
|
2'd0: insert_32_into_128 = {word128[127:32], word32};
|
| 585 |
|
|
2'd1: insert_32_into_128 = {word128[127:64], word32, word128[31:0]};
|
| 586 |
|
|
2'd2: insert_32_into_128 = {word128[127:96], word32, word128[63:0]};
|
| 587 |
|
|
2'd3: insert_32_into_128 = {word32, word128[95:0]};
|
| 588 |
|
|
endcase
|
| 589 |
|
|
end
|
| 590 |
|
|
endfunction
|
| 591 |
|
|
|
| 592 |
|
|
|
| 593 |
15 |
csantifort |
endmodule
|
| 594 |
2 |
csantifort |
|
