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[/] [amber/] [trunk/] [hw/] [vlog/] [xs6_ddr3/] [datasheet.txt] - Blame information for rev 41
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| Line No. |
Rev |
Author |
Line |
| 1 |
41 |
csantifort |
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| 2 |
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| 3 |
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CORE Generator Options:
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| 4 |
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Target Device : xc6slx45t-fgg484
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| 5 |
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Speed Grade : -3
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| 6 |
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HDL : verilog
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| 7 |
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Synthesis Tool : XST
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| 8 |
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| 9 |
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MIG Output Options:
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| 10 |
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Component Name : ddr3
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| 11 |
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No of Controllers : 1
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| 12 |
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Hardware Test Bench : disabled
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| 13 |
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| 14 |
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| 15 |
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/*******************************************************/
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| 16 |
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/* Controller 3 */
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| 17 |
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/*******************************************************/
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| 18 |
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Controller Options :
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| 19 |
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Memory : DDR3_SDRAM
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| 20 |
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Design Clock Frequency : 2500 ps (400.00 MHz)
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| 21 |
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Memory Type : Components
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| 22 |
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Memory Part : MT41J64M16XX-187E
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| 23 |
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Equivalent Part(s) : MT41J64M16LA-187E
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| 24 |
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Row Address : 13
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| 25 |
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Column Address : 10
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| 26 |
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Bank Address : 3
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| 27 |
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Data Mask : enabled
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| 28 |
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| 29 |
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Memory Options :
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| 30 |
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Burst Length : 8(00)
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| 31 |
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CAS Latency : 6
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| 32 |
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TDQS enable : Disabled
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| 33 |
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DLL Enable : Enable
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| 34 |
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Write Leveling Enable : Disabled
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| 35 |
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Output Drive Strength : RZQ/6
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| 36 |
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Additive Latency (AL) : 0
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| 37 |
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RTT (nominal) - ODT : RZQ/4
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| 38 |
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Auto Self Refresh : Enabled
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| 39 |
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CAS write latency : 5
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| 40 |
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Partial-Array Self Refresh : Full Array
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| 41 |
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RTT_WR : Dynamic ODT off
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| 42 |
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High Temparature Self Refresh Rate : Normal
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| 43 |
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| 44 |
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User Interface Parameters :
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| 45 |
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Configuration Type : One 128-bit bi-directional port
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| 46 |
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Ports Selected : Port0
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| 47 |
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Memory Address Mapping : ROW_BANK_COLUMN
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| 48 |
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| 49 |
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Arbitration Algorithm : Round Robin
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| 50 |
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| 51 |
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Arbitration :
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| 52 |
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Time Slot0 : 0
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| 53 |
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Time Slot1 : 0
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| 54 |
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Time Slot2 : 0
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| 55 |
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Time Slot3 : 0
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| 56 |
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Time Slot4 : 0
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| 57 |
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Time Slot5 : 0
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| 58 |
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Time Slot6 : 0
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| 59 |
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Time Slot7 : 0
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| 60 |
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Time Slot8 : 0
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| 61 |
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Time Slot9 : 0
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| 62 |
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Time Slot10: 0
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| 63 |
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Time Slot11: 0
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| 64 |
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| 65 |
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FPGA Options :
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| 66 |
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Class for Address and Control : II
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| 67 |
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Class for Data : II
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| 68 |
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Memory Interface Pin Termination : UNCALIB_TERM
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| 69 |
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DQ/DQS : 50 Ohms
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| 70 |
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Calibration Row Address : 0000
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| 71 |
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Calibration Column Address : 000
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| 72 |
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Calibration Bank Address : 0
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| 73 |
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Bypass Calibration : enabled
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| 74 |
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Debug Signals for Memory Controller : Enable
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| 75 |
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Input Clock Type : Differential
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| 76 |
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