OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [xs6_ddr3/] [datasheet.txt] - Blame information for rev 54

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 41 csantifort 
 
2 
 
3 
CORE Generator Options:
4 
   Target Device              : xc6slx45t-fgg484
5 
   Speed Grade                : -3
6 
   HDL                        : verilog
7 
   Synthesis Tool             : XST
8 
 
9 
MIG Output Options:
10 
   Component Name             : ddr3
11 
   No of Controllers          : 1
12 
   Hardware Test Bench           : disabled
13 
 
14 
 
15 
/*******************************************************/
16 
/*                  Controller 3                       */
17 
/*******************************************************/
18 
Controller Options :
19 
   Memory                  : DDR3_SDRAM
20 
   Design Clock Frequency  : 2500 ps (400.00 MHz)
21 
   Memory Type             : Components
22 
   Memory Part             : MT41J64M16XX-187E
23 
   Equivalent Part(s)      : MT41J64M16LA-187E
24 
   Row Address             : 13
25 
   Column Address          : 10
26 
   Bank Address            : 3
27 
   Data Mask               : enabled
28 
 
29 
Memory Options :
30 
   Burst Length                       : 8(00)
31 
   CAS Latency                        : 6
32 
   TDQS enable                        : Disabled
33 
   DLL Enable                         : Enable
34 
   Write Leveling Enable              : Disabled
35 
   Output Drive Strength              : RZQ/6
36 
   Additive Latency (AL)              : 0
37 
   RTT (nominal) - ODT                : RZQ/4
38 
   Auto Self Refresh                  : Enabled
39 
   CAS write latency                  : 5
40 
   Partial-Array Self Refresh         : Full Array
41 
   RTT_WR                             : Dynamic ODT off
42 
   High Temparature Self Refresh Rate : Normal
43 
 
44 
User Interface Parameters :
45 
   Configuration Type     : One 128-bit bi-directional port
46 
   Ports Selected         : Port0
47 
   Memory Address Mapping : ROW_BANK_COLUMN
48 
 
49 
   Arbitration Algorithm  : Round Robin
50 
 
51 
   Arbitration            :
52 
      Time Slot0 : 0
53 
      Time Slot1 : 0
54 
      Time Slot2 : 0
55 
      Time Slot3 : 0
56 
      Time Slot4 : 0
57 
      Time Slot5 : 0
58 
      Time Slot6 : 0
59 
      Time Slot7 : 0
60 
      Time Slot8 : 0
61 
      Time Slot9 : 0
62 
      Time Slot10: 0
63 
      Time Slot11: 0
64 
 
65 
FPGA Options :
66 
   Class for Address and Control       : II
67 
   Class for Data                      : II
68 
   Memory Interface Pin Termination    : UNCALIB_TERM
69 
   DQ/DQS                              : 50 Ohms
70 
   Calibration Row Address             : 0000
71 
   Calibration Column Address          : 000
72 
   Calibration Bank Address            : 0
73 
   Bypass Calibration                  : enabled
74 
   Debug Signals for Memory Controller : Enable
75 
   Input Clock Type                    : Differential
76 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.