| 1 |
2 |
csantifort |
/*----------------------------------------------------------------
|
| 2 |
|
|
// //
|
| 3 |
|
|
// amber_registers.h //
|
| 4 |
|
|
// //
|
| 5 |
|
|
// This file is part of the Amber project //
|
| 6 |
|
|
// http://www.opencores.org/project,amber //
|
| 7 |
|
|
// //
|
| 8 |
|
|
// Description //
|
| 9 |
|
|
// Defines the address of all registers in the Amber system. //
|
| 10 |
|
|
// Must be kept synchronized with the equivalent Verilog //
|
| 11 |
|
|
// file, $AMBER_BASE/hw/vlog/system/register_addresses.v //
|
| 12 |
|
|
// which is considered the master. //
|
| 13 |
|
|
// //
|
| 14 |
|
|
// Author(s): //
|
| 15 |
|
|
// - Conor Santifort, csantifort.amber@gmail.com //
|
| 16 |
|
|
// //
|
| 17 |
|
|
//////////////////////////////////////////////////////////////////
|
| 18 |
|
|
// //
|
| 19 |
|
|
// Copyright (C) 2010 Authors and OPENCORES.ORG //
|
| 20 |
|
|
// //
|
| 21 |
|
|
// This source file may be used and distributed without //
|
| 22 |
|
|
// restriction provided that this copyright statement is not //
|
| 23 |
|
|
// removed from the file and that any derivative work contains //
|
| 24 |
|
|
// the original copyright notice and the associated disclaimer. //
|
| 25 |
|
|
// //
|
| 26 |
|
|
// This source file is free software; you can redistribute it //
|
| 27 |
|
|
// and/or modify it under the terms of the GNU Lesser General //
|
| 28 |
|
|
// Public License as published by the Free Software Foundation; //
|
| 29 |
|
|
// either version 2.1 of the License, or (at your option) any //
|
| 30 |
|
|
// later version. //
|
| 31 |
|
|
// //
|
| 32 |
|
|
// This source is distributed in the hope that it will be //
|
| 33 |
|
|
// useful, but WITHOUT ANY WARRANTY; without even the implied //
|
| 34 |
|
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
|
| 35 |
|
|
// PURPOSE. See the GNU Lesser General Public License for more //
|
| 36 |
|
|
// details. //
|
| 37 |
|
|
// //
|
| 38 |
|
|
// You should have received a copy of the GNU Lesser General //
|
| 39 |
|
|
// Public License along with this source; if not, download it //
|
| 40 |
|
|
// from http://www.opencores.org/lgpl.shtml //
|
| 41 |
|
|
// //
|
| 42 |
|
|
----------------------------------------------------------------*/
|
| 43 |
|
|
|
| 44 |
|
|
#define ADR_AMBER_TEST_STATUS 0xf0000000
|
| 45 |
|
|
#define ADR_AMBER_TEST_FIRQ_TIMER 0xf0000004
|
| 46 |
|
|
#define ADR_AMBER_TEST_IRQ_TIMER 0xf0000008
|
| 47 |
|
|
#define ADR_AMBER_TEST_UART_CONTROL 0xf0000010
|
| 48 |
|
|
#define ADR_AMBER_TEST_UART_STATUS 0xf0000014
|
| 49 |
|
|
#define ADR_AMBER_TEST_UART_TXD 0xf0000018
|
| 50 |
|
|
#define ADR_AMBER_TEST_SIM_CTRL 0xf000001c
|
| 51 |
11 |
csantifort |
#define ADR_AMBER_TEST_MEM_CTRL 0xf0000020
|
| 52 |
2 |
csantifort |
/* Allow access to the random register over
|
| 53 |
|
|
a 16-word address range to load a series
|
| 54 |
|
|
of random numbers using lmd instruction. */
|
| 55 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM 0xf0000100
|
| 56 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM00 0xf0000100
|
| 57 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM01 0xf0000104
|
| 58 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM02 0xf0000108
|
| 59 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM03 0xf000010c
|
| 60 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM04 0xf0000110
|
| 61 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM05 0xf0000114
|
| 62 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM06 0xf0000118
|
| 63 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM07 0xf000011c
|
| 64 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM08 0xf0000120
|
| 65 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM09 0xf0000124
|
| 66 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM10 0xf0000128
|
| 67 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM11 0xf000012c
|
| 68 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM12 0xf0000130
|
| 69 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM13 0xf0000134
|
| 70 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM14 0xf0000138
|
| 71 |
|
|
#define ADR_AMBER_TEST_RANDOM_NUM15 0xf000013c
|
| 72 |
|
|
|
| 73 |
|
|
#define ADR_AMBER_IC_IRQ0_ENABLESET 0x14000008
|
| 74 |
|
|
#define ADR_AMBER_IC_IRQ1_ENABLESET 0x14000048
|
| 75 |
|
|
#define ADR_AMBER_IC_INT_SOFTSET_0 0x14000010
|
| 76 |
|
|
#define ADR_AMBER_IC_INT_SOFTCLEAR_0 0x14000014
|
| 77 |
|
|
#define ADR_AMBER_IC_INT_SOFTSET_1 0x14000050
|
| 78 |
|
|
#define ADR_AMBER_IC_INT_SOFTCLEAR_1 0x14000054
|
| 79 |
|
|
|
| 80 |
|
|
#define ADR_AMBER_CT_TIMER0_LOAD 0x13000000
|
| 81 |
|
|
#define ADR_AMBER_CT_TIMER1_LOAD 0x13000100
|
| 82 |
|
|
#define ADR_AMBER_CT_TIMER2_LOAD 0x13000200
|
| 83 |
|
|
|
| 84 |
|
|
#define ADR_AMBER_UART0_DR 0x16000000
|
| 85 |
|
|
#define ADR_AMBER_UART0_RSR 0x16000004
|
| 86 |
|
|
#define ADR_AMBER_UART0_LCRH 0x16000008
|
| 87 |
|
|
#define ADR_AMBER_UART0_LCRM 0x1600000c
|
| 88 |
|
|
#define ADR_AMBER_UART0_LCRL 0x16000010
|
| 89 |
|
|
#define ADR_AMBER_UART0_CR 0x16000014
|
| 90 |
|
|
#define ADR_AMBER_UART0_FR 0x16000018
|
| 91 |
|
|
#define ADR_AMBER_UART0_IIR 0x1600001c
|
| 92 |
|
|
#define ADR_AMBER_UART0_ICR 0x1600001c
|
| 93 |
|
|
|
| 94 |
|
|
#define ADR_AMBER_UART1_DR 0x17000000
|
| 95 |
|
|
#define ADR_AMBER_UART1_RSR 0x17000004
|
| 96 |
|
|
#define ADR_AMBER_UART1_LCRH 0x17000008
|
| 97 |
|
|
#define ADR_AMBER_UART1_LCRM 0x1700000c
|
| 98 |
|
|
#define ADR_AMBER_UART1_LCRL 0x17000010
|
| 99 |
|
|
#define ADR_AMBER_UART1_CR 0x17000014
|
| 100 |
|
|
#define ADR_AMBER_UART1_FR 0x17000018
|
| 101 |
|
|
#define ADR_AMBER_UART1_IIR 0x1700001c
|
| 102 |
|
|
#define ADR_AMBER_UART1_ICR 0x1700001c
|
| 103 |
|
|
|
| 104 |
|
|
#define ADR_AMBER_CORE_CTRL 0x1300031c
|
| 105 |
|
|
|
| 106 |
|
|
#define ADR_ETHMAC_MODER 0x20000000
|
| 107 |
|
|
#define ADR_ETHMAC_MIIMODER 0x20000028
|
| 108 |
|
|
#define ADR_ETHMAC_MIICOMMAND 0x2000002C
|
| 109 |
|
|
#define ADR_ETHMAC_MIIADDRESS 0x20000030
|
| 110 |
|
|
#define ADR_ETHMAC_MIITXDATA 0x20000034
|
| 111 |
|
|
#define ADR_ETHMAC_MIIRXDATA 0x20000038
|
| 112 |
|
|
#define ADR_ETHMAC_MIISTATUS 0x2000003C
|
| 113 |
|
|
#define ADR_ETHMAC_BDBASE 0x20000400
|
| 114 |
15 |
csantifort |
|
| 115 |
|
|
#define ADR_HIBOOT_BASE 0x28000000
|
