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[/] [amber/] [trunk/] [sw/] [include/] [amber_registers.h] - Blame information for rev 88

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/*----------------------------------------------------------------
//                                                              //
//  amber_registers.h                                           //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Defines the address of all registers in the Amber system.   //
//  Must be kept synchronized with the equivalent Verilog       //
//  file, $AMBER_BASE/hw/vlog/system/register_addresses.v       //
//  which is considered the master.                             //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
----------------------------------------------------------------*/
 
#define ADR_AMBER_TEST_STATUS          0xf0000000
#define ADR_AMBER_TEST_FIRQ_TIMER      0xf0000004
#define ADR_AMBER_TEST_IRQ_TIMER       0xf0000008
#define ADR_AMBER_TEST_UART_CONTROL    0xf0000010
#define ADR_AMBER_TEST_UART_STATUS     0xf0000014
#define ADR_AMBER_TEST_UART_TXD        0xf0000018
#define ADR_AMBER_TEST_SIM_CTRL        0xf000001c
#define ADR_AMBER_TEST_MEM_CTRL        0xf0000020
#define ADR_AMBER_TEST_CYCLES          0xf0000024
#define ADR_AMBER_TEST_LED             0xf0000028
#define ADR_AMBER_TEST_PHY_RST         0xf000002c
 
 
/* Allow access to the random register over
   a 16-word address range to load a series
   of random numbers using lmd instruction. */
#define ADR_AMBER_TEST_RANDOM_NUM      0xf0000100
#define ADR_AMBER_TEST_RANDOM_NUM00    0xf0000100
#define ADR_AMBER_TEST_RANDOM_NUM01    0xf0000104
#define ADR_AMBER_TEST_RANDOM_NUM02    0xf0000108
#define ADR_AMBER_TEST_RANDOM_NUM03    0xf000010c
#define ADR_AMBER_TEST_RANDOM_NUM04    0xf0000110
#define ADR_AMBER_TEST_RANDOM_NUM05    0xf0000114
#define ADR_AMBER_TEST_RANDOM_NUM06    0xf0000118
#define ADR_AMBER_TEST_RANDOM_NUM07    0xf000011c
#define ADR_AMBER_TEST_RANDOM_NUM08    0xf0000120
#define ADR_AMBER_TEST_RANDOM_NUM09    0xf0000124
#define ADR_AMBER_TEST_RANDOM_NUM10    0xf0000128
#define ADR_AMBER_TEST_RANDOM_NUM11    0xf000012c
#define ADR_AMBER_TEST_RANDOM_NUM12    0xf0000130
#define ADR_AMBER_TEST_RANDOM_NUM13    0xf0000134
#define ADR_AMBER_TEST_RANDOM_NUM14    0xf0000138
#define ADR_AMBER_TEST_RANDOM_NUM15    0xf000013c
 
#define ADR_AMBER_IC_IRQ0_STATUS       0x14000000
#define ADR_AMBER_IC_IRQ0_RAWSTAT      0x14000004
#define ADR_AMBER_IC_IRQ0_ENABLESET    0x14000008
#define ADR_AMBER_IC_IRQ0_ENABLECLR    0x1400000c
#define ADR_AMBER_IC_INT_SOFTSET_0     0x14000010
#define ADR_AMBER_IC_INT_SOFTCLEAR_0   0x14000014
#define ADR_AMBER_IC_FIRQ0_STATUS      0x14000020
#define ADR_AMBER_IC_FIRQ0_RAWSTAT     0x14000024
#define ADR_AMBER_IC_FIRQ0_ENABLESET   0x14000028
#define ADR_AMBER_IC_FIRQ0_ENABLECLR   0x1400002c
#define ADR_AMBER_IC_IRQ1_STATUS       0x14000040
#define ADR_AMBER_IC_IRQ1_RAWSTAT      0x14000044
#define ADR_AMBER_IC_IRQ1_ENABLESET    0x14000048
#define ADR_AMBER_IC_IRQ1_ENABLECLR    0x1400004c
#define ADR_AMBER_IC_INT_SOFTSET_1     0x14000050
#define ADR_AMBER_IC_INT_SOFTCLEAR_1   0x14000054
#define ADR_AMBER_IC_FIRQ1_STATUS      0x14000060
#define ADR_AMBER_IC_FIRQ1_RAWSTAT     0x14000064
#define ADR_AMBER_IC_FIRQ1_ENABLESET   0x14000068
#define ADR_AMBER_IC_FIRQ1_ENABLECLR   0x1400006c
#define ADR_AMBER_IC_INT_SOFTSET_2     0x14000090
#define ADR_AMBER_IC_INT_SOFTCLEAR_2   0x14000094
#define ADR_AMBER_IC_INT_SOFTSET_3     0x140000d0
#define ADR_AMBER_IC_INT_SOFTCLEAR_3   0x140000d4
 
 
#define ADR_AMBER_CT_TIMER0_LOAD       0x13000000
#define ADR_AMBER_TM_TIMER0_LOAD       0x13000000
#define ADR_AMBER_TM_TIMER0_VALUE      0x13000004
#define ADR_AMBER_TM_TIMER0_CTRL       0x13000008
#define ADR_AMBER_TM_TIMER0_CLR        0x1300000c
#define ADR_AMBER_CT_TIMER1_LOAD       0x13000100
#define ADR_AMBER_TM_TIMER1_LOAD       0x13000100
#define ADR_AMBER_TM_TIMER1_VALUE      0x13000104
#define ADR_AMBER_TM_TIMER1_CTRL       0x13000108
#define ADR_AMBER_TM_TIMER1_CLR        0x1300010c
#define ADR_AMBER_CT_TIMER2_LOAD       0x13000200
#define ADR_AMBER_TM_TIMER2_LOAD       0x13000200
#define ADR_AMBER_TM_TIMER2_VALUE      0x13000204
#define ADR_AMBER_TM_TIMER2_CTRL       0x13000208
#define ADR_AMBER_TM_TIMER2_CLR        0x1300020c
 
#define ADR_AMBER_UART0_DR             0x16000000
#define ADR_AMBER_UART0_RSR            0x16000004
#define ADR_AMBER_UART0_LCRH           0x16000008
#define ADR_AMBER_UART0_LCRM           0x1600000c
#define ADR_AMBER_UART0_LCRL           0x16000010
#define ADR_AMBER_UART0_CR             0x16000014
#define ADR_AMBER_UART0_FR             0x16000018
#define ADR_AMBER_UART0_IIR            0x1600001c
#define ADR_AMBER_UART0_ICR            0x1600001c
 
#define ADR_AMBER_UART1_DR             0x17000000
#define ADR_AMBER_UART1_RSR            0x17000004
#define ADR_AMBER_UART1_LCRH           0x17000008
#define ADR_AMBER_UART1_LCRM           0x1700000c
#define ADR_AMBER_UART1_LCRL           0x17000010
#define ADR_AMBER_UART1_CR             0x17000014
#define ADR_AMBER_UART1_FR             0x17000018
#define ADR_AMBER_UART1_IIR            0x1700001c
#define ADR_AMBER_UART1_ICR            0x1700001c
 
#define ADR_AMBER_CORE_CTRL            0x1300031c
 
#define ADR_ETHMAC_MODER               0x20000000
#define ADR_ETHMAC_INT_SOURCE          0x20000004
#define ADR_ETHMAC_INT_MASK            0x20000008
#define ADR_ETHMAC_MIIMODER            0x20000028
#define ADR_ETHMAC_MIICOMMAND          0x2000002C
#define ADR_ETHMAC_MIIADDRESS          0x20000030
#define ADR_ETHMAC_MIITXDATA           0x20000034
#define ADR_ETHMAC_MIIRXDATA           0x20000038
#define ADR_ETHMAC_MIISTATUS           0x2000003C
#define ADR_ETHMAC_MAC_ADDR0           0x20000040
#define ADR_ETHMAC_MAC_ADDR1           0x20000044
 
#define ADR_ETHMAC_BDBASE              0x20000400
 
#define ADR_HIBOOT_BASE                0x28000000

Line No.	Rev	Author	Line
1	2	csantifort	`/*----------------------------------------------------------------`
2			`// //`
3			`// amber_registers.h //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Defines the address of all registers in the Amber system. //`
10			`// Must be kept synchronized with the equivalent Verilog //`
11			`// file, $AMBER_BASE/hw/vlog/system/register_addresses.v //`
12			`// which is considered the master. //`
13			`// //`
14			`// Author(s): //`
15			`// - Conor Santifort, csantifort.amber@gmail.com //`
16			`// //`
17			`//////////////////////////////////////////////////////////////////`
18			`// //`
19			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
20			`// //`
21			`// This source file may be used and distributed without //`
22			`// restriction provided that this copyright statement is not //`
23			`// removed from the file and that any derivative work contains //`
24			`// the original copyright notice and the associated disclaimer. //`
25			`// //`
26			`// This source file is free software; you can redistribute it //`
27			`// and/or modify it under the terms of the GNU Lesser General //`
28			`// Public License as published by the Free Software Foundation; //`
29			`// either version 2.1 of the License, or (at your option) any //`
30			`// later version. //`
31			`// //`
32			`// This source is distributed in the hope that it will be //`
33			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
34			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
35			`// PURPOSE. See the GNU Lesser General Public License for more //`
36			`// details. //`
37			`// //`
38			`// You should have received a copy of the GNU Lesser General //`
39			`// Public License along with this source; if not, download it //`
40			`// from http://www.opencores.org/lgpl.shtml //`
41			`// //`
42			`----------------------------------------------------------------*/`
43
44			`#define ADR_AMBER_TEST_STATUS 0xf0000000`
45			`#define ADR_AMBER_TEST_FIRQ_TIMER 0xf0000004`
46			`#define ADR_AMBER_TEST_IRQ_TIMER 0xf0000008`
47			`#define ADR_AMBER_TEST_UART_CONTROL 0xf0000010`
48			`#define ADR_AMBER_TEST_UART_STATUS 0xf0000014`
49			`#define ADR_AMBER_TEST_UART_TXD 0xf0000018`
50			`#define ADR_AMBER_TEST_SIM_CTRL 0xf000001c`
51	11	csantifort	`#define ADR_AMBER_TEST_MEM_CTRL 0xf0000020`
52	31	csantifort	`#define ADR_AMBER_TEST_CYCLES 0xf0000024`
53	61	csantifort	`#define ADR_AMBER_TEST_LED 0xf0000028`
54			`#define ADR_AMBER_TEST_PHY_RST 0xf000002c`
55	31	csantifort
56	61	csantifort
57	2	csantifort	`/* Allow access to the random register over`
58			`a 16-word address range to load a series`
59			`of random numbers using lmd instruction. */`
60			`#define ADR_AMBER_TEST_RANDOM_NUM 0xf0000100`
61			`#define ADR_AMBER_TEST_RANDOM_NUM00 0xf0000100`
62			`#define ADR_AMBER_TEST_RANDOM_NUM01 0xf0000104`
63			`#define ADR_AMBER_TEST_RANDOM_NUM02 0xf0000108`
64			`#define ADR_AMBER_TEST_RANDOM_NUM03 0xf000010c`
65			`#define ADR_AMBER_TEST_RANDOM_NUM04 0xf0000110`
66			`#define ADR_AMBER_TEST_RANDOM_NUM05 0xf0000114`
67			`#define ADR_AMBER_TEST_RANDOM_NUM06 0xf0000118`
68			`#define ADR_AMBER_TEST_RANDOM_NUM07 0xf000011c`
69			`#define ADR_AMBER_TEST_RANDOM_NUM08 0xf0000120`
70			`#define ADR_AMBER_TEST_RANDOM_NUM09 0xf0000124`
71			`#define ADR_AMBER_TEST_RANDOM_NUM10 0xf0000128`
72			`#define ADR_AMBER_TEST_RANDOM_NUM11 0xf000012c`
73			`#define ADR_AMBER_TEST_RANDOM_NUM12 0xf0000130`
74			`#define ADR_AMBER_TEST_RANDOM_NUM13 0xf0000134`
75			`#define ADR_AMBER_TEST_RANDOM_NUM14 0xf0000138`
76			`#define ADR_AMBER_TEST_RANDOM_NUM15 0xf000013c`
77	61	csantifort
78			`#define ADR_AMBER_IC_IRQ0_STATUS 0x14000000`
79			`#define ADR_AMBER_IC_IRQ0_RAWSTAT 0x14000004`
80	2	csantifort	`#define ADR_AMBER_IC_IRQ0_ENABLESET 0x14000008`
81	61	csantifort	`#define ADR_AMBER_IC_IRQ0_ENABLECLR 0x1400000c`
82	2	csantifort	`#define ADR_AMBER_IC_INT_SOFTSET_0 0x14000010`
83			`#define ADR_AMBER_IC_INT_SOFTCLEAR_0 0x14000014`
84	61	csantifort	`#define ADR_AMBER_IC_FIRQ0_STATUS 0x14000020`
85			`#define ADR_AMBER_IC_FIRQ0_RAWSTAT 0x14000024`
86			`#define ADR_AMBER_IC_FIRQ0_ENABLESET 0x14000028`
87			`#define ADR_AMBER_IC_FIRQ0_ENABLECLR 0x1400002c`
88			`#define ADR_AMBER_IC_IRQ1_STATUS 0x14000040`
89			`#define ADR_AMBER_IC_IRQ1_RAWSTAT 0x14000044`
90			`#define ADR_AMBER_IC_IRQ1_ENABLESET 0x14000048`
91			`#define ADR_AMBER_IC_IRQ1_ENABLECLR 0x1400004c`
92	2	csantifort	`#define ADR_AMBER_IC_INT_SOFTSET_1 0x14000050`
93			`#define ADR_AMBER_IC_INT_SOFTCLEAR_1 0x14000054`
94	61	csantifort	`#define ADR_AMBER_IC_FIRQ1_STATUS 0x14000060`
95			`#define ADR_AMBER_IC_FIRQ1_RAWSTAT 0x14000064`
96			`#define ADR_AMBER_IC_FIRQ1_ENABLESET 0x14000068`
97			`#define ADR_AMBER_IC_FIRQ1_ENABLECLR 0x1400006c`
98			`#define ADR_AMBER_IC_INT_SOFTSET_2 0x14000090`
99			`#define ADR_AMBER_IC_INT_SOFTCLEAR_2 0x14000094`
100			`#define ADR_AMBER_IC_INT_SOFTSET_3 0x140000d0`
101			`#define ADR_AMBER_IC_INT_SOFTCLEAR_3 0x140000d4`
102	2	csantifort
103	61	csantifort
104	2	csantifort	`#define ADR_AMBER_CT_TIMER0_LOAD 0x13000000`
105	61	csantifort	`#define ADR_AMBER_TM_TIMER0_LOAD 0x13000000`
106			`#define ADR_AMBER_TM_TIMER0_VALUE 0x13000004`
107			`#define ADR_AMBER_TM_TIMER0_CTRL 0x13000008`
108			`#define ADR_AMBER_TM_TIMER0_CLR 0x1300000c`
109	2	csantifort	`#define ADR_AMBER_CT_TIMER1_LOAD 0x13000100`
110	61	csantifort	`#define ADR_AMBER_TM_TIMER1_LOAD 0x13000100`
111			`#define ADR_AMBER_TM_TIMER1_VALUE 0x13000104`
112			`#define ADR_AMBER_TM_TIMER1_CTRL 0x13000108`
113			`#define ADR_AMBER_TM_TIMER1_CLR 0x1300010c`
114	2	csantifort	`#define ADR_AMBER_CT_TIMER2_LOAD 0x13000200`
115	61	csantifort	`#define ADR_AMBER_TM_TIMER2_LOAD 0x13000200`
116			`#define ADR_AMBER_TM_TIMER2_VALUE 0x13000204`
117			`#define ADR_AMBER_TM_TIMER2_CTRL 0x13000208`
118			`#define ADR_AMBER_TM_TIMER2_CLR 0x1300020c`
119	2	csantifort
120			`#define ADR_AMBER_UART0_DR 0x16000000`
121			`#define ADR_AMBER_UART0_RSR 0x16000004`
122			`#define ADR_AMBER_UART0_LCRH 0x16000008`
123			`#define ADR_AMBER_UART0_LCRM 0x1600000c`
124			`#define ADR_AMBER_UART0_LCRL 0x16000010`
125			`#define ADR_AMBER_UART0_CR 0x16000014`
126			`#define ADR_AMBER_UART0_FR 0x16000018`
127			`#define ADR_AMBER_UART0_IIR 0x1600001c`
128			`#define ADR_AMBER_UART0_ICR 0x1600001c`
129
130			`#define ADR_AMBER_UART1_DR 0x17000000`
131			`#define ADR_AMBER_UART1_RSR 0x17000004`
132			`#define ADR_AMBER_UART1_LCRH 0x17000008`
133			`#define ADR_AMBER_UART1_LCRM 0x1700000c`
134			`#define ADR_AMBER_UART1_LCRL 0x17000010`
135			`#define ADR_AMBER_UART1_CR 0x17000014`
136			`#define ADR_AMBER_UART1_FR 0x17000018`
137			`#define ADR_AMBER_UART1_IIR 0x1700001c`
138			`#define ADR_AMBER_UART1_ICR 0x1700001c`
139
140			`#define ADR_AMBER_CORE_CTRL 0x1300031c`
141
142			`#define ADR_ETHMAC_MODER 0x20000000`
143	61	csantifort	`#define ADR_ETHMAC_INT_SOURCE 0x20000004`
144			`#define ADR_ETHMAC_INT_MASK 0x20000008`
145	2	csantifort	`#define ADR_ETHMAC_MIIMODER 0x20000028`
146			`#define ADR_ETHMAC_MIICOMMAND 0x2000002C`
147			`#define ADR_ETHMAC_MIIADDRESS 0x20000030`
148			`#define ADR_ETHMAC_MIITXDATA 0x20000034`
149			`#define ADR_ETHMAC_MIIRXDATA 0x20000038`
150			`#define ADR_ETHMAC_MIISTATUS 0x2000003C`
151	61	csantifort	`#define ADR_ETHMAC_MAC_ADDR0 0x20000040`
152			`#define ADR_ETHMAC_MAC_ADDR1 0x20000044`
153
154	2	csantifort	`#define ADR_ETHMAC_BDBASE 0x20000400`
155	15	csantifort
156			`#define ADR_HIBOOT_BASE 0x28000000`

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[/] [amber/] [trunk/] [sw/] [include/] [amber_registers.h] - Blame information for rev 88