URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [change.log] - Blame information for rev 28

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All notable changes to this project will be documented in this file.
 
 
##[1.5.1] - 3-2-2017
## changed
- src_c/jtag_main.c:  variable length memory support is added.
- NoC emulator:  Jtag tabs are reduced to total of 3.   A 64 core 2-VC NoC emulation is sucessfully tested on DE4 FPGA board.
-ssa: Now can work with fully adaptive routing.
 
 
##[1.5.0] - 13-10-2016
### Added
- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.
- NoC emulator.
- Altor processor.
- Jtag_wb: allow access to the wishbone bus slave ports via Jtag.
- Jtag_main: A C code which allows host PC to have access to the jtag_wb.
 
 
## changed
- Memory IP cores are categorized into two IPs: Single and double port.
- The access via jtag_wb or Altera In-System Memory Content Editor is added as optional via parameter setting for single port memory.
 
 
 
##[1.0.0] - 27-1-2016
### added
- ProNoC: new version with GUI generator
- Interface generator
- IP generator
- Processing tile generator
- NoC based MCSoC generator

Line No.	Rev	Author	Line
1	25	alirezamon	`All notable changes to this project will be documented in this file.`
2
3	28	alirezamon
4			`##[1.5.1] - 3-2-2017`
5			`## changed`
6			`- src_c/jtag_main.c: variable length memory support is added.`
7			`- NoC emulator: Jtag tabs are reduced to total of 3. A 64 core 2-VC NoC emulation is sucessfully tested on DE4 FPGA board.`
8			`-ssa: Now can work with fully adaptive routing.`
9
10
11	25	alirezamon	`##[1.5.0] - 13-10-2016`
12			`### Added`
13			`- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.`
14			`- NoC emulator.`
15			`- Altor processor.`
16			`- Jtag_wb: allow access to the wishbone bus slave ports via Jtag.`
17			`- Jtag_main: A C code which allows host PC to have access to the jtag_wb.`
18
19
20			`## changed`
21			`- Memory IP cores are categorized into two IPs: Single and double port.`
22			`- The access via jtag_wb or Altera In-System Memory Content Editor is added as optional via parameter setting for single port memory.`
23
24
25
26			`##[1.0.0] - 27-1-2016`
27			`### added`
28			`- ProNoC: new version with GUI generator`
29			`- Interface generator`
30			`- IP generator`
31			`- Processing tile generator`
32			`- NoC based MCSoC generator`

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [change.log] - Blame information for rev 28