URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [change.log] - Blame information for rev 31

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All notable changes to this project will be documented in this file.
 
 
##[1.5.2] - 22-2-2017
## changed
- fixed bug in wishbone bus
 
##[1.5.1] - 3-2-2017
## changed
- src_c/jtag_main.c:  variable length memory support is added.
- NoC emulator:  Jtag tabs are reduced to total of 3.   A 64 core 2-VC NoC emulation is sucessfully tested on DE4 FPGA board.
-ssa: Now can work with fully adaptive routing.
 
 
##[1.5.0] - 13-10-2016
### Added
- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.
- NoC emulator.
- Altor processor.
- Jtag_wb: allow access to the wishbone bus slave ports via Jtag.
- Jtag_main: A C code which allows host PC to have access to the jtag_wb.
 
 
## changed
- Memory IP cores are categorized into two IPs: Single and double port.
- The access via jtag_wb or Altera In-System Memory Content Editor is added as optional via parameter setting for single port memory.
 
 
 
##[1.0.0] - 27-1-2016
### added
- ProNoC: new version with GUI generator
- Interface generator
- IP generator
- Processing tile generator
- NoC based MCSoC generator

Line No.	Rev	Author	Line
1	25	alirezamon	`All notable changes to this project will be documented in this file.`
2
3	28	alirezamon
4	31	alirezamon	`##[1.5.2] - 22-2-2017`
5			`## changed`
6			`- fixed bug in wishbone bus`
7
8	28	alirezamon	`##[1.5.1] - 3-2-2017`
9			`## changed`
10			`- src_c/jtag_main.c: variable length memory support is added.`
11			`- NoC emulator: Jtag tabs are reduced to total of 3. A 64 core 2-VC NoC emulation is sucessfully tested on DE4 FPGA board.`
12			`-ssa: Now can work with fully adaptive routing.`
13
14
15	25	alirezamon	`##[1.5.0] - 13-10-2016`
16			`### Added`
17			`- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.`
18			`- NoC emulator.`
19			`- Altor processor.`
20			`- Jtag_wb: allow access to the wishbone bus slave ports via Jtag.`
21			`- Jtag_main: A C code which allows host PC to have access to the jtag_wb.`
22
23
24			`## changed`
25			`- Memory IP cores are categorized into two IPs: Single and double port.`
26			`- The access via jtag_wb or Altera In-System Memory Content Editor is added as optional via parameter setting for single port memory.`
27
28
29
30			`##[1.0.0] - 27-1-2016`
31			`### added`
32			`- ProNoC: new version with GUI generator`
33			`- Interface generator`
34			`- IP generator`
35			`- Processing tile generator`
36			`- NoC based MCSoC generator`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [change.log] - Blame information for rev 31