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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [Communication/] [ProNoC_jtag_wb.IP] - Blame information for rev 48

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#######################################################################
##      File: ProNoC_jtag_wb.IP
##
##      Copyright (C) 2014-2019  Alireza Monemi
##
##      This file is part of ProNoC 1.9.1
##
##      WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
##      MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$ipgen = bless( {
                  'modules' => {
                                 'pronoc_jtag_wb' => {}
                               },
                  'category' => 'Communication',
                  'ports_order' => [
                                     'clk',
                                     'reset',
                                     'status_i',
                                     'm_sel_o',
                                     'm_dat_o',
                                     'm_addr_o',
                                     'm_cti_o',
                                     'm_stb_o',
                                     'm_cyc_o',
                                     'm_we_o',
                                     'm_dat_i',
                                     'm_ack_i',
                                     'jtag_to_wb',
                                     'wb_to_jtag'
                                   ],
                  'parameters' => {
                                    'WB2Jw' => {
                                                 'content' => '',
                                                 'type' => 'Fixed',
                                                 'info' => 'Parameter',
                                                 'redefine_param' => 1,
                                                 'global_param' => 'Parameter',
                                                 'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw  : 1'
                                               },
                                    'Dw' => {
                                              'type' => 'Fixed',
                                              'info' => 'Parameter',
                                              'content' => '',
                                              'default' => '32',
                                              'global_param' => 'Localparam',
                                              'redefine_param' => 1
                                            },
                                    'J2WBw' => {
                                                 'global_param' => 'Parameter',
                                                 'redefine_param' => 1,
                                                 'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1',
                                                 'content' => '',
                                                 'type' => 'Fixed',
                                                 'info' => 'Parameter'
                                               },
                                    'JTAG_INDEX' => {
                                                      'redefine_param' => 1,
                                                      'global_param' => 'Parameter',
                                                      'default' => 'CORE_ID',
                                                      'content' => '',
                                                      'info' => 'The index number id used for communicating with this IP. All modules connected to the same jtag tab should have a unique JTAG index number. The default value is CORE_ID. The core ID is the tile number in MPSoC. So if each tile has one JTAG_TO_WB module, its  index would be different. In case there are multiple number of  JTAG_TO_WB modules in one tile or the CORE_ID index number has been taken by another module such as RAM you need to manualy set a new value for this parameter.',
                                                      'type' => 'Entry'
                                                    },
                                    'JTAG_CONNECT' => {
                                                        'content' => '"ALTERA_JTAG_WB","XILINX_JTAG_WB"',
                                                        'type' => 'Combo-box',
                                                        'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the Virtual JTAG tap IP core from Altera lib is used to communicate with the Host PC.
 
For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the BSCANE2 JTAG tap IP core from XILINX lib is used to communicate with the Host PC.',
                                                        'redefine_param' => 1,
                                                        'global_param' => 'Parameter',
                                                        'default' => '"XILINX_JTAG_WB"'
                                                      },
                                    'JDw' => {
                                               'content' => '',
                                               'info' => 'Parameter',
                                               'type' => 'Fixed',
                                               'global_param' => 'Parameter',
                                               'redefine_param' => 1,
                                               'default' => '32'
                                             },
                                    'JINDEXw' => {
                                                   'content' => '',
                                                   'type' => 'Fixed',
                                                   'info' => 'Parameter',
                                                   'global_param' => 'Parameter',
                                                   'redefine_param' => 1,
                                                   'default' => '8'
                                                 },
                                    'JTAG_CHAIN' => {
                                                      'content' => '1,2,3,4',
                                                      'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the  BSCANE2 JTAG tap number. The default Jtag tap numbers are:
    4: JTAG runtime memory programmers.
    3: UART
    1,2: reserved',
                                                      'type' => 'Combo-box',
                                                      'redefine_param' => 0,
                                                      'global_param' => 'Parameter',
                                                      'default' => '4'
                                                    },
                                    'JSTATUSw' => {
                                                    'info' => 'Parameter',
                                                    'type' => 'Fixed',
                                                    'content' => '',
                                                    'default' => '8',
                                                    'redefine_param' => 1,
                                                    'global_param' => 'Parameter'
                                                  },
                                    'JAw' => {
                                               'content' => '',
                                               'type' => 'Fixed',
                                               'info' => 'Parameter',
                                               'redefine_param' => 1,
                                               'global_param' => 'Parameter',
                                               'default' => '32'
                                             },
                                    'SELw' => {
                                                'type' => 'Fixed',
                                                'info' => 'Parameter',
                                                'content' => '',
                                                'default' => '4',
                                                'redefine_param' => 1,
                                                'global_param' => 'Localparam'
                                              },
                                    'Aw' => {
                                              'content' => '',
                                              'type' => 'Fixed',
                                              'info' => 'Parameter',
                                              'redefine_param' => 1,
                                              'global_param' => 'Localparam',
                                              'default' => '32'
                                            },
                                    'TAGw' => {
                                                'redefine_param' => 1,
                                                'global_param' => 'Localparam',
                                                'default' => '3',
                                                'content' => '',
                                                'info' => 'Parameter',
                                                'type' => 'Fixed'
                                              }
                                  },
                  'module_name' => 'pronoc_jtag_wb',
                  'ports' => {
                               'status_i' => {
                                               'type' => 'input',
                                               'range' => 'JSTATUSw-1 :   0',
                                               'intfc_name' => 'IO',
                                               'intfc_port' => 'NC'
                                             },
                               'm_cyc_o' => {
                                              'type' => 'output',
                                              'range' => '',
                                              'intfc_name' => 'plug:wb_master[0]',
                                              'intfc_port' => 'cyc_o'
                                            },
                               'clk' => {
                                          'intfc_port' => 'clk_i',
                                          'intfc_name' => 'plug:clk[0]',
                                          'range' => '',
                                          'type' => 'input'
                                        },
                               'm_sel_o' => {
                                              'intfc_port' => 'sel_o',
                                              'intfc_name' => 'plug:wb_master[0]',
                                              'range' => 'SELw-1          :   0',
                                              'type' => 'output'
                                            },
                               'm_cti_o' => {
                                              'intfc_port' => 'cti_o',
                                              'intfc_name' => 'plug:wb_master[0]',
                                              'range' => 'TAGw-1          :   0',
                                              'type' => 'output'
                                            },
                               'wb_to_jtag' => {
                                                 'range' => 'WB2Jw-1: 0',
                                                 'type' => 'output',
                                                 'intfc_port' => 'jwb_o',
                                                 'intfc_name' => 'socket:jtag_to_wb[0]'
                                               },
                               'm_we_o' => {
                                             'type' => 'output',
                                             'range' => '',
                                             'intfc_port' => 'we_o',
                                             'intfc_name' => 'plug:wb_master[0]'
                                           },
                               'jtag_to_wb' => {
                                                 'range' => 'J2WBw-1 : 0',
                                                 'type' => 'input',
                                                 'intfc_name' => 'socket:jtag_to_wb[0]',
                                                 'intfc_port' => 'jwb_i'
                                               },
                               'm_dat_i' => {
                                              'intfc_port' => 'dat_i',
                                              'intfc_name' => 'plug:wb_master[0]',
                                              'range' => 'Dw-1           :  0',
                                              'type' => 'input'
                                            },
                               'm_stb_o' => {
                                              'type' => 'output',
                                              'range' => '',
                                              'intfc_port' => 'stb_o',
                                              'intfc_name' => 'plug:wb_master[0]'
                                            },
                               'm_ack_i' => {
                                              'type' => 'input',
                                              'range' => '',
                                              'intfc_port' => 'ack_i',
                                              'intfc_name' => 'plug:wb_master[0]'
                                            },
                               'reset' => {
                                            'intfc_name' => 'plug:reset[0]',
                                            'intfc_port' => 'reset_i',
                                            'type' => 'input',
                                            'range' => ''
                                          },
                               'm_addr_o' => {
                                               'intfc_port' => 'adr_o',
                                               'intfc_name' => 'plug:wb_master[0]',
                                               'range' => 'Aw-1            :   0',
                                               'type' => 'output'
                                             },
                               'm_dat_o' => {
                                              'range' => 'Dw-1            :   0',
                                              'type' => 'output',
                                              'intfc_port' => 'dat_o',
                                              'intfc_name' => 'plug:wb_master[0]'
                                            }
                             },
                  'parameters_order' => [
                                          'JTAG_CONNECT',
                                          'JTAG_INDEX',
                                          'JDw',
                                          'JAw',
                                          'JINDEXw',
                                          'JSTATUSw',
                                          'J2WBw',
                                          'WB2Jw',
                                          'Dw',
                                          'Aw',
                                          'TAGw',
                                          'SELw',
                                          'JTAG_CHAIN'
                                        ],
                  'sockets' => {
                                 'jtag_to_wb' => {
                                                   'connection_num' => 'single connection',
                                                   'value' => 1,
                                                   '0' => {
                                                            'name' => 'jtag_to_wb'
                                                          },
                                                   'type' => 'num'
                                                 }
                               },
                  'plugs' => {
                               'reset' => {
                                            'type' => 'num',
                                            '0' => {
                                                     'name' => 'reset'
                                                   },
                                            'value' => 1
                                          },
                               'wb_master' => {
                                                'value' => 1,
                                                '0' => {
                                                         'name' => 'wb_master'
                                                       },
                                                'type' => 'num'
                                              },
                               'clk' => {
                                          '0' => {
                                                   'name' => 'clk'
                                                 },
                                          'value' => 1,
                                          'type' => 'num'
                                        }
                             },
                  'hdl_files' => [],
                  'version' => 8,
                  'file_name' => 'mpsoc/rtl/src_peripheral/jtag/jtag_wb/pronoc_jtag_wb.v',
                  'gui_status' => {
                                    'timeout' => 0,
                                    'status' => 'ideal'
                                  },
                  'description' => 'JTAG to Wishbone bus interface. This module allows reading/writing data to the IP cores connected to the wishbone bus (e.g. memory cores). ',
                  'ip_name' => 'ProNoC_jtag_wb',
                  'unused' => {
                                'plug:wb_master[0]' => [
                                                         'tag_o',
                                                         'bte_o',
                                                         'err_i',
                                                         'rty_i'
                                                       ]
                              }
                }, 'ip_gen' );

Line No.	Rev	Author	Line
1	48	alirezamon	`#######################################################################`
2			`## File: ProNoC_jtag_wb.IP`
3			`##`
4			`## Copyright (C) 2014-2019 Alireza Monemi`
5			`##`
6			`## This file is part of ProNoC 1.9.1`
7			`##`
8			`## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT`
9			`## MAY CAUSE UNEXPECTED BEHAIVOR.`
10			`################################################################################`
11
12			`$ipgen = bless( {`
13			`'modules' => {`
14			`'pronoc_jtag_wb' => {}`
15			`},`
16			`'category' => 'Communication',`
17			`'ports_order' => [`
18			`'clk',`
19			`'reset',`
20			`'status_i',`
21			`'m_sel_o',`
22			`'m_dat_o',`
23			`'m_addr_o',`
24			`'m_cti_o',`
25			`'m_stb_o',`
26			`'m_cyc_o',`
27			`'m_we_o',`
28			`'m_dat_i',`
29			`'m_ack_i',`
30			`'jtag_to_wb',`
31			`'wb_to_jtag'`
32			`],`
33			`'parameters' => {`
34			`'WB2Jw' => {`
35			`'content' => '',`
36			`'type' => 'Fixed',`
37			`'info' => 'Parameter',`
38			`'redefine_param' => 1,`
39			`'global_param' => 'Parameter',`
40			`'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1'`
41			`},`
42			`'Dw' => {`
43			`'type' => 'Fixed',`
44			`'info' => 'Parameter',`
45			`'content' => '',`
46			`'default' => '32',`
47			`'global_param' => 'Localparam',`
48			`'redefine_param' => 1`
49			`},`
50			`'J2WBw' => {`
51			`'global_param' => 'Parameter',`
52			`'redefine_param' => 1,`
53			`'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1',`
54			`'content' => '',`
55			`'type' => 'Fixed',`
56			`'info' => 'Parameter'`
57			`},`
58			`'JTAG_INDEX' => {`
59			`'redefine_param' => 1,`
60			`'global_param' => 'Parameter',`
61			`'default' => 'CORE_ID',`
62			`'content' => '',`
63			`'info' => 'The index number id used for communicating with this IP. All modules connected to the same jtag tab should have a unique JTAG index number. The default value is CORE_ID. The core ID is the tile number in MPSoC. So if each tile has one JTAG_TO_WB module, its index would be different. In case there are multiple number of JTAG_TO_WB modules in one tile or the CORE_ID index number has been taken by another module such as RAM you need to manualy set a new value for this parameter.',`
64			`'type' => 'Entry'`
65			`},`
66			`'JTAG_CONNECT' => {`
67			`'content' => '"ALTERA_JTAG_WB","XILINX_JTAG_WB"',`
68			`'type' => 'Combo-box',`
69			`'info' => 'For Altera FPGAs define it as "ALTERA_JTAG_WB". In this case, the Virtual JTAG tap IP core from Altera lib is used to communicate with the Host PC.`
70
71			`For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the BSCANE2 JTAG tap IP core from XILINX lib is used to communicate with the Host PC.',`
72			`'redefine_param' => 1,`
73			`'global_param' => 'Parameter',`
74			`'default' => '"XILINX_JTAG_WB"'`
75			`},`
76			`'JDw' => {`
77			`'content' => '',`
78			`'info' => 'Parameter',`
79			`'type' => 'Fixed',`
80			`'global_param' => 'Parameter',`
81			`'redefine_param' => 1,`
82			`'default' => '32'`
83			`},`
84			`'JINDEXw' => {`
85			`'content' => '',`
86			`'type' => 'Fixed',`
87			`'info' => 'Parameter',`
88			`'global_param' => 'Parameter',`
89			`'redefine_param' => 1,`
90			`'default' => '8'`
91			`},`
92			`'JTAG_CHAIN' => {`
93			`'content' => '1,2,3,4',`
94			`'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:`
95			`4: JTAG runtime memory programmers.`
96			`3: UART`
97			`1,2: reserved',`
98			`'type' => 'Combo-box',`
99			`'redefine_param' => 0,`
100			`'global_param' => 'Parameter',`
101			`'default' => '4'`
102			`},`
103			`'JSTATUSw' => {`
104			`'info' => 'Parameter',`
105			`'type' => 'Fixed',`
106			`'content' => '',`
107			`'default' => '8',`
108			`'redefine_param' => 1,`
109			`'global_param' => 'Parameter'`
110			`},`
111			`'JAw' => {`
112			`'content' => '',`
113			`'type' => 'Fixed',`
114			`'info' => 'Parameter',`
115			`'redefine_param' => 1,`
116			`'global_param' => 'Parameter',`
117			`'default' => '32'`
118			`},`
119			`'SELw' => {`
120			`'type' => 'Fixed',`
121			`'info' => 'Parameter',`
122			`'content' => '',`
123			`'default' => '4',`
124			`'redefine_param' => 1,`
125			`'global_param' => 'Localparam'`
126			`},`
127			`'Aw' => {`
128			`'content' => '',`
129			`'type' => 'Fixed',`
130			`'info' => 'Parameter',`
131			`'redefine_param' => 1,`
132			`'global_param' => 'Localparam',`
133			`'default' => '32'`
134			`},`
135			`'TAGw' => {`
136			`'redefine_param' => 1,`
137			`'global_param' => 'Localparam',`
138			`'default' => '3',`
139			`'content' => '',`
140			`'info' => 'Parameter',`
141			`'type' => 'Fixed'`
142			`}`
143			`},`
144			`'module_name' => 'pronoc_jtag_wb',`
145			`'ports' => {`
146			`'status_i' => {`
147			`'type' => 'input',`
148			`'range' => 'JSTATUSw-1 : 0',`
149			`'intfc_name' => 'IO',`
150			`'intfc_port' => 'NC'`
151			`},`
152			`'m_cyc_o' => {`
153			`'type' => 'output',`
154			`'range' => '',`
155			`'intfc_name' => 'plug:wb_master[0]',`
156			`'intfc_port' => 'cyc_o'`
157			`},`
158			`'clk' => {`
159			`'intfc_port' => 'clk_i',`
160			`'intfc_name' => 'plug:clk[0]',`
161			`'range' => '',`
162			`'type' => 'input'`
163			`},`
164			`'m_sel_o' => {`
165			`'intfc_port' => 'sel_o',`
166			`'intfc_name' => 'plug:wb_master[0]',`
167			`'range' => 'SELw-1 : 0',`
168			`'type' => 'output'`
169			`},`
170			`'m_cti_o' => {`
171			`'intfc_port' => 'cti_o',`
172			`'intfc_name' => 'plug:wb_master[0]',`
173			`'range' => 'TAGw-1 : 0',`
174			`'type' => 'output'`
175			`},`
176			`'wb_to_jtag' => {`
177			`'range' => 'WB2Jw-1: 0',`
178			`'type' => 'output',`
179			`'intfc_port' => 'jwb_o',`
180			`'intfc_name' => 'socket:jtag_to_wb[0]'`
181			`},`
182			`'m_we_o' => {`
183			`'type' => 'output',`
184			`'range' => '',`
185			`'intfc_port' => 'we_o',`
186			`'intfc_name' => 'plug:wb_master[0]'`
187			`},`
188			`'jtag_to_wb' => {`
189			`'range' => 'J2WBw-1 : 0',`
190			`'type' => 'input',`
191			`'intfc_name' => 'socket:jtag_to_wb[0]',`
192			`'intfc_port' => 'jwb_i'`
193			`},`
194			`'m_dat_i' => {`
195			`'intfc_port' => 'dat_i',`
196			`'intfc_name' => 'plug:wb_master[0]',`
197			`'range' => 'Dw-1 : 0',`
198			`'type' => 'input'`
199			`},`
200			`'m_stb_o' => {`
201			`'type' => 'output',`
202			`'range' => '',`
203			`'intfc_port' => 'stb_o',`
204			`'intfc_name' => 'plug:wb_master[0]'`
205			`},`
206			`'m_ack_i' => {`
207			`'type' => 'input',`
208			`'range' => '',`
209			`'intfc_port' => 'ack_i',`
210			`'intfc_name' => 'plug:wb_master[0]'`
211			`},`
212			`'reset' => {`
213			`'intfc_name' => 'plug:reset[0]',`
214			`'intfc_port' => 'reset_i',`
215			`'type' => 'input',`
216			`'range' => ''`
217			`},`
218			`'m_addr_o' => {`
219			`'intfc_port' => 'adr_o',`
220			`'intfc_name' => 'plug:wb_master[0]',`
221			`'range' => 'Aw-1 : 0',`
222			`'type' => 'output'`
223			`},`
224			`'m_dat_o' => {`
225			`'range' => 'Dw-1 : 0',`
226			`'type' => 'output',`
227			`'intfc_port' => 'dat_o',`
228			`'intfc_name' => 'plug:wb_master[0]'`
229			`}`
230			`},`
231			`'parameters_order' => [`
232			`'JTAG_CONNECT',`
233			`'JTAG_INDEX',`
234			`'JDw',`
235			`'JAw',`
236			`'JINDEXw',`
237			`'JSTATUSw',`
238			`'J2WBw',`
239			`'WB2Jw',`
240			`'Dw',`
241			`'Aw',`
242			`'TAGw',`
243			`'SELw',`
244			`'JTAG_CHAIN'`
245			`],`
246			`'sockets' => {`
247			`'jtag_to_wb' => {`
248			`'connection_num' => 'single connection',`
249			`'value' => 1,`
250			`'0' => {`
251			`'name' => 'jtag_to_wb'`
252			`},`
253			`'type' => 'num'`
254			`}`
255			`},`
256			`'plugs' => {`
257			`'reset' => {`
258			`'type' => 'num',`
259			`'0' => {`
260			`'name' => 'reset'`
261			`},`
262			`'value' => 1`
263			`},`
264			`'wb_master' => {`
265			`'value' => 1,`
266			`'0' => {`
267			`'name' => 'wb_master'`
268			`},`
269			`'type' => 'num'`
270			`},`
271			`'clk' => {`
272			`'0' => {`
273			`'name' => 'clk'`
274			`},`
275			`'value' => 1,`
276			`'type' => 'num'`
277			`}`
278			`},`
279			`'hdl_files' => [],`
280			`'version' => 8,`
281			`'file_name' => 'mpsoc/rtl/src_peripheral/jtag/jtag_wb/pronoc_jtag_wb.v',`
282			`'gui_status' => {`
283			`'timeout' => 0,`
284			`'status' => 'ideal'`
285			`},`
286			`'description' => 'JTAG to Wishbone bus interface. This module allows reading/writing data to the IP cores connected to the wishbone bus (e.g. memory cores). ',`
287			`'ip_name' => 'ProNoC_jtag_wb',`
288			`'unused' => {`
289			`'plug:wb_master[0]' => [`
290			`'tag_o',`
291			`'bte_o',`
292			`'err_i',`
293			`'rty_i'`
294			`]`
295			`}`
296			`}, 'ip_gen' );`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [Communication/] [ProNoC_jtag_wb.IP] - Blame information for rev 48