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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [Communication/] [ethmac_100.IP] - Blame information for rev 48

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#######################################################################
##      File: ethmac_100.IP
##
##      Copyright (C) 2014-2019  Alireza Monemi
##
##      This file is part of ProNoC 1.9.1
##
##      WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
##      MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$ipgen = bless( {
                  'version' => 2,
                  'parameters' => {
                                    'TX_FIFO_DATA_WIDTH' => {
                                                              'type' => 'Fixed',
                                                              'global_param' => 0,
                                                              'redefine_param' => 1,
                                                              'default' => ' 32',
                                                              'content' => '',
                                                              'info' => undef
                                                            },
                                    'TX_FIFO_DEPTH' => {
                                                         'default' => ' 16',
                                                         'content' => '',
                                                         'info' => undef,
                                                         'type' => 'Fixed',
                                                         'redefine_param' => 1,
                                                         'global_param' => 0
                                                       },
                                    'RX_FIFO_CNT_WIDTH' => {
                                                             'info' => undef,
                                                             'default' => ' 5',
                                                             'content' => '',
                                                             'global_param' => 0,
                                                             'redefine_param' => 1,
                                                             'type' => 'Fixed'
                                                           },
                                    'RX_FIFO_DATA_WIDTH' => {
                                                              'default' => ' 32',
                                                              'content' => '',
                                                              'info' => undef,
                                                              'type' => 'Fixed',
                                                              'global_param' => 0,
                                                              'redefine_param' => 1
                                                            },
                                    'TX_FIFO_CNT_WIDTH' => {
                                                             'content' => '',
                                                             'default' => ' 5',
                                                             'info' => undef,
                                                             'type' => 'Fixed',
                                                             'redefine_param' => 1,
                                                             'global_param' => 0
                                                           },
                                    'RX_FIFO_DEPTH' => {
                                                         'default' => ' 16',
                                                         'content' => '',
                                                         'info' => undef,
                                                         'type' => 'Fixed',
                                                         'global_param' => 0,
                                                         'redefine_param' => 1
                                                       }
                                  },
                  'gen_sw_files' => [
                                      '/mpsoc/rtl/src_peripheral/ethmac/ethfrename_sep_t${IP}.h'
                                    ],
                  'system_h' => '
 
void ${IP}_init();
void ${IP}_interrupt();
void ${IP}_recv_ack(void);
int ${IP}_send(int length);   //return (-1) or length (still processing previous) or asserted
 
#define ${IP}_BASE_ADDR         $BASE
#define ${IP}_MODER                     (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x00 )))
#define ${IP}_INT_SOURCE                (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x04 )))
#define ${IP}_INT_MASK                   (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x08 )))
#define ${IP}_IPGT                       (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x0C )))
#define ${IP}_IPGR1                      (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x10 )))
#define ${IP}_IPGR2                     (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x14 )))
#define ${IP}_PACKETLEN                  (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x18 )))
#define ${IP}_COLLCONF                   (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x1C )))
#define ${IP}_TX_BD_NUM                  (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x20 )))
#define ${IP}_CTRLMODER                  (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x24 )))
#define ${IP}_MIIMODER                   (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x28 )))
#define ${IP}_MIICOMMAND                 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x2C )))
#define ${IP}_MIIADDR                    (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x30 )))
#define ${IP}_MIITX_DATA                 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x34 )))
#define ${IP}_MIIRX_DATA                 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x38 )))
#define ${IP}_MIISTATUS                  (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x3C )))
#define ${IP}_MAC_ADDR0                  (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x40 )))
#define ${IP}_MAC_ADDR1                  (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x44 )))
#define ${IP}_HASH0_ADR                  (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x48 )))
#define ${IP}_HASH1_ADR                  (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x4C )))
#define ${IP}_TXCTRL                             (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x50 )))
#define ${IP}_TXBD0H                    (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x404 )))
#define ${IP}_TXBD0L                            (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x400 )))
#define ${IP}_RXBD0H                    (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x604 ))) //this depends on TX_BD_NUM but this is the standard value
#define ${IP}_RXBD0L                            (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x600 ))) //this depends on TX_BD_NUM but this is the standard value
 
 
#include "${IP}.h"',
                  'plugs' => {
                               'reset' => {
                                            'reset' => {},
                                            'type' => 'num',
                                            'value' => 1,
                                            '0' => {
                                                     'name' => 'reset'
                                                   }
                                          },
                               'wb_slave' => {
                                               'value' => 1,
                                               'type' => 'num',
                                               'wb_slave' => {},
                                               '0' => {
                                                        'width' => 11,
                                                        'name' => 'wb_slave',
                                                        'addr' => '0x9200_0000  0x92ff_ffff             Ethernet Controller'
                                                      }
                                             },
                               'interrupt_peripheral' => {
                                                           '0' => {
                                                                    'name' => 'interrupt_peripheral'
                                                                  },
                                                           'interrupt_peripheral' => {},
                                                           'type' => 'num',
                                                           'value' => 1
                                                         },
                               'clk' => {
                                          'clk' => {},
                                          '0' => {
                                                   'name' => 'clk'
                                                 },
                                          'type' => 'num',
                                          'value' => 1
                                        },
                               'wb_master' => {
                                                'value' => 1,
                                                'type' => 'num',
                                                'wb_master' => {},
                                                '0' => {
                                                         'name' => 'wb_master'
                                                       }
                                              }
                             },
                  'sw_files' => [],
                  'custom_file' => {
                                     '0' => {}
                                   },
                  'file_name' => 'mpsoc/rtl/src_peripheral/ethmac/ethtop.v',
                  'custom_file_num' => 1,
                  'parameters_order' => [
                                          'TX_FIFO_DATA_WIDTH',
                                          'TX_FIFO_DEPTH',
                                          'TX_FIFO_CNT_WIDTH',
                                          'RX_FIFO_DATA_WIDTH',
                                          'RX_FIFO_DEPTH',
                                          'RX_FIFO_CNT_WIDTH'
                                        ],
                  'ip_name' => 'ethmac_100',
                  'description' => 'The Ethernet MAC 10/100 Mbps.
For more information please check: https://opencores.org/project,ethmac',
                  'ports' => {
                               'm_wb_adr_o' => {
                                                 'intfc_port' => 'adr_o',
                                                 'range' => '31:0',
                                                 'type' => 'output',
                                                 'intfc_name' => 'plug:wb_master[0]'
                                               },
                               'wb_err_o' => {
                                               'intfc_name' => 'plug:wb_slave[0]',
                                               'range' => '',
                                               'type' => 'output',
                                               'intfc_port' => 'err_o'
                                             },
                               'wb_we_i' => {
                                              'range' => '',
                                              'type' => 'input',
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'intfc_port' => 'we_i'
                                            },
                               'm_wb_sel_o' => {
                                                 'intfc_name' => 'plug:wb_master[0]',
                                                 'range' => '3:0',
                                                 'type' => 'output',
                                                 'intfc_port' => 'sel_o'
                                               },
                               'mrxdv_pad_i' => {
                                                  'range' => '',
                                                  'type' => 'input',
                                                  'intfc_name' => 'IO',
                                                  'intfc_port' => 'IO'
                                                },
                               'int_o' => {
                                            'intfc_port' => 'int_o',
                                            'type' => 'output',
                                            'range' => '',
                                            'intfc_name' => 'plug:interrupt_peripheral[0]'
                                          },
                               'm_wb_dat_i' => {
                                                 'intfc_port' => 'dat_i',
                                                 'type' => 'input',
                                                 'range' => '31:0',
                                                 'intfc_name' => 'plug:wb_master[0]'
                                               },
                               'wb_clk_i' => {
                                               'type' => 'input',
                                               'range' => '',
                                               'intfc_name' => 'plug:clk[0]',
                                               'intfc_port' => 'clk_i'
                                             },
                               'm_wb_ack_i' => {
                                                 'type' => 'input',
                                                 'range' => '',
                                                 'intfc_name' => 'plug:wb_master[0]',
                                                 'intfc_port' => 'ack_i'
                                               },
                               'wb_rst_i' => {
                                               'intfc_port' => 'reset_i',
                                               'range' => '',
                                               'type' => 'input',
                                               'intfc_name' => 'plug:reset[0]'
                                             },
                               'mrxd_pad_i' => {
                                                 'intfc_port' => 'IO',
                                                 'range' => '3:0',
                                                 'type' => 'input',
                                                 'intfc_name' => 'IO'
                                               },
                               'mtxerr_pad_o' => {
                                                   'intfc_port' => 'IO',
                                                   'intfc_name' => 'IO',
                                                   'type' => 'output',
                                                   'range' => ''
                                                 },
                               'md_pad_o' => {
                                               'intfc_port' => 'IO',
                                               'intfc_name' => 'IO',
                                               'type' => 'output',
                                               'range' => ''
                                             },
                               'wb_adr_i' => {
                                               'intfc_port' => 'adr_i',
                                               'intfc_name' => 'plug:wb_slave[0]',
                                               'type' => 'input',
                                               'range' => '9:0'
                                             },
                               'wb_dat_o' => {
                                               'intfc_port' => 'dat_o',
                                               'intfc_name' => 'plug:wb_slave[0]',
                                               'range' => '31:0',
                                               'type' => 'output'
                                             },
                               'm_wb_err_i' => {
                                                 'intfc_name' => 'plug:wb_master[0]',
                                                 'type' => 'input',
                                                 'range' => '',
                                                 'intfc_port' => 'err_i'
                                               },
                               'mtxen_pad_o' => {
                                                  'intfc_port' => 'IO',
                                                  'intfc_name' => 'IO',
                                                  'range' => '',
                                                  'type' => 'output'
                                                },
                               'mrxerr_pad_i' => {
                                                   'type' => 'input',
                                                   'range' => '',
                                                   'intfc_name' => 'IO',
                                                   'intfc_port' => 'IO'
                                                 },
                               'mtx_clk_pad_i' => {
                                                    'type' => 'input',
                                                    'range' => '',
                                                    'intfc_name' => 'IO',
                                                    'intfc_port' => 'IO'
                                                  },
                               'm_wb_stb_o' => {
                                                 'intfc_port' => 'stb_o',
                                                 'intfc_name' => 'plug:wb_master[0]',
                                                 'type' => 'output',
                                                 'range' => ''
                                               },
                               'mcrs_pad_i' => {
                                                 'type' => 'input',
                                                 'range' => '',
                                                 'intfc_name' => 'IO',
                                                 'intfc_port' => 'IO'
                                               },
                               'm_wb_dat_o' => {
                                                 'intfc_port' => 'dat_o',
                                                 'intfc_name' => 'plug:wb_master[0]',
                                                 'type' => 'output',
                                                 'range' => '31:0'
                                               },
                               'm_wb_we_o' => {
                                                'intfc_port' => 'we_o',
                                                'range' => '',
                                                'type' => 'output',
                                                'intfc_name' => 'plug:wb_master[0]'
                                              },
                               'mdc_pad_o' => {
                                                'range' => '',
                                                'type' => 'output',
                                                'intfc_name' => 'IO',
                                                'intfc_port' => 'IO'
                                              },
                               'mtxd_pad_o' => {
                                                 'type' => 'output',
                                                 'range' => '3:0',
                                                 'intfc_name' => 'IO',
                                                 'intfc_port' => 'IO'
                                               },
                               'wb_stb_i' => {
                                               'intfc_port' => 'stb_i',
                                               'intfc_name' => 'plug:wb_slave[0]',
                                               'type' => 'input',
                                               'range' => ''
                                             },
                               'md_pad_i' => {
                                               'intfc_name' => 'IO',
                                               'range' => '',
                                               'type' => 'input',
                                               'intfc_port' => 'IO'
                                             },
                               'wb_ack_o' => {
                                               'range' => '',
                                               'type' => 'output',
                                               'intfc_name' => 'plug:wb_slave[0]',
                                               'intfc_port' => 'ack_o'
                                             },
                               'mcoll_pad_i' => {
                                                  'intfc_name' => 'IO',
                                                  'range' => '',
                                                  'type' => 'input',
                                                  'intfc_port' => 'IO'
                                                },
                               'm_wb_cyc_o' => {
                                                 'range' => '',
                                                 'type' => 'output',
                                                 'intfc_name' => 'plug:wb_master[0]',
                                                 'intfc_port' => 'cyc_o'
                                               },
                               'wb_cyc_i' => {
                                               'intfc_name' => 'plug:wb_slave[0]',
                                               'range' => '',
                                               'type' => 'input',
                                               'intfc_port' => 'cyc_i'
                                             },
                               'wb_sel_i' => {
                                               'intfc_port' => 'sel_i',
                                               'intfc_name' => 'plug:wb_slave[0]',
                                               'range' => '3:0',
                                               'type' => 'input'
                                             },
                               'wb_dat_i' => {
                                               'intfc_port' => 'dat_i',
                                               'intfc_name' => 'plug:wb_slave[0]',
                                               'range' => '31:0',
                                               'type' => 'input'
                                             },
                               'md_padoe_o' => {
                                                 'intfc_name' => 'IO',
                                                 'type' => 'output',
                                                 'range' => '',
                                                 'intfc_port' => 'IO'
                                               },
                               'mrx_clk_pad_i' => {
                                                    'intfc_port' => 'IO',
                                                    'intfc_name' => 'IO',
                                                    'range' => '',
                                                    'type' => 'input'
                                                  }
                             },
                  'module_name' => 'ethtop',
                  'unused' => {
                                'plug:wb_master[0]' => [
                                                         'tag_o',
                                                         'rty_i',
                                                         'bte_o',
                                                         'cti_o'
                                                       ],
                                'plug:wb_slave[0]' => [
                                                        'cti_i',
                                                        'bte_i',
                                                        'rty_o',
                                                        'tag_i'
                                                      ]
                              },
                  'hdl_files' => [
                                   '/mpsoc/rtl/src_peripheral/ethmac'
                                 ],
                  'category' => 'Communication',
                  'modules' => {
                                 'ethtop' => {}
                               },
                  'gui_status' => {
                                    'status' => 'ideal',
                                    'timeout' => 0
                                  },
                  'ports_order' => [
                                     'wb_clk_i',
                                     'wb_rst_i',
                                     'wb_dat_i',
                                     'wb_dat_o',
                                     'wb_adr_i',
                                     'wb_sel_i',
                                     'wb_we_i',
                                     'wb_cyc_i',
                                     'wb_stb_i',
                                     'wb_ack_o',
                                     'wb_err_o',
                                     'm_wb_adr_o',
                                     'm_wb_sel_o',
                                     'm_wb_we_o',
                                     'm_wb_dat_o',
                                     'm_wb_dat_i',
                                     'm_wb_cyc_o',
                                     'm_wb_stb_o',
                                     'm_wb_ack_i',
                                     'm_wb_err_i',
                                     'mtx_clk_pad_i',
                                     'mtxd_pad_o',
                                     'mtxen_pad_o',
                                     'mtxerr_pad_o',
                                     'mrx_clk_pad_i',
                                     'mrxd_pad_i',
                                     'mrxdv_pad_i',
                                     'mrxerr_pad_i',
                                     'mcoll_pad_i',
                                     'mcrs_pad_i',
                                     'mdc_pad_o',
                                     'md_pad_i',
                                     'md_pad_o',
                                     'md_padoe_o',
                                     'int_o'
                                   ],
                  'system_c' => 'void ${IP}_recv_ack(void)
{
        ${IP}_rx_done = 0;
        ${IP}_rx_len = 0;
        //accept further data (reset RXBD to empty)
        ${IP}_RXBD0L = RX_READY;        //len = 0 | IRQ & WR = 1 | EMPTY = 1
}
 
void ${IP}_init()
{
        //TXEN & RXEN = 1; PAD & CRC = 1; FULLD = 1
        ${IP}_MODER = ETH_TXEN | ETH_RXEN | ETH_PAD | ETH_CRCEN | ETH_FULLD;
        //PHY ADDR = 0x001
        ${IP}_MIIADDR = 0x00000001;
 
        //enable all interrupts
        ${IP}_INT_MASK = ETH_RXB | ETH_TXB;
 
        //set MAC ADDR
        ${IP}_MAC_ADDR1 = (${IP}_MAC_ADDR_5 << 8) | ${IP}_MAC_ADDR_4;   //low word = mac ADDR high word
        ${IP}_MAC_ADDR0 = (${IP}_MAC_ADDR_3 << 24) | (${IP}_MAC_ADDR_2 << 16)
                | (${IP}_MAC_ADDR_1 << 8) | ${IP}_MAC_ADDR_0;           //mac ADDR rest
 
        //configure TXBD0
        ${IP}_TXBD0H = (unsigned long) ${IP}_tx_packet;         //ADDR used for tx_data
        ${IP}_TXBD0L = TX_READY;        //length = 0 | PAD & CRC = 1 | IRQ & WR = 1
 
        //configure RXBD0
        ${IP}_RXBD0H = (unsigned long)${IP}_rx_packet;          //ADDR used for tx_data
        ${IP}_RXBD0L = RX_READY;        //len = 0 | IRQ & WR = 1 | EMPTY = 1
 
        //set txdata
        ${IP}_tx_packet[0] = ${IP}_BROADCAST_ADDR_5;
        ${IP}_tx_packet[1] = ${IP}_BROADCAST_ADDR_4;
        ${IP}_tx_packet[2] = ${IP}_BROADCAST_ADDR_3;
        ${IP}_tx_packet[3] = ${IP}_BROADCAST_ADDR_2;
        ${IP}_tx_packet[4] = ${IP}_BROADCAST_ADDR_1;
        ${IP}_tx_packet[5] = ${IP}_BROADCAST_ADDR_0;
 
        ${IP}_tx_packet[6] = ${IP}_MAC_ADDR_5;
        ${IP}_tx_packet[7] = ${IP}_MAC_ADDR_4;
        ${IP}_tx_packet[8] = ${IP}_MAC_ADDR_3;
        ${IP}_tx_packet[9] = ${IP}_MAC_ADDR_2;
        ${IP}_tx_packet[10] = ${IP}_MAC_ADDR_1;
        ${IP}_tx_packet[11] = ${IP}_MAC_ADDR_0;
 
        //erase interrupts
        ${IP}_INT_SOURCE = ETH_RXC | ETH_TXC | ETH_BUSY | ETH_RXE | ETH_RXB | ETH_TXE | ETH_TXB;
 
        ${IP}_tx_done = 1;
        ${IP}_rx_done = 0;
        ${IP}_rx_len  = 0;
        ${IP}_tx_data = & ${IP}_tx_packet[HDR_LEN];
        ${IP}_rx_data = & ${IP}_rx_packet[HDR_LEN];
}
 
 
int ${IP}_send(int length)
{
        if (!${IP}_tx_done)       //if previous command not fully processed, bail out
                return -1;
 
        ${IP}_tx_done = 0;
        ${IP}_tx_packet[12] = length >> 8;
        ${IP}_tx_packet[13] = length;
 
        ${IP}_TXBD0L = (( 0x0000FFFF & ( length + HDR_LEN ) ) << 16) | BD_SND;
 
        return length;
}
 
void ${IP}_interrupt()
{
        unsigned long source = ${IP}_INT_SOURCE;
        if ( source & ETH_TXB )
        {
                ${IP}_tx_done = 1;
                //erase interrupt
                ${IP}_INT_SOURCE |= ETH_TXB;
        }
        if ( source & ETH_RXB )
        {
                ${IP}_rx_done = 1;
                ${IP}_rx_len = (${IP}_RXBD0L >> 16) - HDR_LEN - CRC_LEN;
                //erase interrupt
                ${IP}_INT_SOURCE |= ETH_RXB;
        }
}'
                }, 'ip_gen' );

Line No.	Rev	Author	Line
1	38	alirezamon	`#######################################################################`
2			`## File: ethmac_100.IP`
3			`##`
4	48	alirezamon	`## Copyright (C) 2014-2019 Alireza Monemi`
5	38	alirezamon	`##`
6	48	alirezamon	`## This file is part of ProNoC 1.9.1`
7	38	alirezamon	`##`
8			`## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT`
9			`## MAY CAUSE UNEXPECTED BEHAIVOR.`
10			`################################################################################`
11
12	48	alirezamon	`$ipgen = bless( {`
13			`'version' => 2,`
14			`'parameters' => {`
15			`'TX_FIFO_DATA_WIDTH' => {`
16			`'type' => 'Fixed',`
17			`'global_param' => 0,`
18			`'redefine_param' => 1,`
19			`'default' => ' 32',`
20			`'content' => '',`
21			`'info' => undef`
22			`},`
23			`'TX_FIFO_DEPTH' => {`
24			`'default' => ' 16',`
25			`'content' => '',`
26			`'info' => undef,`
27			`'type' => 'Fixed',`
28			`'redefine_param' => 1,`
29			`'global_param' => 0`
30			`},`
31			`'RX_FIFO_CNT_WIDTH' => {`
32			`'info' => undef,`
33			`'default' => ' 5',`
34			`'content' => '',`
35			`'global_param' => 0,`
36			`'redefine_param' => 1,`
37			`'type' => 'Fixed'`
38			`},`
39			`'RX_FIFO_DATA_WIDTH' => {`
40			`'default' => ' 32',`
41			`'content' => '',`
42			`'info' => undef,`
43			`'type' => 'Fixed',`
44			`'global_param' => 0,`
45			`'redefine_param' => 1`
46			`},`
47			`'TX_FIFO_CNT_WIDTH' => {`
48			`'content' => '',`
49			`'default' => ' 5',`
50			`'info' => undef,`
51			`'type' => 'Fixed',`
52			`'redefine_param' => 1,`
53			`'global_param' => 0`
54			`},`
55			`'RX_FIFO_DEPTH' => {`
56			`'default' => ' 16',`
57			`'content' => '',`
58			`'info' => undef,`
59			`'type' => 'Fixed',`
60			`'global_param' => 0,`
61			`'redefine_param' => 1`
62			`}`
63			`},`
64			`'gen_sw_files' => [`
65			`'/mpsoc/rtl/src_peripheral/ethmac/ethfrename_sep_t${IP}.h'`
66			`],`
67			`'system_h' => '`
68
69			`void ${IP}_init();`
70			`void ${IP}_interrupt();`
71			`void ${IP}_recv_ack(void);`
72			`int ${IP}_send(int length); //return (-1) or length (still processing previous) or asserted`
73
74			`#define ${IP}_BASE_ADDR $BASE`
75			`#define ${IP}_MODER (((volatile unsigned int ) (${IP}_BASE_ADDR+0x00 )))`
76			`#define ${IP}_INT_SOURCE (((volatile unsigned int ) (${IP}_BASE_ADDR+0x04 )))`
77			`#define ${IP}_INT_MASK (((volatile unsigned int ) (${IP}_BASE_ADDR+0x08 )))`
78			`#define ${IP}_IPGT (((volatile unsigned int ) (${IP}_BASE_ADDR+0x0C )))`
79			`#define ${IP}_IPGR1 (((volatile unsigned int ) (${IP}_BASE_ADDR+0x10 )))`
80			`#define ${IP}_IPGR2 (((volatile unsigned int ) (${IP}_BASE_ADDR+0x14 )))`
81			`#define ${IP}_PACKETLEN (((volatile unsigned int ) (${IP}_BASE_ADDR+0x18 )))`
82			`#define ${IP}_COLLCONF (((volatile unsigned int ) (${IP}_BASE_ADDR+0x1C )))`
83			`#define ${IP}_TX_BD_NUM (((volatile unsigned int ) (${IP}_BASE_ADDR+0x20 )))`
84			`#define ${IP}_CTRLMODER (((volatile unsigned int ) (${IP}_BASE_ADDR+0x24 )))`
85			`#define ${IP}_MIIMODER (((volatile unsigned int ) (${IP}_BASE_ADDR+0x28 )))`
86			`#define ${IP}_MIICOMMAND (((volatile unsigned int ) (${IP}_BASE_ADDR+0x2C )))`
87			`#define ${IP}_MIIADDR (((volatile unsigned int ) (${IP}_BASE_ADDR+0x30 )))`
88			`#define ${IP}_MIITX_DATA (((volatile unsigned int ) (${IP}_BASE_ADDR+0x34 )))`
89			`#define ${IP}_MIIRX_DATA (((volatile unsigned int ) (${IP}_BASE_ADDR+0x38 )))`
90			`#define ${IP}_MIISTATUS (((volatile unsigned int ) (${IP}_BASE_ADDR+0x3C )))`
91			`#define ${IP}_MAC_ADDR0 (((volatile unsigned int ) (${IP}_BASE_ADDR+0x40 )))`
92			`#define ${IP}_MAC_ADDR1 (((volatile unsigned int ) (${IP}_BASE_ADDR+0x44 )))`
93			`#define ${IP}_HASH0_ADR (((volatile unsigned int ) (${IP}_BASE_ADDR+0x48 )))`
94			`#define ${IP}_HASH1_ADR (((volatile unsigned int ) (${IP}_BASE_ADDR+0x4C )))`
95			`#define ${IP}_TXCTRL (((volatile unsigned int ) (${IP}_BASE_ADDR+0x50 )))`
96			`#define ${IP}_TXBD0H (((volatile unsigned int ) (${IP}_BASE_ADDR+0x404 )))`
97			`#define ${IP}_TXBD0L (((volatile unsigned int ) (${IP}_BASE_ADDR+0x400 )))`
98			`#define ${IP}_RXBD0H (((volatile unsigned int ) (${IP}_BASE_ADDR+0x604 ))) //this depends on TX_BD_NUM but this is the standard value`
99			`#define ${IP}_RXBD0L (((volatile unsigned int ) (${IP}_BASE_ADDR+0x600 ))) //this depends on TX_BD_NUM but this is the standard value`
100
101
102			`#include "${IP}.h"',`
103			`'plugs' => {`
104			`'reset' => {`
105			`'reset' => {},`
106			`'type' => 'num',`
107			`'value' => 1,`
108			`'0' => {`
109			`'name' => 'reset'`
110			`}`
111			`},`
112			`'wb_slave' => {`
113			`'value' => 1,`
114			`'type' => 'num',`
115			`'wb_slave' => {},`
116			`'0' => {`
117			`'width' => 11,`
118			`'name' => 'wb_slave',`
119			`'addr' => '0x9200_0000 0x92ff_ffff Ethernet Controller'`
120			`}`
121			`},`
122			`'interrupt_peripheral' => {`
123			`'0' => {`
124			`'name' => 'interrupt_peripheral'`
125			`},`
126			`'interrupt_peripheral' => {},`
127			`'type' => 'num',`
128			`'value' => 1`
129			`},`
130			`'clk' => {`
131			`'clk' => {},`
132			`'0' => {`
133			`'name' => 'clk'`
134			`},`
135			`'type' => 'num',`
136			`'value' => 1`
137			`},`
138			`'wb_master' => {`
139	38	alirezamon	`'value' => 1,`
140			`'type' => 'num',`
141	48	alirezamon	`'wb_master' => {},`
142	38	alirezamon	`'0' => {`
143	48	alirezamon	`'name' => 'wb_master'`
144	38	alirezamon	`}`
145	48	alirezamon	`}`
146			`},`
147			`'sw_files' => [],`
148			`'custom_file' => {`
149			`'0' => {}`
150			`},`
151			`'file_name' => 'mpsoc/rtl/src_peripheral/ethmac/ethtop.v',`
152			`'custom_file_num' => 1,`
153			`'parameters_order' => [`
154			`'TX_FIFO_DATA_WIDTH',`
155			`'TX_FIFO_DEPTH',`
156			`'TX_FIFO_CNT_WIDTH',`
157			`'RX_FIFO_DATA_WIDTH',`
158			`'RX_FIFO_DEPTH',`
159			`'RX_FIFO_CNT_WIDTH'`
160			`],`
161			`'ip_name' => 'ethmac_100',`
162			`'description' => 'The Ethernet MAC 10/100 Mbps.`
163			`For more information please check: https://opencores.org/project,ethmac',`
164			`'ports' => {`
165			`'m_wb_adr_o' => {`
166			`'intfc_port' => 'adr_o',`
167			`'range' => '31:0',`
168			`'type' => 'output',`
169			`'intfc_name' => 'plug:wb_master[0]'`
170			`},`
171			`'wb_err_o' => {`
172			`'intfc_name' => 'plug:wb_slave[0]',`
173			`'range' => '',`
174			`'type' => 'output',`
175			`'intfc_port' => 'err_o'`
176			`},`
177			`'wb_we_i' => {`
178			`'range' => '',`
179			`'type' => 'input',`
180			`'intfc_name' => 'plug:wb_slave[0]',`
181			`'intfc_port' => 'we_i'`
182			`},`
183			`'m_wb_sel_o' => {`
184			`'intfc_name' => 'plug:wb_master[0]',`
185			`'range' => '3:0',`
186			`'type' => 'output',`
187			`'intfc_port' => 'sel_o'`
188			`},`
189			`'mrxdv_pad_i' => {`
190			`'range' => '',`
191			`'type' => 'input',`
192			`'intfc_name' => 'IO',`
193			`'intfc_port' => 'IO'`
194	38	alirezamon	`},`
195	48	alirezamon	`'int_o' => {`
196			`'intfc_port' => 'int_o',`
197			`'type' => 'output',`
198			`'range' => '',`
199			`'intfc_name' => 'plug:interrupt_peripheral[0]'`
200			`},`
201			`'m_wb_dat_i' => {`
202			`'intfc_port' => 'dat_i',`
203			`'type' => 'input',`
204			`'range' => '31:0',`
205			`'intfc_name' => 'plug:wb_master[0]'`
206			`},`
207			`'wb_clk_i' => {`
208			`'type' => 'input',`
209			`'range' => '',`
210			`'intfc_name' => 'plug:clk[0]',`
211			`'intfc_port' => 'clk_i'`
212			`},`
213			`'m_wb_ack_i' => {`
214			`'type' => 'input',`
215			`'range' => '',`
216			`'intfc_name' => 'plug:wb_master[0]',`
217			`'intfc_port' => 'ack_i'`
218			`},`
219			`'wb_rst_i' => {`
220			`'intfc_port' => 'reset_i',`
221			`'range' => '',`
222			`'type' => 'input',`
223			`'intfc_name' => 'plug:reset[0]'`
224			`},`
225			`'mrxd_pad_i' => {`
226	38	alirezamon	`'intfc_port' => 'IO',`
227	48	alirezamon	`'range' => '3:0',`
228			`'type' => 'input',`
229	38	alirezamon	`'intfc_name' => 'IO'`
230			`},`
231	48	alirezamon	`'mtxerr_pad_o' => {`
232	38	alirezamon	`'intfc_port' => 'IO',`
233	48	alirezamon	`'intfc_name' => 'IO',`
234	38	alirezamon	`'type' => 'output',`
235	48	alirezamon	`'range' => ''`
236	38	alirezamon	`},`
237	48	alirezamon	`'md_pad_o' => {`
238			`'intfc_port' => 'IO',`
239			`'intfc_name' => 'IO',`
240			`'type' => 'output',`
241			`'range' => ''`
242			`},`
243			`'wb_adr_i' => {`
244			`'intfc_port' => 'adr_i',`
245			`'intfc_name' => 'plug:wb_slave[0]',`
246			`'type' => 'input',`
247			`'range' => '9:0'`
248			`},`
249			`'wb_dat_o' => {`
250			`'intfc_port' => 'dat_o',`
251			`'intfc_name' => 'plug:wb_slave[0]',`
252			`'range' => '31:0',`
253			`'type' => 'output'`
254			`},`
255			`'m_wb_err_i' => {`
256			`'intfc_name' => 'plug:wb_master[0]',`
257			`'type' => 'input',`
258			`'range' => '',`
259			`'intfc_port' => 'err_i'`
260			`},`
261			`'mtxen_pad_o' => {`
262			`'intfc_port' => 'IO',`
263	38	alirezamon	`'intfc_name' => 'IO',`
264			`'range' => '',`
265	48	alirezamon	`'type' => 'output'`
266	38	alirezamon	`},`
267	48	alirezamon	`'mrxerr_pad_i' => {`
268			`'type' => 'input',`
269	38	alirezamon	`'range' => '',`
270			`'intfc_name' => 'IO',`
271	48	alirezamon	`'intfc_port' => 'IO'`
272	38	alirezamon	`},`
273	48	alirezamon	`'mtx_clk_pad_i' => {`
274			`'type' => 'input',`
275			`'range' => '',`
276			`'intfc_name' => 'IO',`
277			`'intfc_port' => 'IO'`
278			`},`
279			`'m_wb_stb_o' => {`
280			`'intfc_port' => 'stb_o',`
281			`'intfc_name' => 'plug:wb_master[0]',`
282			`'type' => 'output',`
283			`'range' => ''`
284			`},`
285			`'mcrs_pad_i' => {`
286			`'type' => 'input',`
287			`'range' => '',`
288			`'intfc_name' => 'IO',`
289			`'intfc_port' => 'IO'`
290			`},`
291			`'m_wb_dat_o' => {`
292			`'intfc_port' => 'dat_o',`
293			`'intfc_name' => 'plug:wb_master[0]',`
294			`'type' => 'output',`
295			`'range' => '31:0'`
296			`},`
297			`'m_wb_we_o' => {`
298			`'intfc_port' => 'we_o',`
299			`'range' => '',`
300	38	alirezamon	`'type' => 'output',`
301	48	alirezamon	`'intfc_name' => 'plug:wb_master[0]'`
302	38	alirezamon	`},`
303	48	alirezamon	`'mdc_pad_o' => {`
304	38	alirezamon	`'range' => '',`
305	48	alirezamon	`'type' => 'output',`
306			`'intfc_name' => 'IO',`
307			`'intfc_port' => 'IO'`
308	38	alirezamon	`},`
309	48	alirezamon	`'mtxd_pad_o' => {`
310			`'type' => 'output',`
311			`'range' => '3:0',`
312			`'intfc_name' => 'IO',`
313			`'intfc_port' => 'IO'`
314			`},`
315			`'wb_stb_i' => {`
316			`'intfc_port' => 'stb_i',`
317			`'intfc_name' => 'plug:wb_slave[0]',`
318			`'type' => 'input',`
319			`'range' => ''`
320			`},`
321			`'md_pad_i' => {`
322			`'intfc_name' => 'IO',`
323			`'range' => '',`
324			`'type' => 'input',`
325			`'intfc_port' => 'IO'`
326			`},`
327			`'wb_ack_o' => {`
328			`'range' => '',`
329			`'type' => 'output',`
330			`'intfc_name' => 'plug:wb_slave[0]',`
331			`'intfc_port' => 'ack_o'`
332			`},`
333			`'mcoll_pad_i' => {`
334	38	alirezamon	`'intfc_name' => 'IO',`
335			`'range' => '',`
336	48	alirezamon	`'type' => 'input',`
337	38	alirezamon	`'intfc_port' => 'IO'`
338			`},`
339	48	alirezamon	`'m_wb_cyc_o' => {`
340	38	alirezamon	`'range' => '',`
341			`'type' => 'output',`
342	48	alirezamon	`'intfc_name' => 'plug:wb_master[0]',`
343			`'intfc_port' => 'cyc_o'`
344	38	alirezamon	`},`
345	48	alirezamon	`'wb_cyc_i' => {`
346	38	alirezamon	`'intfc_name' => 'plug:wb_slave[0]',`
347			`'range' => '',`
348			`'type' => 'input',`
349	48	alirezamon	`'intfc_port' => 'cyc_i'`
350	38	alirezamon	`},`
351	48	alirezamon	`'wb_sel_i' => {`
352			`'intfc_port' => 'sel_i',`
353			`'intfc_name' => 'plug:wb_slave[0]',`
354			`'range' => '3:0',`
355			`'type' => 'input'`
356			`},`
357			`'wb_dat_i' => {`
358			`'intfc_port' => 'dat_i',`
359			`'intfc_name' => 'plug:wb_slave[0]',`
360			`'range' => '31:0',`
361			`'type' => 'input'`
362			`},`
363			`'md_padoe_o' => {`
364			`'intfc_name' => 'IO',`
365			`'type' => 'output',`
366			`'range' => '',`
367			`'intfc_port' => 'IO'`
368			`},`
369			`'mrx_clk_pad_i' => {`
370			`'intfc_port' => 'IO',`
371	38	alirezamon	`'intfc_name' => 'IO',`
372			`'range' => '',`
373	48	alirezamon	`'type' => 'input'`
374			`}`
375			`},`
376			`'module_name' => 'ethtop',`
377			`'unused' => {`
378			`'plug:wb_master[0]' => [`
379			`'tag_o',`
380			`'rty_i',`
381			`'bte_o',`
382			`'cti_o'`
383			`],`
384			`'plug:wb_slave[0]' => [`
385			`'cti_i',`
386			`'bte_i',`
387			`'rty_o',`
388			`'tag_i'`
389			`]`
390	38	alirezamon	`},`
391	48	alirezamon	`'hdl_files' => [`
392			`'/mpsoc/rtl/src_peripheral/ethmac'`
393			`],`
394			`'category' => 'Communication',`
395			`'modules' => {`
396			`'ethtop' => {}`
397			`},`
398			`'gui_status' => {`
399			`'status' => 'ideal',`
400			`'timeout' => 0`
401			`},`
402			`'ports_order' => [`
403			`'wb_clk_i',`
404			`'wb_rst_i',`
405			`'wb_dat_i',`
406			`'wb_dat_o',`
407			`'wb_adr_i',`
408			`'wb_sel_i',`
409			`'wb_we_i',`
410			`'wb_cyc_i',`
411			`'wb_stb_i',`
412			`'wb_ack_o',`
413			`'wb_err_o',`
414			`'m_wb_adr_o',`
415			`'m_wb_sel_o',`
416			`'m_wb_we_o',`
417			`'m_wb_dat_o',`
418			`'m_wb_dat_i',`
419			`'m_wb_cyc_o',`
420			`'m_wb_stb_o',`
421			`'m_wb_ack_i',`
422			`'m_wb_err_i',`
423			`'mtx_clk_pad_i',`
424			`'mtxd_pad_o',`
425			`'mtxen_pad_o',`
426			`'mtxerr_pad_o',`
427			`'mrx_clk_pad_i',`
428			`'mrxd_pad_i',`
429			`'mrxdv_pad_i',`
430			`'mrxerr_pad_i',`
431			`'mcoll_pad_i',`
432			`'mcrs_pad_i',`
433			`'mdc_pad_o',`
434			`'md_pad_i',`
435			`'md_pad_o',`
436			`'md_padoe_o',`
437			`'int_o'`
438			`],`
439			`'system_c' => 'void ${IP}_recv_ack(void)`
440			`{`
441			`${IP}_rx_done = 0;`
442			`${IP}_rx_len = 0;`
443			`//accept further data (reset RXBD to empty)`
444			`${IP}_RXBD0L = RX_READY; //len = 0 \| IRQ & WR = 1 \| EMPTY = 1`
445			`}`
446	38	alirezamon
447	48	alirezamon	`void ${IP}_init()`
448			`{`
449			`//TXEN & RXEN = 1; PAD & CRC = 1; FULLD = 1`
450			`${IP}_MODER = ETH_TXEN \| ETH_RXEN \| ETH_PAD \| ETH_CRCEN \| ETH_FULLD;`
451			`//PHY ADDR = 0x001`
452			`${IP}_MIIADDR = 0x00000001;`
453	38	alirezamon
454	48	alirezamon	`//enable all interrupts`
455			`${IP}_INT_MASK = ETH_RXB \| ETH_TXB;`
456	38	alirezamon
457	48	alirezamon	`//set MAC ADDR`
458			`${IP}_MAC_ADDR1 = (${IP}_MAC_ADDR_5 << 8) \| ${IP}_MAC_ADDR_4; //low word = mac ADDR high word`
459			`${IP}_MAC_ADDR0 = (${IP}_MAC_ADDR_3 << 24) \| (${IP}_MAC_ADDR_2 << 16)`
460			`\| (${IP}_MAC_ADDR_1 << 8) \| ${IP}_MAC_ADDR_0; //mac ADDR rest`
461	38	alirezamon
462	48	alirezamon	`//configure TXBD0`
463			`${IP}_TXBD0H = (unsigned long) ${IP}_tx_packet; //ADDR used for tx_data`
464			`${IP}_TXBD0L = TX_READY; //length = 0 \| PAD & CRC = 1 \| IRQ & WR = 1`
465
466			`//configure RXBD0`
467			`${IP}_RXBD0H = (unsigned long)${IP}_rx_packet; //ADDR used for tx_data`
468			`${IP}_RXBD0L = RX_READY; //len = 0 \| IRQ & WR = 1 \| EMPTY = 1`
469
470			`//set txdata`
471			`${IP}_tx_packet[0] = ${IP}_BROADCAST_ADDR_5;`
472			`${IP}_tx_packet[1] = ${IP}_BROADCAST_ADDR_4;`
473			`${IP}_tx_packet[2] = ${IP}_BROADCAST_ADDR_3;`
474			`${IP}_tx_packet[3] = ${IP}_BROADCAST_ADDR_2;`
475			`${IP}_tx_packet[4] = ${IP}_BROADCAST_ADDR_1;`
476			`${IP}_tx_packet[5] = ${IP}_BROADCAST_ADDR_0;`
477
478			`${IP}_tx_packet[6] = ${IP}_MAC_ADDR_5;`
479			`${IP}_tx_packet[7] = ${IP}_MAC_ADDR_4;`
480			`${IP}_tx_packet[8] = ${IP}_MAC_ADDR_3;`
481			`${IP}_tx_packet[9] = ${IP}_MAC_ADDR_2;`
482			`${IP}_tx_packet[10] = ${IP}_MAC_ADDR_1;`
483			`${IP}_tx_packet[11] = ${IP}_MAC_ADDR_0;`
484
485			`//erase interrupts`
486			`${IP}_INT_SOURCE = ETH_RXC \| ETH_TXC \| ETH_BUSY \| ETH_RXE \| ETH_RXB \| ETH_TXE \| ETH_TXB;`
487
488			`${IP}_tx_done = 1;`
489			`${IP}_rx_done = 0;`
490			`${IP}_rx_len = 0;`
491			`${IP}_tx_data = & ${IP}_tx_packet[HDR_LEN];`
492			`${IP}_rx_data = & ${IP}_rx_packet[HDR_LEN];`
493			`}`
494
495
496			`int ${IP}_send(int length)`
497			`{`
498			`if (!${IP}_tx_done) //if previous command not fully processed, bail out`
499			`return -1;`
500

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [Communication/] [ethmac_100.IP] - Blame information for rev 48