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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [Processor/] [lm32.IP] - Blame information for rev 25

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#######################################################################
##      File: lm32.IP
##
##      Copyright (C) 2014-2016  Alireza Monemi
##
##      This file is part of ProNoC 1.5.0
##
##      WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
##      MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################
 
$lm32 = bless( {
                 'hdl_files' => [
                                  '/mpsoc/src_processor/lm32/verilog/src/er1.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/JTAGB.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/jtag_lm32.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_adder.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_addsub.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_cpu.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_dcache.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_debug.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_decoder.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_functions.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_icache.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_include.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_instruction_unit.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_interrupt.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_jtag.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_load_store_unit.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_logic_op.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_mc_arithmetic.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_monitor.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_multiplier.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_ram.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_shifter.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_simtrace.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/lm32_top.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/spiprog.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/system_conf.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/typea.v',
                                  '/mpsoc/src_processor/lm32/verilog/src/typeb.v'
                                ],
                 'system_h' => '#include "lm32_system.h"
inline void nop (void) {
        asm volatile ("nop");
}',
                 'ip_name' => 'lm32',
                 'parameters_order' => [
                                         'INTR_NUM',
                                         'CFG_PL_MULTIPLY',
                                         'CFG_PL_BARREL_SHIFT',
                                         'CFG_SIGN_EXTEND',
                                         'CFG_MC_DIVIDE'
                                       ],
                 'ports_order' => [
                                    'clk_i',
                                    'rst_i',
                                    'en_i',
                                    'interrupt',
                                    'I_DAT_I',
                                    'I_ACK_I',
                                    'I_ERR_I',
                                    'I_RTY_I',
                                    'I_DAT_O',
                                    'I_ADR_O',
                                    'I_CYC_O',
                                    'I_SEL_O',
                                    'I_STB_O',
                                    'I_WE_O',
                                    'I_CTI_O',
                                    'I_BTE_O',
                                    'D_DAT_I',
                                    'D_ACK_I',
                                    'D_ERR_I',
                                    'D_RTY_I',
                                    'D_DAT_O',
                                    'D_ADR_O',
                                    'D_CYC_O',
                                    'D_SEL_O',
                                    'D_STB_O',
                                    'D_WE_O',
                                    'D_CTI_O',
                                    'D_BTE_O'
                                  ],
                 'sockets' => {
                                'interrupt_peripheral' => {
                                                            'interrupt_peripheral' => {},
                                                            'connection_num' => 'single connection',
                                                            'value' => 'INTR_NUM',
                                                            '0' => {
                                                                     'name' => 'interrupt_peripheral'
                                                                   },
                                                            'type' => 'param'
                                                          }
                              },
                 'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/lm32/verilog/src/lm32.v',
                 'module_name' => 'lm32',
                 'unused' => {
                               'plug:wb_master[1]' => [
                                                        'tag_o'
                                                      ],
                               'plug:wb_master[0]' => [
                                                        'tag_o'
                                                      ]
                             },
                 'category' => 'Processor',
                 'sw_files' => [
                                 '/mpsoc/src_processor/lm32/sw/crt0ram.S',
                                 '/mpsoc/src_processor/lm32/sw/linker.ld',
                                 '/mpsoc/src_processor/lm32/sw/lm32_system.h',
                                 '/mpsoc/src_processor/lm32/sw/Makefile',
                                 '/mpsoc/src_processor/lm32/sw/program',
                                 '/mpsoc/src_processor/program.sh'
                               ],
                 'description' => 'The LatticeMico32 is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensing agreement.
 
for more information vist: http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/LatticeMico32.aspx',
                 'gui_status' => {
                                   'timeout' => 0,
                                   'status' => 'ideal'
                                 },
                 'plugs' => {
                              'wb_master' => {
                                               'wb_master' => {},
                                               '1' => {
                                                        'name' => 'dwb'
                                                      },
                                               'value' => 2,
                                               '0' => {
                                                        'name' => 'iwb'
                                                      },
                                               'type' => 'num'
                                             },
                              'enable' => {
                                            'enable' => {},
                                            '0' => {
                                                     'name' => 'enable'
                                                   },
                                            'value' => 1,
                                            'type' => 'num'
                                          },
                              'reset' => {
                                           '1' => {
                                                    'name' => 'reset_1'
                                                  },
                                           'reset' => {},
                                           '0' => {
                                                    'name' => 'reset'
                                                  },
                                           'value' => 1,
                                           'type' => 'num'
                                         },
                              'clk' => {
                                         'clk' => {},
                                         '0' => {
                                                  'name' => 'clk'
                                                },
                                         'value' => 1,
                                         'type' => 'num'
                                       }
                            },
                 'modules' => {
                                'lm32' => {}
                              },
                 'parameters' => {
                                   'CFG_PL_BARREL_SHIFT' => {
                                                              'info' => undef,
                                                              'deafult' => '"ENABLED"',
                                                              'global_param' => 0,
                                                              'content' => '"ENABLED","DISABLED"',
                                                              'redefine_param' => 1,
                                                              'type' => 'Fixed'
                                                            },
                                   'CFG_SIGN_EXTEND' => {
                                                          'info' => undef,
                                                          'deafult' => '"ENABLED"',
                                                          'global_param' => 0,
                                                          'content' => '"ENABLED","DISABLED"',
                                                          'redefine_param' => 1,
                                                          'type' => 'Fixed'
                                                        },
                                   'CFG_PL_MULTIPLY' => {
                                                          'info' => undef,
                                                          'deafult' => '"ENABLED"',
                                                          'global_param' => 0,
                                                          'content' => '"ENABLED","DISABLED"',
                                                          'redefine_param' => 1,
                                                          'type' => 'Fixed'
                                                        },
                                   'INTR_NUM' => {
                                                   'info' => undef,
                                                   'deafult' => '32',
                                                   'global_param' => 0,
                                                   'content' => '',
                                                   'redefine_param' => 1,
                                                   'type' => 'Fixed'
                                                 },
                                   'CFG_MC_DIVIDE' => {
                                                        'info' => undef,
                                                        'deafult' => '"DISABLED"',
                                                        'global_param' => 0,
                                                        'content' => '"ENABLED","DISABLED"',
                                                        'redefine_param' => 1,
                                                        'type' => 'Fixed'
                                                      }
                                 },
                 'ports' => {
                              'I_SEL_O' => {
                                             'intfc_port' => 'sel_o',
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'range' => '(4-1):0',
                                             'type' => 'output'
                                           },
                              'I_DAT_I' => {
                                             'intfc_port' => 'dat_i',
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'range' => '(32-1):0',
                                             'type' => 'input'
                                           },
                              'I_CTI_O' => {
                                             'intfc_port' => 'cti_o',
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'range' => '(3-1):0',
                                             'type' => 'output'
                                           },
                              'D_WE_O' => {
                                            'intfc_port' => 'we_o',
                                            'intfc_name' => 'plug:wb_master[1]',
                                            'range' => '',
                                            'type' => 'output'
                                          },
                              'I_ERR_I' => {
                                             'intfc_port' => 'err_i',
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'range' => '',
                                             'type' => 'input'
                                           },
                              'D_ADR_O' => {
                                             'intfc_port' => 'adr_o',
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'range' => '(32-1):0',
                                             'type' => 'output'
                                           },
                              'D_CTI_O' => {
                                             'intfc_port' => 'cti_o',
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'range' => '(3-1):0',
                                             'type' => 'output'
                                           },
                              'D_STB_O' => {
                                             'intfc_port' => 'stb_o',
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'range' => '',
                                             'type' => 'output'
                                           },
                              'en_i' => {
                                          'intfc_port' => 'enable_i',
                                          'intfc_name' => 'plug:enable[0]',
                                          'range' => '',
                                          'type' => 'input'
                                        },
                              'I_CYC_O' => {
                                             'intfc_port' => 'cyc_o',
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'range' => '',
                                             'type' => 'output'
                                           },
                              'D_DAT_I' => {
                                             'intfc_port' => 'dat_i',
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'range' => '(32-1):0',
                                             'type' => 'input'
                                           },
                              'D_ACK_I' => {
                                             'intfc_port' => 'ack_i',
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'range' => '',
                                             'type' => 'input'
                                           },
                              'D_DAT_O' => {
                                             'intfc_port' => 'dat_o',
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'range' => '(32-1):0',
                                             'type' => 'output'
                                           },
                              'I_ADR_O' => {
                                             'intfc_port' => 'adr_o',
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'range' => '(32-1):0',
                                             'type' => 'output'
                                           },
                              'I_WE_O' => {
                                            'intfc_port' => 'we_o',
                                            'intfc_name' => 'plug:wb_master[0]',
                                            'range' => '',
                                            'type' => 'output'
                                          },
                              'I_BTE_O' => {
                                             'intfc_port' => 'bte_o',
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'range' => '(2-1):0',
                                             'type' => 'output'
                                           },
                              'rst_i' => {
                                           'intfc_port' => 'reset_i',
                                           'intfc_name' => 'plug:reset[0]',
                                           'range' => '',
                                           'type' => 'input'
                                         },
                              'interrupt' => {
                                               'intfc_port' => 'int_i',
                                               'intfc_name' => 'socket:interrupt_peripheral[array]',
                                               'range' => '(32-1):0',
                                               'type' => 'input'
                                             },
                              'D_BTE_O' => {
                                             'intfc_port' => 'bte_o',
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'range' => '(2-1):0',
                                             'type' => 'output'
                                           },
                              'D_CYC_O' => {
                                             'intfc_port' => 'cyc_o',
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'range' => '',
                                             'type' => 'output'
                                           },
                              'I_STB_O' => {
                                             'intfc_port' => 'stb_o',
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'range' => '',
                                             'type' => 'output'
                                           },
                              'D_SEL_O' => {
                                             'intfc_port' => 'sel_o',
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'range' => '(4-1):0',
                                             'type' => 'output'
                                           },
                              'I_DAT_O' => {
                                             'intfc_port' => 'dat_o',
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'range' => '(32-1):0',
                                             'type' => 'output'
                                           },
                              'D_ERR_I' => {
                                             'intfc_port' => 'err_i',
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'range' => '',
                                             'type' => 'input'
                                           },
                              'D_RTY_I' => {
                                             'intfc_port' => 'rty_i',
                                             'intfc_name' => 'plug:wb_master[1]',
                                             'range' => '',
                                             'type' => 'input'
                                           },
                              'I_ACK_I' => {
                                             'intfc_port' => 'ack_i',
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'range' => '',
                                             'type' => 'input'
                                           },
                              'I_RTY_I' => {
                                             'intfc_port' => 'rty_i',
                                             'intfc_name' => 'plug:wb_master[0]',
                                             'range' => '',
                                             'type' => 'input'
                                           },
                              'clk_i' => {
                                           'intfc_port' => 'clk_i',
                                           'intfc_name' => 'plug:clk[0]',
                                           'range' => '',
                                           'type' => 'input'
                                         }
                            }
               }, 'ip_gen' );

Line No.	Rev	Author	Line
1	25	alirezamon	`#######################################################################`
2			`## File: lm32.IP`
3			`##`
4			`## Copyright (C) 2014-2016 Alireza Monemi`
5			`##`
6			`## This file is part of ProNoC 1.5.0`
7			`##`
8			`## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT`
9			`## MAY CAUSE UNEXPECTED BEHAIVOR.`
10			`################################################################################`
11
12			`$lm32 = bless( {`
13			`'hdl_files' => [`
14			`'/mpsoc/src_processor/lm32/verilog/src/er1.v',`
15			`'/mpsoc/src_processor/lm32/verilog/src/JTAGB.v',`
16			`'/mpsoc/src_processor/lm32/verilog/src/jtag_lm32.v',`
17			`'/mpsoc/src_processor/lm32/verilog/src/lm32.v',`
18			`'/mpsoc/src_processor/lm32/verilog/src/lm32_adder.v',`
19			`'/mpsoc/src_processor/lm32/verilog/src/lm32_addsub.v',`
20			`'/mpsoc/src_processor/lm32/verilog/src/lm32_cpu.v',`
21			`'/mpsoc/src_processor/lm32/verilog/src/lm32_dcache.v',`
22			`'/mpsoc/src_processor/lm32/verilog/src/lm32_debug.v',`
23			`'/mpsoc/src_processor/lm32/verilog/src/lm32_decoder.v',`
24			`'/mpsoc/src_processor/lm32/verilog/src/lm32_functions.v',`
25			`'/mpsoc/src_processor/lm32/verilog/src/lm32_icache.v',`
26			`'/mpsoc/src_processor/lm32/verilog/src/lm32_include.v',`
27			`'/mpsoc/src_processor/lm32/verilog/src/lm32_instruction_unit.v',`
28			`'/mpsoc/src_processor/lm32/verilog/src/lm32_interrupt.v',`
29			`'/mpsoc/src_processor/lm32/verilog/src/lm32_jtag.v',`
30			`'/mpsoc/src_processor/lm32/verilog/src/lm32_load_store_unit.v',`
31			`'/mpsoc/src_processor/lm32/verilog/src/lm32_logic_op.v',`
32			`'/mpsoc/src_processor/lm32/verilog/src/lm32_mc_arithmetic.v',`
33			`'/mpsoc/src_processor/lm32/verilog/src/lm32_monitor.v',`
34			`'/mpsoc/src_processor/lm32/verilog/src/lm32_multiplier.v',`
35			`'/mpsoc/src_processor/lm32/verilog/src/lm32_ram.v',`
36			`'/mpsoc/src_processor/lm32/verilog/src/lm32_shifter.v',`
37			`'/mpsoc/src_processor/lm32/verilog/src/lm32_simtrace.v',`
38			`'/mpsoc/src_processor/lm32/verilog/src/lm32_top.v',`
39			`'/mpsoc/src_processor/lm32/verilog/src/spiprog.v',`
40			`'/mpsoc/src_processor/lm32/verilog/src/system_conf.v',`
41			`'/mpsoc/src_processor/lm32/verilog/src/typea.v',`
42			`'/mpsoc/src_processor/lm32/verilog/src/typeb.v'`
43			`],`
44			`'system_h' => '#include "lm32_system.h"`
45			`inline void nop (void) {`
46			`asm volatile ("nop");`
47			`}',`
48			`'ip_name' => 'lm32',`
49			`'parameters_order' => [`
50			`'INTR_NUM',`
51			`'CFG_PL_MULTIPLY',`
52			`'CFG_PL_BARREL_SHIFT',`
53			`'CFG_SIGN_EXTEND',`
54			`'CFG_MC_DIVIDE'`
55			`],`
56			`'ports_order' => [`
57			`'clk_i',`
58			`'rst_i',`
59			`'en_i',`
60			`'interrupt',`
61			`'I_DAT_I',`
62			`'I_ACK_I',`
63			`'I_ERR_I',`
64			`'I_RTY_I',`
65			`'I_DAT_O',`
66			`'I_ADR_O',`
67			`'I_CYC_O',`
68			`'I_SEL_O',`
69			`'I_STB_O',`
70			`'I_WE_O',`
71			`'I_CTI_O',`
72			`'I_BTE_O',`
73			`'D_DAT_I',`
74			`'D_ACK_I',`
75			`'D_ERR_I',`
76			`'D_RTY_I',`
77			`'D_DAT_O',`
78			`'D_ADR_O',`
79			`'D_CYC_O',`
80			`'D_SEL_O',`
81			`'D_STB_O',`
82			`'D_WE_O',`
83			`'D_CTI_O',`
84			`'D_BTE_O'`
85			`],`
86			`'sockets' => {`
87			`'interrupt_peripheral' => {`
88			`'interrupt_peripheral' => {},`
89			`'connection_num' => 'single connection',`
90			`'value' => 'INTR_NUM',`
91			`'0' => {`
92			`'name' => 'interrupt_peripheral'`
93			`},`
94			`'type' => 'param'`
95			`}`
96			`},`
97			`'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/lm32/verilog/src/lm32.v',`
98			`'module_name' => 'lm32',`
99			`'unused' => {`
100			`'plug:wb_master[1]' => [`
101			`'tag_o'`
102			`],`
103			`'plug:wb_master[0]' => [`
104			`'tag_o'`
105			`]`
106			`},`
107			`'category' => 'Processor',`
108			`'sw_files' => [`
109			`'/mpsoc/src_processor/lm32/sw/crt0ram.S',`
110			`'/mpsoc/src_processor/lm32/sw/linker.ld',`
111			`'/mpsoc/src_processor/lm32/sw/lm32_system.h',`
112			`'/mpsoc/src_processor/lm32/sw/Makefile',`
113			`'/mpsoc/src_processor/lm32/sw/program',`
114			`'/mpsoc/src_processor/program.sh'`
115			`],`
116			`'description' => 'The LatticeMico32 is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensing agreement.`
117
118			`for more information vist: http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/LatticeMico32.aspx',`
119			`'gui_status' => {`
120			`'timeout' => 0,`
121			`'status' => 'ideal'`
122			`},`
123			`'plugs' => {`
124			`'wb_master' => {`
125			`'wb_master' => {},`
126			`'1' => {`
127			`'name' => 'dwb'`
128			`},`
129			`'value' => 2,`
130			`'0' => {`
131			`'name' => 'iwb'`
132			`},`
133			`'type' => 'num'`
134			`},`
135			`'enable' => {`
136			`'enable' => {},`
137			`'0' => {`
138			`'name' => 'enable'`
139			`},`
140			`'value' => 1,`
141			`'type' => 'num'`
142			`},`
143			`'reset' => {`
144			`'1' => {`
145			`'name' => 'reset_1'`
146			`},`
147			`'reset' => {},`
148			`'0' => {`
149			`'name' => 'reset'`
150			`},`
151			`'value' => 1,`
152			`'type' => 'num'`
153			`},`
154			`'clk' => {`
155			`'clk' => {},`
156			`'0' => {`
157			`'name' => 'clk'`
158			`},`
159			`'value' => 1,`
160			`'type' => 'num'`
161			`}`
162			`},`
163			`'modules' => {`
164			`'lm32' => {}`
165			`},`
166			`'parameters' => {`
167			`'CFG_PL_BARREL_SHIFT' => {`
168			`'info' => undef,`
169			`'deafult' => '"ENABLED"',`
170			`'global_param' => 0,`
171			`'content' => '"ENABLED","DISABLED"',`
172			`'redefine_param' => 1,`
173			`'type' => 'Fixed'`
174			`},`
175			`'CFG_SIGN_EXTEND' => {`
176			`'info' => undef,`
177			`'deafult' => '"ENABLED"',`
178			`'global_param' => 0,`
179			`'content' => '"ENABLED","DISABLED"',`
180			`'redefine_param' => 1,`
181			`'type' => 'Fixed'`
182			`},`
183			`'CFG_PL_MULTIPLY' => {`
184			`'info' => undef,`
185			`'deafult' => '"ENABLED"',`
186			`'global_param' => 0,`
187			`'content' => '"ENABLED","DISABLED"',`
188			`'redefine_param' => 1,`
189			`'type' => 'Fixed'`
190			`},`
191			`'INTR_NUM' => {`
192			`'info' => undef,`
193			`'deafult' => '32',`
194			`'global_param' => 0,`
195			`'content' => '',`
196			`'redefine_param' => 1,`
197			`'type' => 'Fixed'`
198			`},`
199			`'CFG_MC_DIVIDE' => {`
200			`'info' => undef,`
201			`'deafult' => '"DISABLED"',`
202			`'global_param' => 0,`
203			`'content' => '"ENABLED","DISABLED"',`
204			`'redefine_param' => 1,`
205			`'type' => 'Fixed'`
206			`}`
207			`},`
208			`'ports' => {`
209			`'I_SEL_O' => {`
210			`'intfc_port' => 'sel_o',`
211			`'intfc_name' => 'plug:wb_master[0]',`
212			`'range' => '(4-1):0',`
213			`'type' => 'output'`
214			`},`
215			`'I_DAT_I' => {`
216			`'intfc_port' => 'dat_i',`
217			`'intfc_name' => 'plug:wb_master[0]',`
218			`'range' => '(32-1):0',`
219			`'type' => 'input'`
220			`},`
221			`'I_CTI_O' => {`
222			`'intfc_port' => 'cti_o',`
223			`'intfc_name' => 'plug:wb_master[0]',`
224			`'range' => '(3-1):0',`
225			`'type' => 'output'`
226			`},`
227			`'D_WE_O' => {`
228			`'intfc_port' => 'we_o',`
229			`'intfc_name' => 'plug:wb_master[1]',`
230			`'range' => '',`
231			`'type' => 'output'`
232			`},`
233			`'I_ERR_I' => {`
234			`'intfc_port' => 'err_i',`
235			`'intfc_name' => 'plug:wb_master[0]',`
236			`'range' => '',`
237			`'type' => 'input'`
238			`},`
239			`'D_ADR_O' => {`
240			`'intfc_port' => 'adr_o',`
241			`'intfc_name' => 'plug:wb_master[1]',`
242			`'range' => '(32-1):0',`
243			`'type' => 'output'`
244			`},`
245			`'D_CTI_O' => {`
246			`'intfc_port' => 'cti_o',`
247			`'intfc_name' => 'plug:wb_master[1]',`
248			`'range' => '(3-1):0',`
249			`'type' => 'output'`
250			`},`
251			`'D_STB_O' => {`
252			`'intfc_port' => 'stb_o',`
253			`'intfc_name' => 'plug:wb_master[1]',`
254			`'range' => '',`
255			`'type' => 'output'`
256			`},`
257			`'en_i' => {`
258			`'intfc_port' => 'enable_i',`
259			`'intfc_name' => 'plug:enable[0]',`
260			`'range' => '',`
261			`'type' => 'input'`
262			`},`
263			`'I_CYC_O' => {`
264			`'intfc_port' => 'cyc_o',`
265			`'intfc_name' => 'plug:wb_master[0]',`
266			`'range' => '',`
267			`'type' => 'output'`
268			`},`
269			`'D_DAT_I' => {`
270			`'intfc_port' => 'dat_i',`
271			`'intfc_name' => 'plug:wb_master[1]',`
272			`'range' => '(32-1):0',`
273			`'type' => 'input'`
274			`},`
275			`'D_ACK_I' => {`
276			`'intfc_port' => 'ack_i',`
277			`'intfc_name' => 'plug:wb_master[1]',`
278			`'range' => '',`
279			`'type' => 'input'`
280			`},`
281			`'D_DAT_O' => {`
282			`'intfc_port' => 'dat_o',`
283			`'intfc_name' => 'plug:wb_master[1]',`
284			`'range' => '(32-1):0',`
285			`'type' => 'output'`
286			`},`
287			`'I_ADR_O' => {`
288			`'intfc_port' => 'adr_o',`
289			`'intfc_name' => 'plug:wb_master[0]',`
290			`'range' => '(32-1):0',`
291			`'type' => 'output'`
292			`},`
293			`'I_WE_O' => {`
294			`'intfc_port' => 'we_o',`
295			`'intfc_name' => 'plug:wb_master[0]',`
296			`'range' => '',`
297			`'type' => 'output'`
298			`},`
299			`'I_BTE_O' => {`
300			`'intfc_port' => 'bte_o',`
301			`'intfc_name' => 'plug:wb_master[0]',`
302			`'range' => '(2-1):0',`
303			`'type' => 'output'`
304			`},`
305			`'rst_i' => {`
306			`'intfc_port' => 'reset_i',`
307			`'intfc_name' => 'plug:reset[0]',`
308			`'range' => '',`
309			`'type' => 'input'`
310			`},`
311			`'interrupt' => {`
312			`'intfc_port' => 'int_i',`
313			`'intfc_name' => 'socket:interrupt_peripheral[array]',`
314			`'range' => '(32-1):0',`
315			`'type' => 'input'`
316			`},`
317			`'D_BTE_O' => {`
318			`'intfc_port' => 'bte_o',`
319			`'intfc_name' => 'plug:wb_master[1]',`
320			`'range' => '(2-1):0',`
321			`'type' => 'output'`
322			`},`
323			`'D_CYC_O' => {`
324			`'intfc_port' => 'cyc_o',`
325			`'intfc_name' => 'plug:wb_master[1]',`
326			`'range' => '',`
327			`'type' => 'output'`
328			`},`
329			`'I_STB_O' => {`
330			`'intfc_port' => 'stb_o',`
331			`'intfc_name' => 'plug:wb_master[0]',`
332			`'range' => '',`
333			`'type' => 'output'`
334			`},`
335			`'D_SEL_O' => {`
336			`'intfc_port' => 'sel_o',`
337			`'intfc_name' => 'plug:wb_master[1]',`
338			`'range' => '(4-1):0',`
339			`'type' => 'output'`
340			`},`
341			`'I_DAT_O' => {`
342			`'intfc_port' => 'dat_o',`
343			`'intfc_name' => 'plug:wb_master[0]',`
344			`'range' => '(32-1):0',`
345			`'type' => 'output'`
346			`},`
347			`'D_ERR_I' => {`
348			`'intfc_port' => 'err_i',`
349			`'intfc_name' => 'plug:wb_master[1]',`
350			`'range' => '',`
351			`'type' => 'input'`
352			`},`
353			`'D_RTY_I' => {`
354			`'intfc_port' => 'rty_i',`
355			`'intfc_name' => 'plug:wb_master[1]',`
356			`'range' => '',`
357			`'type' => 'input'`
358			`},`
359			`'I_ACK_I' => {`
360			`'intfc_port' => 'ack_i',`
361			`'intfc_name' => 'plug:wb_master[0]',`
362			`'range' => '',`
363			`'type' => 'input'`
364			`},`
365			`'I_RTY_I' => {`
366			`'intfc_port' => 'rty_i',`
367			`'intfc_name' => 'plug:wb_master[0]',`
368			`'range' => '',`
369			`'type' => 'input'`
370			`},`
371			`'clk_i' => {`
372			`'intfc_port' => 'clk_i',`
373			`'intfc_name' => 'plug:clk[0]',`
374			`'range' => '',`
375			`'type' => 'input'`
376			`}`
377			`}`
378			`}, 'ip_gen' );`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [Processor/] [lm32.IP] - Blame information for rev 25