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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS.v,v 1.10 2009/08/21 23:55:43 harikr Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor : Xilinx
// \   \   \/     Version : 10.1
//  \   \         Description : Xilinx Functional Simulation Library Component
//  /   /                  Differential Signaling Input Clock Buffer
// /___/   /\     Filename : IBUFGDS.v
// \   \  /  \    Timestamp : Thu Mar 25 16:42:24 PST 2004
//  \___\/\___\
//
// Revision:
//    03/23/04 - Initial version.
//    05/23/07 - Changed timescale to 1 ps / 1 ps.
//    07/26/07 - Add else to handle x case for o_out (CR 424214).
//    07/16/08 - Added IBUF_LOW_PWR attribute.
//    03/19/09 - CR 511590 - Added Z condition handling.
//    04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE.
// End Revision
 
 
`timescale  1 ps / 1 ps
 
 
module IBUFGDS (O, I, IB);
 
    parameter CAPACITANCE = "DONT_CARE";
    parameter DIFF_TERM = "FALSE";
    parameter IBUF_DELAY_VALUE = "0";
    parameter IBUF_LOW_PWR = "TRUE";
    parameter IOSTANDARD = "DEFAULT";
 
    output O;
    input  I, IB;
 
    reg o_out;
 
    buf b_0 (O, o_out);
 
    initial begin
 
        case (CAPACITANCE)
 
            "LOW", "NORMAL", "DONT_CARE" : ;
            default : begin
                          $display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFGDS instance %m is set to %s.  Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
                          $finish;
                      end
 
        endcase
 
 
        case (DIFF_TERM)
 
            "TRUE", "FALSE" : ;
            default : begin
                          $display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFGDS instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
                          $finish;
                      end
 
        endcase
 
 
        case (IBUF_DELAY_VALUE)
 
            "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
            default : begin
                          $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFGDS instance %m is set to %s.  Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
                          $finish;
                      end
 
        endcase
 
        case (IBUF_LOW_PWR)
 
            "FALSE", "TRUE" : ;
            default : begin
                          $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
                          $finish;
                      end
 
        endcase
 
 
    end
 
    always @(I or IB) begin
        if (I == 1'b1 && IB == 1'b0)
            o_out <= I;
        else if (I == 1'b0 && IB == 1'b1)
            o_out <= I;
        else if (I == 1'bx || I == 1'bz || IB == 1'bx || IB == 1'bz)
            o_out <= 1'bx;
    end
 
endmodule

Line No.	Rev	Author	Line
1	48	alirezamon	`// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS.v,v 1.10 2009/08/21 23:55:43 harikr Exp $`
2			`///////////////////////////////////////////////////////////////////////////////`
3			`// Copyright (c) 1995/2004 Xilinx, Inc.`
4			`// All Right Reserved.`
5			`///////////////////////////////////////////////////////////////////////////////`
6			`// ____ ____`
7			`// / /\/ /`
8			`// /___/ \ / Vendor : Xilinx`
9			`// \ \ \/ Version : 10.1`
10			`// \ \ Description : Xilinx Functional Simulation Library Component`
11			`// / / Differential Signaling Input Clock Buffer`
12			`// /___/ /\ Filename : IBUFGDS.v`
13			`// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004`
14			`// \___\/\___\`
15			`//`
16			`// Revision:`
17			`// 03/23/04 - Initial version.`
18			`// 05/23/07 - Changed timescale to 1 ps / 1 ps.`
19			`// 07/26/07 - Add else to handle x case for o_out (CR 424214).`
20			`// 07/16/08 - Added IBUF_LOW_PWR attribute.`
21			`// 03/19/09 - CR 511590 - Added Z condition handling.`
22			`// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE.`
23			`// End Revision`
24
25
26			`timescale 1 ps / 1 ps
27
28
29			`module IBUFGDS (O, I, IB);`
30
31			`parameter CAPACITANCE = "DONT_CARE";`
32			`parameter DIFF_TERM = "FALSE";`
33			`parameter IBUF_DELAY_VALUE = "0";`
34			`parameter IBUF_LOW_PWR = "TRUE";`
35			`parameter IOSTANDARD = "DEFAULT";`
36
37			`output O;`
38			`input I, IB;`
39
40			`reg o_out;`
41
42			`buf b_0 (O, o_out);`
43
44			`initial begin`
45
46			`case (CAPACITANCE)`
47
48			`"LOW", "NORMAL", "DONT_CARE" : ;`
49			`default : begin`
50			`$display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFGDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);`
51			`$finish;`
52			`end`
53
54			`endcase`
55
56
57			`case (DIFF_TERM)`
58
59			`"TRUE", "FALSE" : ;`
60			`default : begin`
61			`$display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFGDS instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);`
62			`$finish;`
63			`end`
64
65			`endcase`
66
67
68			`case (IBUF_DELAY_VALUE)`
69
70			`"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;`
71			`default : begin`
72			`$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFGDS instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);`
73			`$finish;`
74			`end`
75
76			`endcase`
77
78			`case (IBUF_LOW_PWR)`
79
80			`"FALSE", "TRUE" : ;`
81			`default : begin`
82			`$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);`
83			`$finish;`
84			`end`
85
86			`endcase`
87
88
89			`end`
90
91			`always @(I or IB) begin`
92			`if (I == 1'b1 && IB == 1'b0)`
93			`o_out <= I;`
94			`else if (I == 1'b0 && IB == 1'b1)`
95			`o_out <= I;`
96			`else if (I == 1'bx \|\| I == 1'bz \|\| IB == 1'bx \|\| IB == 1'bz)`
97			`o_out <= 1'bx;`
98			`end`
99
100			`endmodule`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [verilog/] [IBUFGDS.v] - Blame information for rev 48