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alirezamon |
/**************************************
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* Module: xilinx_pll_base
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* Date:2020-03-18
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* Author: alireza
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*
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* Description:
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***************************************/
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module xilinx_pll_base #(
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parameter BANDWIDTH = "OPTIMIZED", // OPTIMIZED, HIGH, LOW
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parameter CLKFBOUT_MULT = 5, // Multiply value for all CLKOUT, (2-64)
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parameter CLKFBOUT_PHASE = 0.0, // Phase offset in degrees of CLKFB, (-360.000-360.000).
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parameter CLKIN1_PERIOD =0.0, // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
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// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
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parameter CLKOUT0_DIVIDE =1,
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parameter CLKOUT1_DIVIDE =1,
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parameter CLKOUT2_DIVIDE =1,
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parameter CLKOUT3_DIVIDE =1,
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parameter CLKOUT4_DIVIDE =1,
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parameter CLKOUT5_DIVIDE =1,
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// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
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parameter CLKOUT0_DUTY_CYCLE= 0.5,
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parameter CLKOUT1_DUTY_CYCLE=0.5,
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parameter CLKOUT2_DUTY_CYCLE=0.5,
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parameter CLKOUT3_DUTY_CYCLE=0.5,
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parameter CLKOUT4_DUTY_CYCLE=0.5,
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parameter CLKOUT5_DUTY_CYCLE=0.5,
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// CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
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parameter CLKOUT0_PHASE=0.0,
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parameter CLKOUT1_PHASE=0.0,
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parameter CLKOUT2_PHASE=0.0,
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parameter CLKOUT3_PHASE=0.0,
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parameter CLKOUT4_PHASE=0.0,
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parameter CLKOUT5_PHASE=0.0,
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parameter DIVCLK_DIVIDE=1, // Master division value, (1-56)
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parameter REF_JITTER1=0.0, // Reference input jitter in UI, (0.000-0.999).
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parameter STARTUP_WAIT="FALSE" // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
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)(
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// Clock Outputs: 1-bit (each) output: User configurable clock outputs
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output clk_out0, // 1-bit output: CLKOUT0
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output clk_out1, // 1-bit output: CLKOUT1
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output clk_out2, // 1-bit output: CLKOUT2
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output clk_out3, // 1-bit output: CLKOUT3
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output clk_out4, // 1-bit output: CLKOUT4
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output clk_out5, // 1-bit output: CLKOUT5
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// Feedback Clocks: 1-bit (each) output: Clock feedback ports
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// output CLKFBOUT, // 1-bit output: Feedback clock
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output reset_out, // 1-bit output: LOCK
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input clk_in, // 1-bit input: Input clock
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// Control Ports: 1-bit (each) input: PLL control ports
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// input PWRDWN, // 1-bit input: Power-down
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input reset_in // 1-bit input: Reset
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// Feedback Clocks: 1-bit (each) input: Clock feedback ports
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//input CLKFBIN // 1-bit input: Feedback clock
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);
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// Xilinx HDL Language Template, version 2019.1
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wire clk_feedback;
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wire locked;
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PLLE2_BASE #(
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.BANDWIDTH (BANDWIDTH ),
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.CLKFBOUT_MULT (CLKFBOUT_MULT ),
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.CLKFBOUT_PHASE (CLKFBOUT_PHASE ),
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.CLKIN1_PERIOD (CLKIN1_PERIOD ),
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.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE ),
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.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE ),
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.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE ),
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.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE ),
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.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE ),
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.CLKOUT5_DIVIDE (CLKOUT5_DIVIDE ),
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.CLKOUT0_DUTY_CYCLE (CLKOUT0_DUTY_CYCLE ),
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.CLKOUT1_DUTY_CYCLE (CLKOUT1_DUTY_CYCLE ),
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.CLKOUT2_DUTY_CYCLE (CLKOUT2_DUTY_CYCLE ),
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.CLKOUT3_DUTY_CYCLE (CLKOUT3_DUTY_CYCLE ),
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.CLKOUT4_DUTY_CYCLE (CLKOUT4_DUTY_CYCLE ),
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.CLKOUT5_DUTY_CYCLE (CLKOUT5_DUTY_CYCLE ),
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.CLKOUT0_PHASE (CLKOUT0_PHASE ),
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.CLKOUT1_PHASE (CLKOUT1_PHASE ),
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.CLKOUT2_PHASE (CLKOUT2_PHASE ),
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.CLKOUT3_PHASE (CLKOUT3_PHASE ),
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.CLKOUT4_PHASE (CLKOUT4_PHASE ),
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.CLKOUT5_PHASE (CLKOUT5_PHASE ),
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.DIVCLK_DIVIDE (DIVCLK_DIVIDE ),
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.REF_JITTER1 (REF_JITTER1 ),
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.STARTUP_WAIT (STARTUP_WAIT )
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)
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PLLE2_BASE_inst
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(
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// Clock Outputs: 1-bit (each) output: User configurable clock outputs
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.CLKOUT0(clk_out0), // 1-bit output: CLKOUT0
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.CLKOUT1(clk_out1), // 1-bit output: CLKOUT1
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.CLKOUT2(clk_out2), // 1-bit output: CLKOUT2
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.CLKOUT3(clk_out3), // 1-bit output: CLKOUT3
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.CLKOUT4(clk_out4), // 1-bit output: CLKOUT4
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.CLKOUT5(clk_out5), // 1-bit output: CLKOUT5
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// Feedback Clocks: 1-bit (each) output: Clock feedback ports
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.CLKFBOUT(clk_feedback), // 1-bit output: Feedback clock
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.LOCKED(locked), // 1-bit output: LOCK
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.CLKIN1(clk_in), // 1-bit input: Input clock
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// Control Ports: 1-bit (each) input: PLL control ports
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.PWRDWN(1'b0), // 1-bit input: Power-down
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.RST(reset_in), // 1-bit input: Reset
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// Feedback Clocks: 1-bit (each) input: Clock feedback ports
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.CLKFBIN(clk_feedback) // 1-bit input: Feedback clock
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);
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assign reset_out =~locked;
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endmodule
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