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alirezamon |
/*
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* pll.v: Simulates the pll of the xilinx 7 series. This is used by the
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* frontend files "plle2_base.v" and "plle2_adv.v"
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* author: Till Mahlburg
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* year: 2019-2020
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* organization: Universität Leipzig
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* license: ISC
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*
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*/
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// synthesis translate_off
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`timescale 1 ns / 1 ps
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/* A reference for the interface can be found in Xilinx UG953 page 503ff */
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module plle2_base_sim #(
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/* not implemented */
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parameter BANDWIDTH = "OPTIMIZED",
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parameter CLKFBOUT_MULT_F = 5.0,
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parameter CLKFBOUT_PHASE = 0.0,
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/* need to be set */
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parameter CLKIN1_PERIOD = 0.0,
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parameter CLKIN2_PERIOD = 0.0,
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parameter CLKOUT0_DIVIDE_F = 1.0,
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parameter CLKOUT1_DIVIDE = 1,
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parameter CLKOUT2_DIVIDE = 1,
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parameter CLKOUT3_DIVIDE = 1,
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parameter CLKOUT4_DIVIDE = 1,
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parameter CLKOUT5_DIVIDE = 1,
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parameter CLKOUT6_DIVIDE = 1,
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parameter CLKOUT0_DUTY_CYCLE = 0.5,
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parameter CLKOUT1_DUTY_CYCLE = 0.5,
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parameter CLKOUT2_DUTY_CYCLE = 0.5,
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parameter CLKOUT3_DUTY_CYCLE = 0.5,
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parameter CLKOUT4_DUTY_CYCLE = 0.5,
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parameter CLKOUT5_DUTY_CYCLE = 0.5,
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parameter CLKOUT6_DUTY_CYCLE = 0.5,
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parameter CLKOUT0_PHASE = 0.0,
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parameter CLKOUT1_PHASE = 0.0,
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parameter CLKOUT2_PHASE = 0.0,
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parameter CLKOUT3_PHASE = 0.0,
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parameter CLKOUT4_PHASE = 0.0,
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parameter CLKOUT5_PHASE = 0.0,
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parameter CLKOUT6_PHASE = 0.0,
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parameter CLKOUT4_CASCADE = "FALSE",
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parameter DIVCLK_DIVIDE = 1,
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/* not implemented */
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parameter REF_JITTER1 = 0.010,
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parameter REF_JITTER2 = 0.010,
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parameter STARTUP_WAIT = "FALSE",
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parameter COMPENSATION = "ZHOLD",
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/* this is additional, optional information for determining the
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* correct hardware limits. By default it uses the most restrictive
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* model */
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parameter FPGA_TYPE = "ARTIX",
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parameter SPEED_GRADE = "-1",
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/* just for internal use */
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parameter MODULE_TYPE = "PLLE2_BASE")(
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output CLKOUT0,
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output CLKOUT0B,
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output CLKOUT1,
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output CLKOUT1B,
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output CLKOUT2,
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output CLKOUT2B,
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output CLKOUT3,
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output CLKOUT3B,
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output CLKOUT4,
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output CLKOUT5,
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output CLKOUT6,
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/* PLL feedback output. */
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output CLKFBOUT,
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output CLKFBOUTB,
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output LOCKED,
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input CLKIN1,
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input CLKIN2,
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/* Select input clk. 1 for CLKIN1, 0 for CLKIN2 */
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input CLKINSEL,
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/* PLL feedback input. Is ignored in this implementation, but should be connected to CLKFBOUT for internal feedback. */
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input CLKFBIN,
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/* Used to power down instatiated but unused PLLs */
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input PWRDWN,
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input RST,
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/* Dynamic reconfiguration ports */
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/* register address to write to or read from */
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input [6:0] DADDR,
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/* reference clk */
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input DCLK,
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/* enable dynamic reconfiguration (read only) */
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input DEN,
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/* enable writing */
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input DWE,
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/* what to write */
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input [15:0] DI,
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/* read values */
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output [15:0] DO,
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/* ready flag for next operation */
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output DRDY);
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/* assign inverted outputs */
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assign CLKOUT0B = ~CLKOUT0;
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assign CLKOUT1B = ~CLKOUT1;
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assign CLKOUT2B = ~CLKOUT2;
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assign CLKOUT3B = ~CLKOUT3;
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assign CLKFBOUTB = ~CLKFBOUT;
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/* gets assigned to the chosen CLKIN */
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reg clkin;
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wire [31:0] clkin_period_length_1000;
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/* internal values */
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reg [31:0] CLKOUT_DIVIDE_INT_1000[0:6];
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reg [31:0] CLKOUT_DUTY_CYCLE_INT_1000[0:6];
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reg signed [31:0] CLKOUT_PHASE_INT_1000[0:6];
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reg [31:0] CLKFBOUT_MULT_F_INT_1000;
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reg signed [31:0] CLKFBOUT_PHASE_INT_1000;
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reg [31:0] DIVCLK_DIVIDE_INT;
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wire CLKOUT_INT[0:6];
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assign CLKOUT0 = CLKOUT_INT[0];
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assign CLKOUT1 = CLKOUT_INT[1];
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assign CLKOUT2 = CLKOUT_INT[2];
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assign CLKOUT3 = CLKOUT_INT[3];
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assign CLKOUT4 = CLKOUT_INT[4];
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assign CLKOUT5 = CLKOUT_INT[5];
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assign CLKOUT6 = CLKOUT_INT[6];
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/* Used to determine the period length of the divided CLK */
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period_count #(
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.RESOLUTION(0.01))
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period_count (
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.RST(RST),
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.PWRDWN(PWRDWN),
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.clk(clkin),
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.period_length_1000(clkin_period_length_1000));
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wire period_stable;
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/* Used to delay the output of the period until it's stable */
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period_check period_check (
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.RST(RST),
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.PWRDWN(PWRDWN),
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.clk(clkin),
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.period_length((clkin_period_length_1000 / 1000.0)),
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.period_stable(period_stable));
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wire out[0:6];
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wire [31:0] out_period_length_1000[0:6];
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wire lock[0:6];
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/* frequency generators */
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genvar i;
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generate
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for (i = 0; i <= 6; i = i + 1) begin : fg
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freq_gen fg (
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.M_1000(CLKFBOUT_MULT_F_INT_1000),
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.D(DIVCLK_DIVIDE_INT),
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.O_1000(CLKOUT_DIVIDE_INT_1000[i]),
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.RST(RST),
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.PWRDWN(PWRDWN),
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.period_stable(period_stable),
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.ref_period_1000((clkin_period_length_1000)),
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.clk(clkin),
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.out(out[i]),
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.out_period_length_1000(out_period_length_1000[i]));
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end
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endgenerate
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/* phase shift */
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generate
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for (i = 0; i <= 6; i = i + 1) begin : ps
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phase_shift ps (
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.RST(RST),
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.PWRDWN(PWRDWN),
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.clk(out[i]),
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.shift_1000(CLKOUT_PHASE_INT_1000[i] + CLKFBOUT_PHASE_INT_1000),
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.duty_cycle(CLKOUT_DUTY_CYCLE_INT_1000[i] / 10),
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.clk_period_1000(out_period_length_1000[i]),
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.lock(lock[i]),
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.clk_shifted(CLKOUT_INT[i]));
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end
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endgenerate
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wire fb_out;
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wire [31:0] fb_out_period_length_1000;
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wire fb_lock;
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/* CLKOUTFB */
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freq_gen fb_fg (
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.M_1000(CLKFBOUT_MULT_F_INT_1000),
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.D(DIVCLK_DIVIDE_INT),
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.O_1000(1000.0),
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.RST(RST),
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.PWRDWN(PWRDWN),
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.period_stable(period_stable),
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.ref_period_1000((clkin_period_length_1000)),
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.clk(clkin),
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.out(fb_out),
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.out_period_length_1000(fb_out_period_length_1000));
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phase_shift fb_ps (
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.RST(RST),
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.PWRDWN(PWRDWN),
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.clk(fb_out),
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.shift_1000(CLKFBOUT_PHASE_INT_1000),
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.clk_period_1000(fb_out_period_length_1000),
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.duty_cycle(50),
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.lock(fb_lock),
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.clk_shifted(CLKFBOUT));
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/* dynamically set values */
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wire [31:0] CLKOUT_DIVIDE_DYN[0:6];
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wire [31:0] CLKOUT_DUTY_CYCLE_DYN_1000[0:6];
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wire signed [31:0] CLKOUT_PHASE_DYN[0:6];
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wire [31:0] CLKFBOUT_MULT_F_DYN_1000;
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wire signed [31:0] CLKFBOUT_PHASE_DYN;
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wire [31:0] DIVCLK_DIVIDE_DYN;
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/* reconfiguration */
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dyn_reconf dyn_reconf (
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.RST(RST),
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.PWRDWN(PWRDWN),
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.vco_period_1000(fb_out_period_length_1000),
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.DADDR(DADDR),
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.DCLK(DCLK),
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.DEN(DEN),
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.DWE(DWE),
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.DI(DI),
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.DO(DO),
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.DRDY(DRDY),
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.CLKOUT0_DIVIDE(CLKOUT_DIVIDE_DYN[0]),
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.CLKOUT0_DUTY_CYCLE_1000(CLKOUT_DUTY_CYCLE_DYN_1000[0]),
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.CLKOUT0_PHASE(CLKOUT_PHASE_DYN[0]),
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.CLKOUT1_DIVIDE(CLKOUT_DIVIDE_DYN[1]),
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.CLKOUT1_DUTY_CYCLE_1000(CLKOUT_DUTY_CYCLE_DYN_1000[1]),
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.CLKOUT1_PHASE(CLKOUT_PHASE_DYN[1]),
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.CLKOUT2_DIVIDE(CLKOUT_DIVIDE_DYN[2]),
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.CLKOUT2_DUTY_CYCLE_1000(CLKOUT_DUTY_CYCLE_DYN_1000[2]),
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.CLKOUT2_PHASE(CLKOUT_PHASE_DYN[2]),
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.CLKOUT3_DIVIDE(CLKOUT_DIVIDE_DYN[3]),
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.CLKOUT3_DUTY_CYCLE_1000(CLKOUT_DUTY_CYCLE_DYN_1000[3]),
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.CLKOUT3_PHASE(CLKOUT_PHASE_DYN[3]),
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.CLKOUT4_DIVIDE(CLKOUT_DIVIDE_DYN[4]),
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.CLKOUT4_DUTY_CYCLE_1000(CLKOUT_DUTY_CYCLE_DYN_1000[4]),
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.CLKOUT4_PHASE(CLKOUT_PHASE_DYN[4]),
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.CLKOUT5_DIVIDE(CLKOUT_DIVIDE_DYN[5]),
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.CLKOUT5_DUTY_CYCLE_1000(CLKOUT_DUTY_CYCLE_DYN_1000[5]),
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.CLKOUT5_PHASE(CLKOUT_PHASE_DYN[5]),
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.CLKOUT6_DIVIDE(CLKOUT_DIVIDE_DYN[6]),
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.CLKOUT6_DUTY_CYCLE_1000(CLKOUT_DUTY_CYCLE_DYN_1000[6]),
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.CLKOUT6_PHASE(CLKOUT_PHASE_DYN[6]),
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.CLKFBOUT_MULT_F_1000(CLKFBOUT_MULT_F_DYN_1000),
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.CLKFBOUT_PHASE(CLKFBOUT_PHASE_DYN),
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.DIVCLK_DIVIDE(DIVCLK_DIVIDE_DYN));
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/* lock detection using the lock information given by the phase shift modules */
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assign LOCKED = lock[0] & lock[1] & lock[2] & lock[3] & lock[4] & lock[5] & lock[6] & fb_lock;
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/* set clkin to the correct CLKIN */
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always @* begin
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if (CLKINSEL === 1'b1) begin
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clkin = CLKIN1;
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end else if (CLKINSEL === 1'b0) begin
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clkin = CLKIN2;
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end
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end
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| 294 |
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integer k;
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| 295 |
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/* set the internal values to the dynamically set */
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| 296 |
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always @* begin
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for (k = 0; k <= 6; k = k + 1) begin
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if (CLKOUT_DIVIDE_DYN[k] != 0)
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CLKOUT_DIVIDE_INT_1000[k] = CLKOUT_DIVIDE_DYN[k] * 1000;
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if (CLKOUT_DUTY_CYCLE_DYN_1000[k] != 0)
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CLKOUT_DUTY_CYCLE_INT_1000[k] = CLKOUT_DUTY_CYCLE_DYN_1000[k];
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if (CLKOUT_PHASE_DYN[k] != 0)
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CLKOUT_PHASE_INT_1000[k] = CLKOUT_PHASE_DYN[k] * 1000;
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end
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if (CLKFBOUT_MULT_F_DYN_1000 != 0)
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CLKFBOUT_MULT_F_INT_1000 = CLKFBOUT_MULT_F_DYN_1000;
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if (CLKFBOUT_PHASE_DYN != 0)
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CLKFBOUT_PHASE_INT_1000 = CLKFBOUT_PHASE_DYN * 1000;
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if (DIVCLK_DIVIDE_DYN != 0)
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DIVCLK_DIVIDE_INT = DIVCLK_DIVIDE_DYN;
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end
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/* assign initial values */
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| 314 |
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integer vco_min;
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| 315 |
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integer vco_max;
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| 316 |
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initial begin
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CLKOUT_DIVIDE_INT_1000[0] = CLKOUT0_DIVIDE_F * 1000;
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| 318 |
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CLKOUT_DIVIDE_INT_1000[1] = CLKOUT1_DIVIDE * 1000;
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|
|
CLKOUT_DIVIDE_INT_1000[2] = CLKOUT2_DIVIDE * 1000;
|
| 320 |
|
|
CLKOUT_DIVIDE_INT_1000[3] = CLKOUT3_DIVIDE * 1000;
|
| 321 |
|
|
if (CLKOUT4_CASCADE == "FALSE") begin
|
| 322 |
|
|
CLKOUT_DIVIDE_INT_1000[4] = CLKOUT4_DIVIDE * 1000;
|
| 323 |
|
|
CLKOUT_DIVIDE_INT_1000[6] = CLKOUT6_DIVIDE * 1000;
|
| 324 |
|
|
end else if (CLKOUT4_CASCADE == "TRUE") begin
|
| 325 |
|
|
CLKOUT_DIVIDE_INT_1000[4] = CLKOUT4_DIVIDE * CLKOUT6_DIVIDE * 1000;
|
| 326 |
|
|
CLKOUT_DIVIDE_INT_1000[6] = 1000;
|
| 327 |
|
|
end
|
| 328 |
|
|
CLKOUT_DIVIDE_INT_1000[5] = CLKOUT5_DIVIDE * 1000;
|
| 329 |
|
|
|
| 330 |
|
|
CLKOUT_DUTY_CYCLE_INT_1000[0] = CLKOUT0_DUTY_CYCLE * 1000;
|
| 331 |
|
|
CLKOUT_DUTY_CYCLE_INT_1000[1] = CLKOUT1_DUTY_CYCLE * 1000;
|
| 332 |
|
|
CLKOUT_DUTY_CYCLE_INT_1000[2] = CLKOUT2_DUTY_CYCLE * 1000;
|
| 333 |
|
|
CLKOUT_DUTY_CYCLE_INT_1000[3] = CLKOUT3_DUTY_CYCLE * 1000;
|
| 334 |
|
|
CLKOUT_DUTY_CYCLE_INT_1000[4] = CLKOUT4_DUTY_CYCLE * 1000;
|
| 335 |
|
|
CLKOUT_DUTY_CYCLE_INT_1000[5] = CLKOUT5_DUTY_CYCLE * 1000;
|
| 336 |
|
|
CLKOUT_DUTY_CYCLE_INT_1000[6] = CLKOUT6_DUTY_CYCLE * 1000;
|
| 337 |
|
|
|
| 338 |
|
|
CLKOUT_PHASE_INT_1000[0] = CLKOUT0_PHASE * 1000;
|
| 339 |
|
|
CLKOUT_PHASE_INT_1000[1] = CLKOUT1_PHASE * 1000;
|
| 340 |
|
|
CLKOUT_PHASE_INT_1000[2] = CLKOUT2_PHASE * 1000;
|
| 341 |
|
|
CLKOUT_PHASE_INT_1000[3] = CLKOUT3_PHASE * 1000;
|
| 342 |
|
|
CLKOUT_PHASE_INT_1000[4] = CLKOUT4_PHASE * 1000;
|
| 343 |
|
|
CLKOUT_PHASE_INT_1000[5] = CLKOUT5_PHASE * 1000;
|
| 344 |
|
|
CLKOUT_PHASE_INT_1000[6] = CLKOUT6_PHASE * 1000;
|
| 345 |
|
|
|
| 346 |
|
|
CLKFBOUT_MULT_F_INT_1000 = CLKFBOUT_MULT_F * 1000;
|
| 347 |
|
|
CLKFBOUT_PHASE_INT_1000 = CLKFBOUT_PHASE * 1000;
|
| 348 |
|
|
DIVCLK_DIVIDE_INT = DIVCLK_DIVIDE;
|
| 349 |
|
|
|
| 350 |
|
|
/* set up limits correctly */
|
| 351 |
|
|
case (FPGA_TYPE)
|
| 352 |
|
|
"ARTIX":
|
| 353 |
|
|
case (SPEED_GRADE)
|
| 354 |
|
|
"-3": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
|
| 355 |
|
|
vco_min = 800;
|
| 356 |
|
|
vco_max = 2133;
|
| 357 |
|
|
end else if (MODULE_TYPE == "MMCME2_BASE") begin
|
| 358 |
|
|
vco_min = 600;
|
| 359 |
|
|
vco_max = 1600;
|
| 360 |
|
|
end
|
| 361 |
|
|
"-2": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
|
| 362 |
|
|
vco_min = 800;
|
| 363 |
|
|
vco_max = 1866;
|
| 364 |
|
|
end else if (MODULE_TYPE == "MMCME2_BASE") begin
|
| 365 |
|
|
vco_min = 600;
|
| 366 |
|
|
vco_max = 1440;
|
| 367 |
|
|
end
|
| 368 |
|
|
"-1", "-1LI", "-2LE": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
|
| 369 |
|
|
vco_min = 800;
|
| 370 |
|
|
vco_max = 1600;
|
| 371 |
|
|
end else if (MODULE_TYPE == "MMCME2_BASE") begin
|
| 372 |
|
|
vco_min = 600;
|
| 373 |
|
|
vco_max = 1200;
|
| 374 |
|
|
end
|
| 375 |
|
|
default: begin
|
| 376 |
|
|
$display("The speed grade given is not valid. Please choose one of the following: -3, -2, -2LE, -1, -1LI");
|
| 377 |
|
|
$display("Exiting simulation...");
|
| 378 |
|
|
$finish;
|
| 379 |
|
|
end
|
| 380 |
|
|
endcase
|
| 381 |
|
|
"KINTEX":
|
| 382 |
|
|
case (SPEED_GRADE)
|
| 383 |
|
|
"-3": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
|
| 384 |
|
|
vco_min = 800;
|
| 385 |
|
|
vco_max = 2133;
|
| 386 |
|
|
end else if (MODULE_TYPE == "MMCME2_BASE") begin
|
| 387 |
|
|
vco_min = 600;
|
| 388 |
|
|
vco_max = 1600;
|
| 389 |
|
|
end
|
| 390 |
|
|
"-2", "-2LI": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
|
| 391 |
|
|
vco_min = 800;
|
| 392 |
|
|
vco_max = 1866;
|
| 393 |
|
|
end else if (MODULE_TYPE == "MMCME2_BASE") begin
|
| 394 |
|
|
vco_min = 600;
|
| 395 |
|
|
vco_max = 1440;
|
| 396 |
|
|
end
|
| 397 |
|
|
"-1", "-1M", "-1LM", "-1Q", "-2LE": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
|
| 398 |
|
|
vco_min = 800;
|
| 399 |
|
|
vco_max = 1600;
|
| 400 |
|
|
end else if (MODULE_TYPE == "MMCME2_BASE") begin
|
| 401 |
|
|
vco_min = 600;
|
| 402 |
|
|
vco_max = 1200;
|
| 403 |
|
|
end
|
| 404 |
|
|
default: begin
|
| 405 |
|
|
$display("The speed grade given is not valid. Please choose one of the following: -3, -2, -2LI, -2LE, -1, -1M, -1LM, -1Q");
|
| 406 |
|
|
$display("Exiting simulation...");
|
| 407 |
|
|
$finish;
|
| 408 |
|
|
end
|
| 409 |
|
|
endcase
|
| 410 |
|
|
"VIRTEX":
|
| 411 |
|
|
case (SPEED_GRADE)
|
| 412 |
|
|
"-3": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
|
| 413 |
|
|
vco_min = 800;
|
| 414 |
|
|
vco_max = 2133;
|
| 415 |
|
|
end else if (MODULE_TYPE == "MMCME2_BASE") begin
|
| 416 |
|
|
vco_min = 600;
|
| 417 |
|
|
vco_max = 1600;
|
| 418 |
|
|
end
|
| 419 |
|
|
"-2", "-2L", "-2LG": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
|
| 420 |
|
|
vco_min = 800;
|
| 421 |
|
|
vco_max = 1833;
|
| 422 |
|
|
end else if (MODULE_TYPE == "MMCME2_BASE") begin
|
| 423 |
|
|
vco_min = 600;
|
| 424 |
|
|
vco_max = 1440;
|
| 425 |
|
|
end
|
| 426 |
|
|
"-1", "-1M": if (MODULE_TYPE == "PLLE2_ADV" || MODULE_TYPE == "PLLE2_BASE") begin
|
| 427 |
|
|
vco_min = 800;
|
| 428 |
|
|
vco_max = 1600;
|
| 429 |
|
|
end else if (MODULE_TYPE == "MMCME2_BASE") begin
|
| 430 |
|
|
vco_min = 600;
|
| 431 |
|
|
vco_max = 1200;
|
| 432 |
|
|
end
|
| 433 |
|
|
default: begin
|
| 434 |
|
|
$display("The speed grade given is not valid. Please choose one of the following: -3, -2, -2L, -2LG, -1, -1M");
|
| 435 |
|
|
$display("Exiting simulation...");
|
| 436 |
|
|
$finish;
|
| 437 |
|
|
end
|
| 438 |
|
|
endcase
|
| 439 |
|
|
default: begin
|
| 440 |
|
|
$display("The FPGA type given is not recognized. Please choose one of the following: ARTIX, VIRTEX, KINTEX");
|
| 441 |
|
|
$display("Exiting simulation...");
|
| 442 |
|
|
$finish;
|
| 443 |
|
|
end
|
| 444 |
|
|
endcase
|
| 445 |
|
|
end
|
| 446 |
|
|
|
| 447 |
|
|
integer l;
|
| 448 |
|
|
reg invalid = 1'b0;
|
| 449 |
|
|
/* check values for validity */
|
| 450 |
|
|
always @(*) begin
|
| 451 |
|
|
/* the same for each version of the pll/mmcm */
|
| 452 |
|
|
if (!(BANDWIDTH == "OPTIMIZED" || BANDWIDTH == "HIGH" || BANDWIDTH == "LOW")) begin
|
| 453 |
|
|
$display("BANDWIDTH doesn't match any of its allowed inputs.");
|
| 454 |
|
|
invalid = 1'b1;
|
| 455 |
|
|
end else if (CLKIN1_PERIOD < 0.000 || CLKIN1_PERIOD > 52.631) begin
|
| 456 |
|
|
$display("CLKIN1_PERIOD is not in the allowed range (0 - 52.631).");
|
| 457 |
|
|
invalid = 1'b1;
|
| 458 |
|
|
end else if (CLKIN2_PERIOD < 0.000 || CLKIN2_PERIOD > 52.631) begin
|
| 459 |
|
|
$display("CLKIN2_PERIOD is not in the allowed range (0 - 52.631).");
|
| 460 |
|
|
invalid = 1'b1;
|
| 461 |
|
|
end else if (CLKFBOUT_PHASE_INT_1000 < -360000 || CLKFBOUT_PHASE_INT_1000 > 360000) begin
|
| 462 |
|
|
$display("CLKFBOUT_PHASE is not in the allowed range (-360-360).");
|
| 463 |
|
|
invalid = 1'b1;
|
| 464 |
|
|
end else if (DIVCLK_DIVIDE_INT < 1 || DIVCLK_DIVIDE_INT > 56) begin
|
| 465 |
|
|
$display("DIVCLK_DIVIDE is not in the allowed range (1-56).");
|
| 466 |
|
|
invalid = 1'b1;
|
| 467 |
|
|
end else if (REF_JITTER1 < 0.000 || REF_JITTER1 > 0.999) begin
|
| 468 |
|
|
$display("REF_JITTER1 is not in the allowed range (0.000 - 0.999).");
|
| 469 |
|
|
invalid = 1'b1;
|
| 470 |
|
|
end else if (REF_JITTER2 < 0.000 || REF_JITTER2 > 0.999) begin
|
| 471 |
|
|
$display("REF_JITTER2 is not in the allowed range (0.000 - 0.999).");
|
| 472 |
|
|
invalid = 1'b1;
|
| 473 |
|
|
end else if (!(STARTUP_WAIT == "FALSE" || STARTUP_WAIT == "TRUE")) begin
|
| 474 |
|
|
$display("STARTUP_WAIT doesn't match any of its allowed inputs");
|
| 475 |
|
|
invalid = 1'b1;
|
| 476 |
|
|
end else if (!(COMPENSATION == "ZHOLD" || COMPENSATION == "BUF_IN" || COMPENSATION == "EXTERNAL" || COMPENSATION == "INTERNAL")) begin
|
| 477 |
|
|
$display("COMPENSATION doesn't match any of its allowed inputs");
|
| 478 |
|
|
invalid = 1'b1;
|
| 479 |
|
|
end else if (!(CLKOUT4_CASCADE == "TRUE" || CLKOUT4_CASCADE == "FALSE")) begin
|
| 480 |
|
|
$display("CLKOUT4_CASCADE doesn't match any of its allowed inputs");
|
| 481 |
|
|
invalid = 1'b1;
|
| 482 |
|
|
end
|
| 483 |
|
|
|
| 484 |
|
|
for (l = 0; l <= 6; l = l + 1) begin
|
| 485 |
|
|
if (l != 0) begin
|
| 486 |
|
|
if ((CLKOUT_DIVIDE_INT_1000[l] / 1000.0) < 1 || (CLKOUT_DIVIDE_INT_1000[l] / 1000.0) > 128 || ((((CLKOUT_DIVIDE_INT_1000[l] / 1000.0) - $floor((CLKOUT_DIVIDE_INT_1000[l] / 1000.0)) > 0.001)))) begin
|
| 487 |
|
|
$display("CLKOUT%0d_DIVIDE is not in the allowed range (1-128) or it is a floating point number", l);
|
| 488 |
|
|
invalid = 1'b1;
|
| 489 |
|
|
end
|
| 490 |
|
|
end
|
| 491 |
|
|
if (CLKOUT_DUTY_CYCLE_INT_1000[l] < 1 || CLKOUT_DUTY_CYCLE_INT_1000[l] > 999) begin
|
| 492 |
|
|
$display("CLKOUT%0d_DUTY_CYCLE is not in the allowed range(0.001-0.999)", l);
|
| 493 |
|
|
invalid = 1'b1;
|
| 494 |
|
|
end else if (CLKOUT_PHASE_INT_1000[l] < -360000 || CLKOUT_PHASE_INT_1000[l] > 360000) begin
|
| 495 |
|
|
$display("CLKOUT%0d_PHASE is not in the allowed range(-360.000-360.000)", l);
|
| 496 |
|
|
invalid = 1'b1;
|
| 497 |
|
|
end
|
| 498 |
|
|
end
|
| 499 |
|
|
|
| 500 |
|
|
/* different on pll and mmcm */
|
| 501 |
|
|
if (MODULE_TYPE == "PLLE2_BASE" || MODULE_TYPE == "PLLE2_ADV") begin
|
| 502 |
|
|
if (CLKFBOUT_MULT_F_INT_1000 < 2000 || CLKFBOUT_MULT_F_INT_1000 > 64000 || ((CLKFBOUT_MULT_F_INT_1000 / 1000.0) - $floor((CLKFBOUT_MULT_F_INT_1000 / 1000.0)) > 0.001)) begin
|
| 503 |
|
|
$display("CLKFBOUT_MULT is not in the allowed range (2-64) or a floating point number.");
|
| 504 |
|
|
invalid = 1'b1;
|
| 505 |
|
|
end else if ((CLKOUT_DIVIDE_INT_1000[0] / 1000.0) < 1 || (CLKOUT_DIVIDE_INT_1000[0] / 1000.0) > 128 || (((CLKOUT_DIVIDE_INT_1000[0] / 1000.0) - $floor((CLKOUT_DIVIDE_INT_1000[0] / 1000.0)) > 0.001))) begin
|
| 506 |
|
|
$display("CLKOUT0_DIVIDE is not in the allowed range (1-128) or it is a floating point number");
|
| 507 |
|
|
invalid = 1'b1;
|
| 508 |
|
|
end
|
| 509 |
|
|
end else if (MODULE_TYPE == "MMCME2_BASE") begin
|
| 510 |
|
|
if (CLKFBOUT_MULT_F_INT_1000 < 2000 || CLKFBOUT_MULT_F_INT_1000 > 64000) begin
|
| 511 |
|
|
$display("CLKFBOUT_MULT_F is not in the allowed range (2.000-64.000)");
|
| 512 |
|
|
invalid = 1'b1;
|
| 513 |
|
|
end else if (CLKOUT_DIVIDE_INT_1000[0] < 1000 || CLKOUT_DIVIDE_INT_1000[0] > 128000) begin
|
| 514 |
|
|
$display("CLKOUT0_DIVIDE_F is not in the allowed range(2.000-64.000)");
|
| 515 |
|
|
invalid = 1'b1;
|
| 516 |
|
|
end
|
| 517 |
|
|
end
|
| 518 |
|
|
|
| 519 |
|
|
if (CLKINSEL == 1 && ((CLKFBOUT_MULT_F_INT_1000 / (CLKIN1_PERIOD * 1.0 * DIVCLK_DIVIDE)) < vco_min || (CLKFBOUT_MULT_F_INT_1000 / (CLKIN1_PERIOD * 1.0 * DIVCLK_DIVIDE_INT)) > vco_max)) begin
|
| 520 |
|
|
$display("The calculated VCO frequency is not in the allowed range (%0d-%0d). Change either CLKFBOUT_MULT_F, CLKIN1_PERIOD or DIVCLK_DIVIDE to an appropiate value.", vco_min, vco_max);
|
| 521 |
|
|
$display("To calculate the VCO frequency use this formula: (CLKFBOUT_MULT_F * 1000) / (CLKIN1_PERIOD * DIVCLK_DIVIDE).");
|
| 522 |
|
|
$display("Currently the value is %0f.", (CLKFBOUT_MULT_F_INT_1000 / (CLKIN1_PERIOD * 1.0 * DIVCLK_DIVIDE_INT)));
|
| 523 |
|
|
invalid = 1'b1;
|
| 524 |
|
|
end else if (CLKINSEL == 0 && ((CLKFBOUT_MULT_F_INT_1000 / (CLKIN2_PERIOD * 1.0 * DIVCLK_DIVIDE)) < vco_min || (CLKFBOUT_MULT_F_INT_1000 / (CLKIN2_PERIOD * 1.0 * DIVCLK_DIVIDE_INT)) > vco_max)) begin
|
| 525 |
|
|
$display("The calculated VCO frequency is not in the allowed range (%0d-%0d). Change either CLKFBOUT_MULT_F, CLKIN2_PERIOD or DIVCLK_DIVIDE to an appropiate value.", vco_min, vco_max);
|
| 526 |
|
|
$display("To calculate the VCO frequency use this formula: (CLKFBOUT_MULT_F * 1000) / (CLKIN2_PERIOD * DIVCLK_DIVIDE).");
|
| 527 |
|
|
$display("Currently the value is %0f.", (CLKFBOUT_MULT_F_INT_1000 / (CLKIN2_PERIOD * 1.0 * DIVCLK_DIVIDE_INT)));
|
| 528 |
|
|
invalid = 1'b1;
|
| 529 |
|
|
end
|
| 530 |
|
|
|
| 531 |
|
|
|
| 532 |
|
|
/* NOTE: delete this to simulate even if there are invalid values */
|
| 533 |
|
|
if (invalid) begin
|
| 534 |
|
|
$display("Exiting simulation...");
|
| 535 |
|
|
$finish;
|
| 536 |
|
|
end
|
| 537 |
|
|
end
|
| 538 |
|
|
endmodule
|
| 539 |
|
|
|
| 540 |
|
|
// synthesis translate_on
|
