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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [ext_int/] [ext_int.v] - Blame information for rev 48

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/**********************************************************************
**      File:  ext_int.v
**
**
**      Copyright (C) 2014-2017  Alireza Monemi
**
**      This file is part of ProNoC
**
**      ProNoC ( stands for Prototype Network-on-chip)  is free software:
**      you can redistribute it and/or modify it under the terms of the GNU
**      Lesser General Public License as published by the Free Software Foundation,
**      either version 2 of the License, or (at your option) any later version.
**
**      ProNoC is distributed in the hope that it will be useful, but WITHOUT
**      ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
**      or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
**      Public License for more details.
**
**      You should have received a copy of the GNU Lesser General Public
**      License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
**
**
**      Description:
**      Wishbone bus based external intrrupt module
**
*******************************************************************/
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
module ext_int #(
        parameter EXT_INT_NUM   =       3,//max 32
        parameter Aw            =       3,
        parameter SELw          =       4,
        parameter TAGw      =   3,
        parameter Dw            =       32
 
)(
    clk,
    reset,
 
    //wishbone bus interface
        sa_dat_i,
    sa_sel_i,
    sa_addr_i,
    sa_tag_i,
    sa_stb_i,
    sa_cyc_i,
    sa_we_i,
    sa_dat_o,
    sa_ack_o,
    sa_err_o,
    sa_rty_o,
 
    //interrupt ports
    ext_int_i,
    ext_int_o
);
 
    input                               clk;
    input                               reset;
 
    //wishbone bus interface
    input       [Dw-1       :   0]      sa_dat_i;
    input       [SELw-1     :   0]      sa_sel_i;
    input       [Aw-1       :   0]      sa_addr_i;
    input       [TAGw-1     :   0]      sa_tag_i;
    input                               sa_stb_i;
    input                               sa_cyc_i;
    input                               sa_we_i;
 
    output      [Dw-1       :   0]      sa_dat_o;
    output  reg                         sa_ack_o;
    output                              sa_err_o;
    output                              sa_rty_o;
 
 
    //interrupt ports
    input   [EXT_INT_NUM-1      :   0]  ext_int_i;
    output                              ext_int_o; //output to the interrupt controller
 
 
 
 
//interrupt registers                                                   
 
        localparam      [Aw-1           :       0]               GER_REG_ADDR                    =       0;
        localparam      [Aw-1           :       0]               IER_RISING_REG_ADDR     =       1;
        localparam      [Aw-1           :       0]               IER_FALLING_REG_ADDR    =       2;
        localparam      [Aw-1           :       0]               ISR_REG_ADDR                    =       3;
        localparam      [Aw-1           :       0]               PIN_REG_ADDR                    =       4;
 
 
        reg                                                                             ger,ger_next;
        reg     [EXT_INT_NUM-1                  :       0]       ier_rise,ier_fall,isr,read,int_reg1,int_reg2;//2        
        reg     [EXT_INT_NUM-1                  :       0]       ier_rise_next,ier_fall_next,isr_next,read_next,int_reg1_next,int_reg2_next;
 
        wire    [EXT_INT_NUM-1                  :       0]       triggered,rise_edge,fall_edge;
 
 
        assign  sa_err_o=1'b0;
        assign  sa_rty_o=1'b0;
        assign rise_edge = (ger)?       ier_rise & ~int_reg2    & int_reg1      :       {EXT_INT_NUM{1'b0}};
        assign fall_edge = (ger)?       ier_fall & int_reg2     & ~int_reg1     :       {EXT_INT_NUM{1'b0}};
 
        assign  triggered       =       rise_edge |  fall_edge;
 
`ifdef SYNC_RESET_MODE
    always @ (posedge clk )begin
`else
    always @ (posedge clk or posedge reset)begin
`endif
                if(reset) begin
                        ger             <=      1'b0;
                        ier_rise        <= {EXT_INT_NUM{1'b0}};
                        ier_fall        <= {EXT_INT_NUM{1'b0}};
                        isr             <=      {EXT_INT_NUM{1'b0}};
                        read            <=      {EXT_INT_NUM{1'b0}};
                        int_reg1        <=      {EXT_INT_NUM{1'b0}};
                        int_reg2        <=      {EXT_INT_NUM{1'b0}};
                        sa_ack_o        <=      1'b0;
 
                end else begin
                        ger             <=      ger_next;
                        ier_rise        <= ier_rise_next;
                        ier_fall        <=      ier_fall_next;
                        isr             <=      isr_next;
                        read            <=      read_next;
                        int_reg1        <=      int_reg1_next;
                        int_reg2        <=      int_reg2_next;
                        sa_ack_o        <=       sa_stb_i && ~sa_ack_o;
                end//                   
        end//always
 
        always@(*) begin
                int_reg2_next   = int_reg1;
                int_reg1_next   = ext_int_i;
                ger_next                        = ger;
                ier_rise_next   = ier_rise;
                ier_fall_next   = ier_fall;
                isr_next                        = isr | triggered; // set isr if the intrrupt is triggered 
                read_next               = read;
                if(sa_stb_i && sa_we_i ) begin
                        if( sa_addr_i   ==      GER_REG_ADDR                    )               ger_next                        =       sa_dat_i[0];
                        if( sa_addr_i   == IER_RISING_REG_ADDR  )               ier_rise_next   =       sa_dat_i[EXT_INT_NUM-1'b1               :       0];
                        if( sa_addr_i   == IER_FALLING_REG_ADDR )               ier_fall_next   =       sa_dat_i[EXT_INT_NUM-1'b1               :       0];
                        if( sa_addr_i   == ISR_REG_ADDR                         )               isr_next                        =       isr & ~sa_dat_i[EXT_INT_NUM-1'b1                :       0];// reset isr by writting 1
                end
                if(sa_stb_i && ~sa_we_i) begin
                        case(sa_addr_i)
                                GER_REG_ADDR:                           read_next       =       {{(EXT_INT_NUM-1){1'b0}},ger};
                                IER_RISING_REG_ADDR:            read_next       =       ier_rise;
                                IER_FALLING_REG_ADDR:   read_next       =       ier_fall;
                                ISR_REG_ADDR:                           read_next       =       isr;
                                PIN_REG_ADDR:                           read_next       =       ext_int_i;
                                default                                         read_next       =       read;
                        endcase
                end
        end//always
 
 
        generate
                if(EXT_INT_NUM!=Dw)begin
                        assign sa_dat_o ={{(Dw-EXT_INT_NUM){1'b0}}, read};
                end else begin
                        assign sa_dat_o = read;
                end
        endgenerate
 
        assign ext_int_o = |isr;
 
 
endmodule

Line No.	Rev	Author	Line
1	48	alirezamon
2			`/**********************************************************************`
3			`** File: ext_int.v`
4			`**`
5			`**`
6			`** Copyright (C) 2014-2017 Alireza Monemi`
7			`**`
8			`** This file is part of ProNoC`
9			`**`
10			`** ProNoC ( stands for Prototype Network-on-chip) is free software:`
11			`** you can redistribute it and/or modify it under the terms of the GNU`
12			`** Lesser General Public License as published by the Free Software Foundation,`
13			`** either version 2 of the License, or (at your option) any later version.`
14			`**`
15			`** ProNoC is distributed in the hope that it will be useful, but WITHOUT`
16			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
17			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
18			`** Public License for more details.`
19			`**`
20			`** You should have received a copy of the GNU Lesser General Public`
21			` License along with ProNoC. If not, see <http:www.gnu.org/licenses/>.`
22			`**`
23			`**`
24			`** Description:`
25			`** Wishbone bus based external intrrupt module`
26			`**`
27			`*******************************************************************/`
28
29
30			`// synthesis translate_off`
31			`timescale 1ns / 1ps
32			`// synthesis translate_on`
33
34			`module ext_int #(`
35			`parameter EXT_INT_NUM = 3,//max 32`
36			`parameter Aw = 3,`
37			`parameter SELw = 4,`
38			`parameter TAGw = 3,`
39			`parameter Dw = 32`
40
41			`)(`
42			`clk,`
43			`reset,`
44
45			`//wishbone bus interface`
46			`sa_dat_i,`
47			`sa_sel_i,`
48			`sa_addr_i,`
49			`sa_tag_i,`
50			`sa_stb_i,`
51			`sa_cyc_i,`
52			`sa_we_i,`
53			`sa_dat_o,`
54			`sa_ack_o,`
55			`sa_err_o,`
56			`sa_rty_o,`
57
58			`//interrupt ports`
59			`ext_int_i,`
60			`ext_int_o`
61			`);`
62
63			`input clk;`
64			`input reset;`
65
66			`//wishbone bus interface`
67			`input [Dw-1 : 0] sa_dat_i;`
68			`input [SELw-1 : 0] sa_sel_i;`
69			`input [Aw-1 : 0] sa_addr_i;`
70			`input [TAGw-1 : 0] sa_tag_i;`
71			`input sa_stb_i;`
72			`input sa_cyc_i;`
73			`input sa_we_i;`
74
75			`output [Dw-1 : 0] sa_dat_o;`
76			`output reg sa_ack_o;`
77			`output sa_err_o;`
78			`output sa_rty_o;`
79
80
81			`//interrupt ports`
82			`input [EXT_INT_NUM-1 : 0] ext_int_i;`
83			`output ext_int_o; //output to the interrupt controller`
84
85
86
87
88			`//interrupt registers`
89
90			`localparam [Aw-1 : 0] GER_REG_ADDR = 0;`
91			`localparam [Aw-1 : 0] IER_RISING_REG_ADDR = 1;`
92			`localparam [Aw-1 : 0] IER_FALLING_REG_ADDR = 2;`
93			`localparam [Aw-1 : 0] ISR_REG_ADDR = 3;`
94			`localparam [Aw-1 : 0] PIN_REG_ADDR = 4;`
95
96
97			`reg ger,ger_next;`
98			`reg [EXT_INT_NUM-1 : 0] ier_rise,ier_fall,isr,read,int_reg1,int_reg2;//2`
99			`reg [EXT_INT_NUM-1 : 0] ier_rise_next,ier_fall_next,isr_next,read_next,int_reg1_next,int_reg2_next;`
100
101			`wire [EXT_INT_NUM-1 : 0] triggered,rise_edge,fall_edge;`
102
103
104			`assign sa_err_o=1'b0;`
105			`assign sa_rty_o=1'b0;`
106			`assign rise_edge = (ger)? ier_rise & ~int_reg2 & int_reg1 : {EXT_INT_NUM{1'b0}};`
107			`assign fall_edge = (ger)? ier_fall & int_reg2 & ~int_reg1 : {EXT_INT_NUM{1'b0}};`
108
109			`assign triggered = rise_edge \| fall_edge;`
110
111			`ifdef SYNC_RESET_MODE
112			`always @ (posedge clk )begin`
113			`else
114			`always @ (posedge clk or posedge reset)begin`
115			`endif
116			`if(reset) begin`
117			`ger <= 1'b0;`
118			`ier_rise <= {EXT_INT_NUM{1'b0}};`
119			`ier_fall <= {EXT_INT_NUM{1'b0}};`
120			`isr <= {EXT_INT_NUM{1'b0}};`
121			`read <= {EXT_INT_NUM{1'b0}};`
122			`int_reg1 <= {EXT_INT_NUM{1'b0}};`
123			`int_reg2 <= {EXT_INT_NUM{1'b0}};`
124			`sa_ack_o <= 1'b0;`
125
126			`end else begin`
127			`ger <= ger_next;`
128			`ier_rise <= ier_rise_next;`
129			`ier_fall <= ier_fall_next;`
130			`isr <= isr_next;`
131			`read <= read_next;`
132			`int_reg1 <= int_reg1_next;`
133			`int_reg2 <= int_reg2_next;`
134			`sa_ack_o <= sa_stb_i && ~sa_ack_o;`
135			`end//`
136			`end//always`
137
138			`always@(*) begin`
139			`int_reg2_next = int_reg1;`
140			`int_reg1_next = ext_int_i;`
141			`ger_next = ger;`
142			`ier_rise_next = ier_rise;`
143			`ier_fall_next = ier_fall;`
144			`isr_next = isr \| triggered; // set isr if the intrrupt is triggered`
145			`read_next = read;`
146			`if(sa_stb_i && sa_we_i ) begin`
147			`if( sa_addr_i == GER_REG_ADDR ) ger_next = sa_dat_i[0];`
148			`if( sa_addr_i == IER_RISING_REG_ADDR ) ier_rise_next = sa_dat_i[EXT_INT_NUM-1'b1 : 0];`
149			`if( sa_addr_i == IER_FALLING_REG_ADDR ) ier_fall_next = sa_dat_i[EXT_INT_NUM-1'b1 : 0];`
150			`if( sa_addr_i == ISR_REG_ADDR ) isr_next = isr & ~sa_dat_i[EXT_INT_NUM-1'b1 : 0];// reset isr by writting 1`
151			`end`
152			`if(sa_stb_i && ~sa_we_i) begin`
153			`case(sa_addr_i)`
154			`GER_REG_ADDR: read_next = {{(EXT_INT_NUM-1){1'b0}},ger};`
155			`IER_RISING_REG_ADDR: read_next = ier_rise;`
156			`IER_FALLING_REG_ADDR: read_next = ier_fall;`
157			`ISR_REG_ADDR: read_next = isr;`
158			`PIN_REG_ADDR: read_next = ext_int_i;`
159			`default read_next = read;`
160			`endcase`
161			`end`
162			`end//always`
163
164
165			`generate`
166			`if(EXT_INT_NUM!=Dw)begin`
167			`assign sa_dat_o ={{(Dw-EXT_INT_NUM){1'b0}}, read};`
168			`end else begin`
169			`assign sa_dat_o = read;`
170			`end`
171			`endgenerate`
172
173			`assign ext_int_o = \|isr;`
174
175
176			`endmodule`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [ext_int/] [ext_int.v] - Blame information for rev 48