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alirezamon |
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/**************************************************************************
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** WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
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** OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
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****************************************************************************/
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/**********************************************************************
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** File: ram_test.v
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**
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** Copyright (C) 2014-2018 Alireza Monemi
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**
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** This file is part of ProNoC 1.7.0
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**
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** you can redistribute it and/or modify it under the terms of the GNU
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** Lesser General Public License as published by the Free Software Foundation,
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** either version 2 of the License, or (at your option) any later version.
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**
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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**
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** You should have received a copy of the GNU Lesser General Public
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** License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
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******************************************************************************/
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`timescale 1ns / 1ps
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module ram_test #(
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parameter CORE_ID=0,
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parameter SW_LOC="/home/alireza/mywork/mpsoc_work/SOC/ram_test/sw" ,
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parameter ram_Dw=32 ,
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parameter ram_Aw=12
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)(
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ss_clk_in,
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ss_reset_in
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);
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function integer log2;
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input integer number; begin
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log2=0;
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while(2**log2<number) begin
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log2=log2+1;
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end
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end
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endfunction // log2
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function [15:0]i2s;
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input integer c; integer i; integer tmp; begin
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tmp =0;
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for (i=0; i<2; i=i+1'b1) begin
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tmp = tmp + (((c % 10) + 6'd48) << i*8);
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c = c/10;
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end
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i2s = tmp[15:0];
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end
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endfunction //i2s
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localparam programer_DW=32;
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localparam programer_AW=32;
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localparam programer_S_Aw= 7;
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localparam programer_M_Aw= 32;
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localparam programer_TAGw= 3;
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localparam programer_SELw= 4;
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localparam programer_VJTAG_INDEX=CORE_ID;
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localparam ram_BYTE_WR_EN="YES";
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localparam ram_FPGA_VENDOR="ALTERA";
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localparam ram_JTAG_CONNECT= "ALTERA_IMCE";
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localparam ram_JTAG_INDEX=CORE_ID;
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localparam ram_TAGw=3;
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localparam ram_SELw=ram_Dw/8;
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localparam ram_CTIw=3;
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localparam ram_BTEw=2;
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localparam ram_BURST_MODE="DISABLED";
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localparam ram_MEM_CONTENT_FILE_NAME="ram0";
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localparam ram_INITIAL_EN="NO";
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localparam ram_INIT_FILE_PATH=SW_LOC;
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localparam bus_M=1;
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localparam bus_S=1;
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localparam bus_Dw=32;
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localparam bus_Aw=32;
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localparam bus_SELw=bus_Dw/8;
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localparam bus_TAGw=3;
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localparam bus_CTIw=3;
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localparam bus_BTEw=2 ;
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//Wishbone slave base address based on instance name
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localparam ram_WB0_BASE_ADDR = 32'h00000000;
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localparam ram_WB0_END_ADDR = 32'h00000fff;
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//Wishbone slave base address based on module name.
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localparam single_port_ram0_WB0_BASE_ADDR = 32'h00000000;
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localparam single_port_ram0_WB0_END_ADDR = 32'h00000fff;
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input ss_clk_in;
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input ss_reset_in;
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wire ss_socket_clk_0_clk_o;
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wire ss_socket_reset_0_reset_o;
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wire programer_plug_clk_0_clk_i;
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wire programer_plug_wb_master_0_ack_i;
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wire [ programer_M_Aw-1 : 0 ] programer_plug_wb_master_0_adr_o;
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wire [ programer_TAGw-1 : 0 ] programer_plug_wb_master_0_cti_o;
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wire programer_plug_wb_master_0_cyc_o;
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wire [ programer_DW-1 : 0 ] programer_plug_wb_master_0_dat_i;
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wire [ programer_DW-1 : 0 ] programer_plug_wb_master_0_dat_o;
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wire [ programer_SELw-1 : 0 ] programer_plug_wb_master_0_sel_o;
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wire programer_plug_wb_master_0_stb_o;
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wire programer_plug_wb_master_0_we_o;
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wire programer_plug_reset_0_reset_i;
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wire ram_plug_clk_0_clk_i;
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wire ram_plug_reset_0_reset_i;
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wire ram_plug_wb_slave_0_ack_o;
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wire [ ram_Aw-1 : 0 ] ram_plug_wb_slave_0_adr_i;
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wire [ ram_BTEw-1 : 0 ] ram_plug_wb_slave_0_bte_i;
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wire [ ram_CTIw-1 : 0 ] ram_plug_wb_slave_0_cti_i;
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wire ram_plug_wb_slave_0_cyc_i;
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wire [ ram_Dw-1 : 0 ] ram_plug_wb_slave_0_dat_i;
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wire [ ram_Dw-1 : 0 ] ram_plug_wb_slave_0_dat_o;
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wire ram_plug_wb_slave_0_err_o;
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wire ram_plug_wb_slave_0_rty_o;
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wire [ ram_SELw-1 : 0 ] ram_plug_wb_slave_0_sel_i;
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wire ram_plug_wb_slave_0_stb_i;
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wire [ ram_TAGw-1 : 0 ] ram_plug_wb_slave_0_tag_i;
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wire ram_plug_wb_slave_0_we_i;
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wire bus_plug_clk_0_clk_i;
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wire [ bus_M-1 : 0 ] bus_socket_wb_master_array_ack_o;
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wire bus_socket_wb_master_0_ack_o;
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wire [ bus_Aw*bus_M-1 : 0 ] bus_socket_wb_master_array_adr_i;
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wire [ bus_Aw-1:0 ] bus_socket_wb_master_0_adr_i;
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wire [ bus_BTEw*bus_M-1 : 0 ] bus_socket_wb_master_array_bte_i;
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wire [ bus_BTEw-1:0 ] bus_socket_wb_master_0_bte_i;
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wire [ bus_CTIw*bus_M-1 : 0 ] bus_socket_wb_master_array_cti_i;
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wire [ bus_CTIw-1:0 ] bus_socket_wb_master_0_cti_i;
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wire [ bus_M-1 : 0 ] bus_socket_wb_master_array_cyc_i;
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wire bus_socket_wb_master_0_cyc_i;
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wire [ bus_Dw*bus_M-1 : 0 ] bus_socket_wb_master_array_dat_i;
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wire [ bus_Dw-1:0 ] bus_socket_wb_master_0_dat_i;
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wire [ bus_Dw*bus_M-1 : 0 ] bus_socket_wb_master_array_dat_o;
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wire [ bus_Dw-1:0 ] bus_socket_wb_master_0_dat_o;
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wire [ bus_M-1 : 0 ] bus_socket_wb_master_array_err_o;
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wire bus_socket_wb_master_0_err_o;
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wire [ bus_Aw-1 : 0 ] bus_socket_wb_addr_map_0_grant_addr;
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wire [ bus_M-1 : 0 ] bus_socket_wb_master_array_rty_o;
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wire bus_socket_wb_master_0_rty_o;
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wire [ bus_SELw*bus_M-1 : 0 ] bus_socket_wb_master_array_sel_i;
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wire [ bus_SELw-1:0 ] bus_socket_wb_master_0_sel_i;
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wire [ bus_M-1 : 0 ] bus_socket_wb_master_array_stb_i;
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wire bus_socket_wb_master_0_stb_i;
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wire [ bus_TAGw*bus_M-1 : 0 ] bus_socket_wb_master_array_tag_i;
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wire [ bus_TAGw-1:0 ] bus_socket_wb_master_0_tag_i;
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wire [ bus_M-1 : 0 ] bus_socket_wb_master_array_we_i;
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wire bus_socket_wb_master_0_we_i;
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wire bus_plug_reset_0_reset_i;
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wire [ bus_S-1 : 0 ] bus_socket_wb_slave_array_ack_i;
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wire bus_socket_wb_slave_0_ack_i;
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wire [ bus_Aw*bus_S-1 : 0 ] bus_socket_wb_slave_array_adr_o;
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wire [ bus_Aw-1:0 ] bus_socket_wb_slave_0_adr_o;
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wire [ bus_BTEw*bus_S-1 : 0 ] bus_socket_wb_slave_array_bte_o;
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wire [ bus_BTEw-1:0 ] bus_socket_wb_slave_0_bte_o;
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wire [ bus_CTIw*bus_S-1 : 0 ] bus_socket_wb_slave_array_cti_o;
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wire [ bus_CTIw-1:0 ] bus_socket_wb_slave_0_cti_o;
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wire [ bus_S-1 : 0 ] bus_socket_wb_slave_array_cyc_o;
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wire bus_socket_wb_slave_0_cyc_o;
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wire [ bus_Dw*bus_S-1 : 0 ] bus_socket_wb_slave_array_dat_i;
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wire [ bus_Dw-1:0 ] bus_socket_wb_slave_0_dat_i;
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wire [ bus_Dw*bus_S-1 : 0 ] bus_socket_wb_slave_array_dat_o;
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wire [ bus_Dw-1:0 ] bus_socket_wb_slave_0_dat_o;
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wire [ bus_S-1 : 0 ] bus_socket_wb_slave_array_err_i;
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wire bus_socket_wb_slave_0_err_i;
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wire [ bus_S-1 : 0 ] bus_socket_wb_slave_array_rty_i;
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wire bus_socket_wb_slave_0_rty_i;
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wire [ bus_SELw*bus_S-1 : 0 ] bus_socket_wb_slave_array_sel_o;
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wire [ bus_SELw-1:0 ] bus_socket_wb_slave_0_sel_o;
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wire [ bus_S-1 : 0 ] bus_socket_wb_addr_map_0_sel_one_hot;
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wire [ bus_S-1 : 0 ] bus_socket_wb_slave_array_stb_o;
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wire bus_socket_wb_slave_0_stb_o;
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wire [ bus_TAGw*bus_S-1 : 0 ] bus_socket_wb_slave_array_tag_o;
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wire [ bus_TAGw-1:0 ] bus_socket_wb_slave_0_tag_o;
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wire [ bus_S-1 : 0 ] bus_socket_wb_slave_array_we_o;
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wire bus_socket_wb_slave_0_we_o;
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//Take the default value for ports that defined by interfaces but did not assigned to any wires.
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assign bus_socket_wb_master_0_bte_i = {bus_BTEw{1'b0}};
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assign bus_socket_wb_master_0_tag_i = {bus_TAGw{1'b0}};
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clk_source ss (
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.clk_in(ss_clk_in),
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.clk_out(ss_socket_clk_0_clk_o),
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.reset_in(ss_reset_in),
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.reset_out(ss_socket_reset_0_reset_o)
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);
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vjtag_wb #(
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.DW(programer_DW),
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.AW(programer_AW),
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.S_Aw(programer_S_Aw),
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.M_Aw(programer_M_Aw),
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.TAGw(programer_TAGw),
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.SELw(programer_SELw),
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.VJTAG_INDEX(programer_VJTAG_INDEX)
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) programer (
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.clk(programer_plug_clk_0_clk_i),
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.m_ack_i(programer_plug_wb_master_0_ack_i),
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.m_addr_o(programer_plug_wb_master_0_adr_o),
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.m_cti_o(programer_plug_wb_master_0_cti_o),
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.m_cyc_o(programer_plug_wb_master_0_cyc_o),
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.m_dat_i(programer_plug_wb_master_0_dat_i),
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.m_dat_o(programer_plug_wb_master_0_dat_o),
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.m_sel_o(programer_plug_wb_master_0_sel_o),
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.m_stb_o(programer_plug_wb_master_0_stb_o),
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.m_we_o(programer_plug_wb_master_0_we_o),
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.reset(programer_plug_reset_0_reset_i),
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.status_i()
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);
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wb_single_port_ram #(
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.Dw(ram_Dw),
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.Aw(ram_Aw),
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.BYTE_WR_EN(ram_BYTE_WR_EN),
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.FPGA_VENDOR(ram_FPGA_VENDOR),
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.JTAG_CONNECT(ram_JTAG_CONNECT),
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.JTAG_INDEX(1),
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.TAGw(ram_TAGw),
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.SELw(ram_SELw),
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.CTIw(ram_CTIw),
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.BTEw(ram_BTEw),
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.BURST_MODE(ram_BURST_MODE),
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.MEM_CONTENT_FILE_NAME(ram_MEM_CONTENT_FILE_NAME),
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.INITIAL_EN(ram_INITIAL_EN),
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.INIT_FILE_PATH(ram_INIT_FILE_PATH)
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) ram (
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.clk(ram_plug_clk_0_clk_i),
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.reset(ram_plug_reset_0_reset_i),
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.sa_ack_o(ram_plug_wb_slave_0_ack_o),
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.sa_addr_i(ram_plug_wb_slave_0_adr_i),
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.sa_bte_i(ram_plug_wb_slave_0_bte_i),
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.sa_cti_i(ram_plug_wb_slave_0_cti_i),
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.sa_cyc_i(ram_plug_wb_slave_0_cyc_i),
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.sa_dat_i(ram_plug_wb_slave_0_dat_i),
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.sa_dat_o(ram_plug_wb_slave_0_dat_o),
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.sa_err_o(ram_plug_wb_slave_0_err_o),
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.sa_rty_o(ram_plug_wb_slave_0_rty_o),
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.sa_sel_i(ram_plug_wb_slave_0_sel_i),
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.sa_stb_i(ram_plug_wb_slave_0_stb_i),
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.sa_tag_i(ram_plug_wb_slave_0_tag_i),
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.sa_we_i(ram_plug_wb_slave_0_we_i)
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);
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wishbone_bus #(
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.M(bus_M),
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.S(bus_S),
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.Dw(bus_Dw),
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.Aw(bus_Aw),
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.SELw(bus_SELw),
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.TAGw(bus_TAGw),
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.CTIw(bus_CTIw),
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.BTEw(bus_BTEw)
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) bus (
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.clk(bus_plug_clk_0_clk_i),
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.m_ack_o_all(bus_socket_wb_master_array_ack_o),
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.m_adr_i_all(bus_socket_wb_master_array_adr_i),
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.m_bte_i_all(bus_socket_wb_master_array_bte_i),
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.m_cti_i_all(bus_socket_wb_master_array_cti_i),
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.m_cyc_i_all(bus_socket_wb_master_array_cyc_i),
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.m_dat_i_all(bus_socket_wb_master_array_dat_i),
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.m_dat_o_all(bus_socket_wb_master_array_dat_o),
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.m_err_o_all(bus_socket_wb_master_array_err_o),
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.m_grant_addr(bus_socket_wb_addr_map_0_grant_addr),
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.m_rty_o_all(bus_socket_wb_master_array_rty_o),
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.m_sel_i_all(bus_socket_wb_master_array_sel_i),
|
279 |
|
|
.m_stb_i_all(bus_socket_wb_master_array_stb_i),
|
280 |
|
|
.m_tag_i_all(bus_socket_wb_master_array_tag_i),
|
281 |
|
|
.m_we_i_all(bus_socket_wb_master_array_we_i),
|
282 |
|
|
.reset(bus_plug_reset_0_reset_i),
|
283 |
|
|
.s_ack_i_all(bus_socket_wb_slave_array_ack_i),
|
284 |
|
|
.s_adr_o_all(bus_socket_wb_slave_array_adr_o),
|
285 |
|
|
.s_bte_o_all(bus_socket_wb_slave_array_bte_o),
|
286 |
|
|
.s_cti_o_all(bus_socket_wb_slave_array_cti_o),
|
287 |
|
|
.s_cyc_o_all(bus_socket_wb_slave_array_cyc_o),
|
288 |
|
|
.s_dat_i_all(bus_socket_wb_slave_array_dat_i),
|
289 |
|
|
.s_dat_o_all(bus_socket_wb_slave_array_dat_o),
|
290 |
|
|
.s_err_i_all(bus_socket_wb_slave_array_err_i),
|
291 |
|
|
.s_rty_i_all(bus_socket_wb_slave_array_rty_i),
|
292 |
|
|
.s_sel_o_all(bus_socket_wb_slave_array_sel_o),
|
293 |
|
|
.s_sel_one_hot(bus_socket_wb_addr_map_0_sel_one_hot),
|
294 |
|
|
.s_stb_o_all(bus_socket_wb_slave_array_stb_o),
|
295 |
|
|
.s_tag_o_all(bus_socket_wb_slave_array_tag_o),
|
296 |
|
|
.s_we_o_all(bus_socket_wb_slave_array_we_o)
|
297 |
|
|
);
|
298 |
|
|
|
299 |
|
|
|
300 |
|
|
|
301 |
|
|
assign programer_plug_clk_0_clk_i = ss_socket_clk_0_clk_o;
|
302 |
|
|
assign programer_plug_wb_master_0_ack_i = bus_socket_wb_master_0_ack_o;
|
303 |
|
|
assign bus_socket_wb_master_0_adr_i = programer_plug_wb_master_0_adr_o;
|
304 |
|
|
assign bus_socket_wb_master_0_cti_i = programer_plug_wb_master_0_cti_o;
|
305 |
|
|
assign bus_socket_wb_master_0_cyc_i = programer_plug_wb_master_0_cyc_o;
|
306 |
|
|
assign programer_plug_wb_master_0_dat_i = bus_socket_wb_master_0_dat_o[programer_DW-1 : 0];
|
307 |
|
|
assign bus_socket_wb_master_0_dat_i = programer_plug_wb_master_0_dat_o;
|
308 |
|
|
assign bus_socket_wb_master_0_sel_i = programer_plug_wb_master_0_sel_o;
|
309 |
|
|
assign bus_socket_wb_master_0_stb_i = programer_plug_wb_master_0_stb_o;
|
310 |
|
|
assign bus_socket_wb_master_0_we_i = programer_plug_wb_master_0_we_o;
|
311 |
|
|
assign programer_plug_reset_0_reset_i = ss_socket_reset_0_reset_o;
|
312 |
|
|
|
313 |
|
|
|
314 |
|
|
assign ram_plug_clk_0_clk_i = ss_socket_clk_0_clk_o;
|
315 |
|
|
assign ram_plug_reset_0_reset_i = ss_socket_reset_0_reset_o;
|
316 |
|
|
assign bus_socket_wb_slave_0_ack_i = ram_plug_wb_slave_0_ack_o;
|
317 |
|
|
assign ram_plug_wb_slave_0_adr_i = bus_socket_wb_slave_0_adr_o[ram_Aw-1 : 0];
|
318 |
|
|
assign ram_plug_wb_slave_0_bte_i = bus_socket_wb_slave_0_bte_o[ram_BTEw-1 : 0];
|
319 |
|
|
assign ram_plug_wb_slave_0_cti_i = bus_socket_wb_slave_0_cti_o[ram_CTIw-1 : 0];
|
320 |
|
|
assign ram_plug_wb_slave_0_cyc_i = bus_socket_wb_slave_0_cyc_o;
|
321 |
|
|
assign ram_plug_wb_slave_0_dat_i = bus_socket_wb_slave_0_dat_o[ram_Dw-1 : 0];
|
322 |
|
|
assign bus_socket_wb_slave_0_dat_i = ram_plug_wb_slave_0_dat_o;
|
323 |
|
|
assign bus_socket_wb_slave_0_err_i = ram_plug_wb_slave_0_err_o;
|
324 |
|
|
assign bus_socket_wb_slave_0_rty_i = ram_plug_wb_slave_0_rty_o;
|
325 |
|
|
assign ram_plug_wb_slave_0_sel_i = bus_socket_wb_slave_0_sel_o[ram_SELw-1 : 0];
|
326 |
|
|
assign ram_plug_wb_slave_0_stb_i = bus_socket_wb_slave_0_stb_o;
|
327 |
|
|
assign ram_plug_wb_slave_0_tag_i = bus_socket_wb_slave_0_tag_o[ram_TAGw-1 : 0];
|
328 |
|
|
assign ram_plug_wb_slave_0_we_i = bus_socket_wb_slave_0_we_o;
|
329 |
|
|
|
330 |
|
|
|
331 |
|
|
assign bus_plug_clk_0_clk_i = ss_socket_clk_0_clk_o;
|
332 |
|
|
assign bus_plug_reset_0_reset_i = ss_socket_reset_0_reset_o;
|
333 |
|
|
|
334 |
|
|
assign bus_socket_wb_master_0_ack_o = bus_socket_wb_master_array_ack_o;
|
335 |
|
|
assign bus_socket_wb_master_array_adr_i = bus_socket_wb_master_0_adr_i;
|
336 |
|
|
assign bus_socket_wb_master_array_bte_i = bus_socket_wb_master_0_bte_i;
|
337 |
|
|
assign bus_socket_wb_master_array_cti_i = bus_socket_wb_master_0_cti_i;
|
338 |
|
|
assign bus_socket_wb_master_array_cyc_i = bus_socket_wb_master_0_cyc_i;
|
339 |
|
|
assign bus_socket_wb_master_array_dat_i = bus_socket_wb_master_0_dat_i;
|
340 |
|
|
assign bus_socket_wb_master_0_dat_o = bus_socket_wb_master_array_dat_o;
|
341 |
|
|
assign bus_socket_wb_master_0_err_o = bus_socket_wb_master_array_err_o;
|
342 |
|
|
assign bus_socket_wb_master_0_rty_o = bus_socket_wb_master_array_rty_o;
|
343 |
|
|
assign bus_socket_wb_master_array_sel_i = bus_socket_wb_master_0_sel_i;
|
344 |
|
|
assign bus_socket_wb_master_array_stb_i = bus_socket_wb_master_0_stb_i;
|
345 |
|
|
assign bus_socket_wb_master_array_tag_i = bus_socket_wb_master_0_tag_i;
|
346 |
|
|
assign bus_socket_wb_master_array_we_i = bus_socket_wb_master_0_we_i;
|
347 |
|
|
assign bus_socket_wb_slave_array_ack_i = bus_socket_wb_slave_0_ack_i;
|
348 |
|
|
assign bus_socket_wb_slave_0_adr_o = bus_socket_wb_slave_array_adr_o;
|
349 |
|
|
assign bus_socket_wb_slave_0_bte_o = bus_socket_wb_slave_array_bte_o;
|
350 |
|
|
assign bus_socket_wb_slave_0_cti_o = bus_socket_wb_slave_array_cti_o;
|
351 |
|
|
assign bus_socket_wb_slave_0_cyc_o = bus_socket_wb_slave_array_cyc_o;
|
352 |
|
|
assign bus_socket_wb_slave_array_dat_i = bus_socket_wb_slave_0_dat_i;
|
353 |
|
|
assign bus_socket_wb_slave_0_dat_o = bus_socket_wb_slave_array_dat_o;
|
354 |
|
|
assign bus_socket_wb_slave_array_err_i = bus_socket_wb_slave_0_err_i;
|
355 |
|
|
assign bus_socket_wb_slave_array_rty_i = bus_socket_wb_slave_0_rty_i;
|
356 |
|
|
assign bus_socket_wb_slave_0_sel_o = bus_socket_wb_slave_array_sel_o;
|
357 |
|
|
assign bus_socket_wb_slave_0_stb_o = bus_socket_wb_slave_array_stb_o;
|
358 |
|
|
assign bus_socket_wb_slave_0_tag_o = bus_socket_wb_slave_array_tag_o;
|
359 |
|
|
assign bus_socket_wb_slave_0_we_o = bus_socket_wb_slave_array_we_o;
|
360 |
|
|
|
361 |
|
|
|
362 |
|
|
//Wishbone slave address match
|
363 |
|
|
/* ram wb_slave 0 */
|
364 |
|
|
assign bus_socket_wb_addr_map_0_sel_one_hot[0] = ((bus_socket_wb_addr_map_0_grant_addr >= ram_WB0_BASE_ADDR) & (bus_socket_wb_addr_map_0_grant_addr <= ram_WB0_END_ADDR));
|
365 |
|
|
endmodule
|
366 |
|
|
|