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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [verilog/] [src/] [aeMB2_brcc.v] - Blame information for rev 16

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1 16 alirezamon
/* $Id: aeMB2_brcc.v,v 1.3 2008-04-26 01:09:05 sybreon Exp $
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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** This file is part of AEMB.
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
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** Public License for more details.
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**
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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*/
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/**
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 * Branch Condition Checker
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 * @file aeMB2_brcc.v
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 * This controls the decision to branch/delay. The actualy branch
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   target is calculated in the ALU.
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 */
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`timescale  1ns/1ps
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module aeMB2_brcc (/*AUTOARG*/
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   // Outputs
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   bra_ex,
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   // Inputs
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   opd_of, ra_of, rd_of, opc_of, gclk, grst, dena, iena, gpha
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   );
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   parameter AEMB_HTX = 1;
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   input [31:0] opd_of;
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   input [4:0]   ra_of;
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   input [4:0]   rd_of;
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   input [5:0]   opc_of;
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   output [1:0] bra_ex;
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   // SYS signals
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   input        gclk,
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                grst,
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                dena,
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                iena,
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                gpha;
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   /*AUTOREG*/
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   // Beginning of automatic regs (for this module's undeclared outputs)
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   reg [1:0]             bra_ex;
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   // End of automatics
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   // TODO: replace comparators with logic
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   /* Branch Control */
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   wire         wRTD = (opc_of == 6'o55);
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   wire         wBCC = (opc_of == 6'o47) | (opc_of == 6'o57);
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   wire         wBRU = (opc_of == 6'o46) | (opc_of == 6'o56);
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   wire         wBEQ = (opd_of == 32'd0);
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   wire         wBLT = opd_of[31];
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   wire         wBLE = wBLT | wBEQ;
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   wire         wBNE = ~wBEQ;
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   wire         wBGE = ~wBLT;
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   wire         wBGT = ~wBLE;
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   reg           xcc;
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   always @(/*AUTOSENSE*/rd_of or wBEQ or wBGE or wBGT or wBLE or wBLT
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            or wBNE) begin
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      case (rd_of[2:0])
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        3'o0: xcc <= wBEQ;
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        3'o1: xcc <= wBNE;
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        3'o2: xcc <= wBLT;
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        3'o3: xcc <= wBLE;
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        3'o4: xcc <= wBGT;
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        3'o5: xcc <= wBGE;
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        default: xcc <= 1'bX;
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      endcase // case (rd_of[2:0])
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   end // always @ (...
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   always @(posedge gclk)
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     if (grst) begin
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        /*AUTORESET*/
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        // Beginning of autoreset for uninitialized flops
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        bra_ex <= 2'h0;
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        // End of automatics
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     end else if (dena) begin
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        bra_ex[1] <= #1 (wRTD | wBRU | (wBCC & xcc)); // branch
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        bra_ex[0] <= #1 (wBRU) ? ra_of[4] : rd_of[4]; // delay   
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     end
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endmodule // aeMB2_brcc
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/*
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 $Log: not supported by cvs2svn $
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 Revision 1.2  2008/04/20 16:34:32  sybreon
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 Basic version with some features left out.
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 Revision 1.1  2008/04/18 00:21:52  sybreon
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 Initial import.
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*/

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