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/* $Id: aeMB2_ctrl.v,v 1.7 2008-05-11 13:50:50 sybreon Exp $
**
** AEMB2 EDK 6.2 COMPATIBLE CORE
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
*/
/**
 * Instruction Decode & Control
 * @file aeMB2_ctrl.v
 
 * This is the data decoder that will control the command signals and
   operand fetch.
 
 */
`timescale  1ns/1ps
module aeMB2_ctrl (/*AUTOARG*/
   // Outputs
   opa_of, opb_of, opd_of, opc_of, ra_of, rd_of, imm_of, rd_ex,
   mux_of, mux_ex, hzd_bpc, hzd_fwd,
   // Inputs
   opa_if, opb_if, opd_if, brk_if, bra_ex, rpc_if, alu_ex, ich_dat,
   exc_dwb, exc_ill, exc_iwb, gclk, grst, dena, iena, gpha
   );
   parameter AEMB_HTX = 1;
 
   // EX CONTROL
   output [31:0] opa_of;
   output [31:0] opb_of;
   output [31:0] opd_of;
   output [5:0]  opc_of;
   output [4:0]  ra_of,
                 //rb_of,
                 rd_of;
   output [15:0] imm_of;
   output [4:0]   rd_ex;
 
   // REGS
   input [31:0]  opa_if,
                 opb_if,
                 opd_if;
 
   // WB CONTROL
   output [2:0]  mux_of,
                 mux_ex;
 
   // INTERNAL
   input [1:0]    brk_if;
   input [1:0]    bra_ex;
   input [31:2]  rpc_if;
   input [31:0]  alu_ex;
   input [31:0]  ich_dat;
 
   input [1:0]    exc_dwb;
   input         exc_ill;
   input         exc_iwb;
 
   output        hzd_bpc;
   output        hzd_fwd;
 
   // SYSTEM
   input         gclk,
                 grst,
                 dena,
                 iena,
                 gpha;
 
   /*AUTOREG*/
   // Beginning of automatic regs (for this module's undeclared outputs)
   reg [15:0]            imm_of;
   reg [2:0]             mux_ex;
   reg [2:0]             mux_of;
   reg [31:0]            opa_of;
   reg [31:0]            opb_of;
   reg [5:0]             opc_of;
   reg [31:0]            opd_of;
   reg [4:0]             ra_of;
   reg [4:0]             rd_ex;
   reg [4:0]             rd_of;
   // End of automatics
 
   wire                 fINT, fXCE;
   wire [31:0]           wXCEOP = 32'hBA2E0020; // Vector 0x20
   wire [31:0]           wINTOP = 32'hB9CD0010; // Vector 0x10   
   //wire [31:0]                wNOPOP = 32'h88000000; // branch-no-delay/stall
 
   wire [1:0]            mux_opa, mux_opb, mux_opd;
 
   // translate signals
   wire [4:0]            wRD, wRA, wRB;
   wire [5:0]            wOPC;
   wire [15:0]           wIMM;
   wire [31:0]           imm_if;
 
   assign               {wOPC, wRD, wRA, wIMM} = (fXCE) ? wXCEOP :
                                                 (fINT) ? wINTOP :
                                                 ich_dat;
   assign               wRB = wIMM[15:11];
 
   // decode main opgroups
 
   //wire               fSFT = (wOPC == 6'o44);
   //wire               fLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);      
   wire                 fMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
   wire                 fBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
   //wire               fDIV = (wOPC == 6'o22);   
   wire                 fRTD = (wOPC == 6'o55);
   wire                 fBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
   wire                 fBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
   //wire               fBRA = fBRU & wRA[3];      
   wire                 fIMM = (wOPC == 6'o54);
   wire                 fMOV = (wOPC == 6'o45);
   wire                 fLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);
   wire                 fSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);
   //wire               fLDST = (wOPC[5:4] == 2'o3);   
   //wire               fPUT = (wOPC == 6'o33) & wRB[4];
   wire                 fGET = (wOPC == 6'o33) & !wRB[4];
 
 
   // control signals
   localparam [2:0]      MUX_SFR = 3'o7,
                        MUX_BSF = 3'o6,
                        MUX_MUL = 3'o5,
                        MUX_MEM = 3'o4,
 
                        MUX_RPC = 3'o2,
                        MUX_ALU = 3'o1,
                        MUX_NOP = 3'o0;
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        imm_of <= 16'h0;
        mux_of <= 3'h0;
        opc_of <= 6'h0;
        ra_of <= 5'h0;
        rd_of <= 5'h0;
        // End of automatics
     end else if (dena) begin
 
        mux_of <= #1
                  (hzd_bpc | hzd_fwd | fSTR | fRTD | fBCC) ? MUX_NOP :
                  (fLOD | fGET) ? MUX_MEM :
                  (fMOV) ? MUX_SFR :
                  (fMUL) ? MUX_MUL :
                  (fBSF) ? MUX_BSF :
                  (fBRU) ? MUX_RPC :
                  MUX_ALU;
 
        opc_of <= #1
                  (hzd_bpc | hzd_fwd) ? 6'o42 : // XOR (SKIP) 
                  wOPC;
 
        rd_of <= #1 wRD;
        ra_of <= #1 wRA;
        imm_of <= #1 wIMM;
 
     end // if (dena)
 
   // immediate implementation
   reg [15:0]            rIMM0, rIMM1;
   reg                  rFIM0, rFIM1;
   //wire               wFIMH = (gpha & AEMB_HTX[0]) ? rFIM1 : rFIM0;   
   //wire [15:0]                wIMMH = (gpha & AEMB_HTX[0]) ? rIMM1 : rIMM0;
 
   assign               imm_if[15:0] = wIMM;
   assign               imm_if[31:16] = (rFIM1) ? rIMM1 :
                                        {(16){wIMM[15]}};
 
   // BARREL IMM
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rFIM0 <= 1'h0;
        rFIM1 <= 1'h0;
        rIMM0 <= 16'h0;
        rIMM1 <= 16'h0;
        // End of automatics
     end else if (dena) begin
        rFIM1 <= #1 rFIM0;
        rFIM0 <= #1 fIMM & !hzd_bpc;
 
        rIMM1 <= #1 rIMM0;
        rIMM0 <= #1 wIMM;
     end
 
   wire       fBRKI = (opc_of == 6'o56) & (ra_of[4:0] == 5'hD);
   reg [2:0]  rINT;
 
   assign fINT = brk_if[0] & (gpha ^ rINT[2]) & !rFIM1;
   //assign fXCE = brk_if[1];
   assign fXCE = |{exc_ill, exc_iwb, exc_dwb};
   // & ((gpha & !rFIM1) | (!gpha & rFIM0));   
 
   // Distribute interrupts over the phases.
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        rINT <= 3'h0;
        // End of automatics
     end else if (dena) begin
        rINT <= #1 {rINT[1:0],rINT[0] ^ fBRKI};
     end
 
   // operand latch   
   reg                  wrb_ex;
   reg                  fwd_ex;
   reg [2:0]             mux_mx;
 
   wire                 opb_fwd, opa_fwd, opd_fwd;
 
   assign               mux_opb = {wOPC[3], opb_fwd};
   assign               opb_fwd = ((wRB ^ rd_ex) == 5'd0) & // RB forwarding needed
                                  fwd_ex & wrb_ex;
 
   assign               mux_opa = {(fBRU|fBCC), opa_fwd};
   assign               opa_fwd = ((wRA ^ rd_ex) == 5'd0) & // RA forwarding needed
                                  fwd_ex & wrb_ex;
 
   assign               mux_opd = {fBCC, opd_fwd};
   assign               opd_fwd = (( ((wRA ^ rd_ex) == 5'd0) & fBCC) | // RA forwarding
                                   ( ((wRD ^ rd_ex) == 5'd0) & fSTR)) & // RD forwarding
                                  fwd_ex & wrb_ex;
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        fwd_ex <= 1'h0;
        mux_ex <= 3'h0;
        mux_mx <= 3'h0;
        rd_ex <= 5'h0;
        wrb_ex <= 1'h0;
        // End of automatics
     end else if (dena) begin
        wrb_ex <= #1 |rd_of & |mux_of; // FIXME: check mux      
        fwd_ex <= #1 |mux_of; // FIXME: check mux
 
        mux_mx <= #1 mux_ex;
        mux_ex <= #1 mux_of;
        rd_ex <= #1 rd_of;
     end
 
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        opa_of <= 32'h0;
        opb_of <= 32'h0;
        opd_of <= 32'h0;
        // End of automatics
 
     end else if (dena) begin
 
        case (mux_opd)
          2'o2: opd_of <= #1 opa_if; // BCC
          2'o1: opd_of <= #1 alu_ex; // FWD
          2'o0: opd_of <= #1 opd_if; // SXX
          2'o3: opd_of <= #1 alu_ex; // FWD               
        endcase // case (mux_opd)
 
        case (mux_opb)
          2'o0: opb_of <= #1 opb_if;
          2'o1: opb_of <= #1 alu_ex;
          2'o2: opb_of <= #1 imm_if;
          2'o3: opb_of <= #1 imm_if;
        endcase // case (mux_opb)
 
        case (mux_opa)
          2'o0: opa_of <= #1 opa_if;
          2'o1: opa_of <= #1 alu_ex;
          2'o2: opa_of <= #1 {rpc_if, 2'o0};
          2'o3: opa_of <= #1 {rpc_if, 2'o0};
        endcase // case (mux_opa)
 
     end // if (dena)
 
   // Hazard Detection
   //wire               wFMUL = (mux_ex == MUX_MUL);
   //wire               wFBSF = (mux_ex == MUX_BSF);
   //wire               wFMEM = (mux_ex == MUX_MEM);
   //wire               wFMOV = (mux_ex == MUX_SFR);   
 
   assign               hzd_fwd = (opd_fwd | opa_fwd | opb_fwd) & mux_ex[2];
                                  //(wFMUL | wFBSF | wFMEM | wFMOV);
   assign               hzd_bpc = (bra_ex[1] & !bra_ex[0]);
 
endmodule // aeMB2_ctrl

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [verilog/] [src/] [aeMB2_ctrl.v] - Blame information for rev 16

Line No.	Rev	Author	Line
1	16	alirezamon	`/* $Id: aeMB2_ctrl.v,v 1.7 2008-05-11 13:50:50 sybreon Exp $`
2			`**`
3			`** AEMB2 EDK 6.2 COMPATIBLE CORE`
4			`** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>`
5			`**`
6			`** This file is part of AEMB.`
7			`**`
8			`** AEMB is free software: you can redistribute it and/or modify it`
9			`** under the terms of the GNU Lesser General Public License as`
10			`** published by the Free Software Foundation, either version 3 of the`
11			`** License, or (at your option) any later version.`
12			`**`
13			`** AEMB is distributed in the hope that it will be useful, but WITHOUT`
14			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
15			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
16			`** Public License for more details.`
17			`**`
18			`** You should have received a copy of the GNU Lesser General Public`
19			` License along with AEMB. If not, see <http:www.gnu.org/licenses/>.`
20			`*/`
21			`/**`
22			`* Instruction Decode & Control`
23			`* @file aeMB2_ctrl.v`
24
25			`* This is the data decoder that will control the command signals and`
26			`operand fetch.`
27
28			`*/`
29			`timescale 1ns/1ps
30			`module aeMB2_ctrl (/AUTOARG/`
31			`// Outputs`
32			`opa_of, opb_of, opd_of, opc_of, ra_of, rd_of, imm_of, rd_ex,`
33			`mux_of, mux_ex, hzd_bpc, hzd_fwd,`
34			`// Inputs`
35			`opa_if, opb_if, opd_if, brk_if, bra_ex, rpc_if, alu_ex, ich_dat,`
36			`exc_dwb, exc_ill, exc_iwb, gclk, grst, dena, iena, gpha`
37			`);`
38			`parameter AEMB_HTX = 1;`
39
40			`// EX CONTROL`
41			`output [31:0] opa_of;`
42			`output [31:0] opb_of;`
43			`output [31:0] opd_of;`
44			`output [5:0] opc_of;`
45			`output [4:0] ra_of,`
46			`//rb_of,`
47			`rd_of;`
48			`output [15:0] imm_of;`
49			`output [4:0] rd_ex;`
50
51			`// REGS`
52			`input [31:0] opa_if,`
53			`opb_if,`
54			`opd_if;`
55
56			`// WB CONTROL`
57			`output [2:0] mux_of,`
58			`mux_ex;`
59
60			`// INTERNAL`
61			`input [1:0] brk_if;`
62			`input [1:0] bra_ex;`
63			`input [31:2] rpc_if;`
64			`input [31:0] alu_ex;`
65			`input [31:0] ich_dat;`
66
67			`input [1:0] exc_dwb;`
68			`input exc_ill;`
69			`input exc_iwb;`
70
71			`output hzd_bpc;`
72			`output hzd_fwd;`
73
74			`// SYSTEM`
75			`input gclk,`
76			`grst,`
77			`dena,`
78			`iena,`
79			`gpha;`
80
81			`/AUTOREG/`
82			`// Beginning of automatic regs (for this module's undeclared outputs)`
83			`reg [15:0] imm_of;`
84			`reg [2:0] mux_ex;`
85			`reg [2:0] mux_of;`
86			`reg [31:0] opa_of;`
87			`reg [31:0] opb_of;`
88			`reg [5:0] opc_of;`
89			`reg [31:0] opd_of;`
90			`reg [4:0] ra_of;`
91			`reg [4:0] rd_ex;`
92			`reg [4:0] rd_of;`
93			`// End of automatics`
94
95			`wire fINT, fXCE;`
96			`wire [31:0] wXCEOP = 32'hBA2E0020; // Vector 0x20`
97			`wire [31:0] wINTOP = 32'hB9CD0010; // Vector 0x10`
98			`//wire [31:0] wNOPOP = 32'h88000000; // branch-no-delay/stall`
99
100			`wire [1:0] mux_opa, mux_opb, mux_opd;`
101
102			`// translate signals`
103			`wire [4:0] wRD, wRA, wRB;`
104			`wire [5:0] wOPC;`
105			`wire [15:0] wIMM;`
106			`wire [31:0] imm_if;`
107
108			`assign {wOPC, wRD, wRA, wIMM} = (fXCE) ? wXCEOP :`
109			`(fINT) ? wINTOP :`
110			`ich_dat;`
111			`assign wRB = wIMM[15:11];`
112
113			`// decode main opgroups`
114
115			`//wire fSFT = (wOPC == 6'o44);`
116			`//wire fLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);`
117			`wire fMUL = (wOPC == 6'o20) \| (wOPC == 6'o30);`
118			`wire fBSF = (wOPC == 6'o21) \| (wOPC == 6'o31);`
119			`//wire fDIV = (wOPC == 6'o22);`
120			`wire fRTD = (wOPC == 6'o55);`
121			`wire fBCC = (wOPC == 6'o47) \| (wOPC == 6'o57);`
122			`wire fBRU = (wOPC == 6'o46) \| (wOPC == 6'o56);`
123			`//wire fBRA = fBRU & wRA[3];`
124			`wire fIMM = (wOPC == 6'o54);`
125			`wire fMOV = (wOPC == 6'o45);`
126			`wire fLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);`
127			`wire fSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);`
128			`//wire fLDST = (wOPC[5:4] == 2'o3);`
129			`//wire fPUT = (wOPC == 6'o33) & wRB[4];`
130			`wire fGET = (wOPC == 6'o33) & !wRB[4];`
131
132
133			`// control signals`
134			`localparam [2:0] MUX_SFR = 3'o7,`
135			`MUX_BSF = 3'o6,`
136			`MUX_MUL = 3'o5,`
137			`MUX_MEM = 3'o4,`
138
139			`MUX_RPC = 3'o2,`
140			`MUX_ALU = 3'o1,`
141			`MUX_NOP = 3'o0;`
142
143			`always @(posedge gclk)`
144			`if (grst) begin`
145			`/AUTORESET/`
146			`// Beginning of autoreset for uninitialized flops`
147			`imm_of <= 16'h0;`
148			`mux_of <= 3'h0;`
149			`opc_of <= 6'h0;`
150			`ra_of <= 5'h0;`
151			`rd_of <= 5'h0;`
152			`// End of automatics`
153			`end else if (dena) begin`
154
155			`mux_of <= #1`
156			`(hzd_bpc \| hzd_fwd \| fSTR \| fRTD \| fBCC) ? MUX_NOP :`
157			`(fLOD \| fGET) ? MUX_MEM :`
158			`(fMOV) ? MUX_SFR :`
159			`(fMUL) ? MUX_MUL :`
160			`(fBSF) ? MUX_BSF :`
161			`(fBRU) ? MUX_RPC :`
162			`MUX_ALU;`
163
164			`opc_of <= #1`
165			`(hzd_bpc \| hzd_fwd) ? 6'o42 : // XOR (SKIP)`
166			`wOPC;`
167
168			`rd_of <= #1 wRD;`
169			`ra_of <= #1 wRA;`
170			`imm_of <= #1 wIMM;`
171
172			`end // if (dena)`
173
174			`// immediate implementation`
175			`reg [15:0] rIMM0, rIMM1;`
176			`reg rFIM0, rFIM1;`
177			`//wire wFIMH = (gpha & AEMB_HTX[0]) ? rFIM1 : rFIM0;`
178			`//wire [15:0] wIMMH = (gpha & AEMB_HTX[0]) ? rIMM1 : rIMM0;`
179
180			`assign imm_if[15:0] = wIMM;`
181			`assign imm_if[31:16] = (rFIM1) ? rIMM1 :`
182			`{(16){wIMM[15]}};`
183
184			`// BARREL IMM`
185			`always @(posedge gclk)`
186			`if (grst) begin`
187			`/AUTORESET/`
188			`// Beginning of autoreset for uninitialized flops`
189			`rFIM0 <= 1'h0;`
190			`rFIM1 <= 1'h0;`
191			`rIMM0 <= 16'h0;`
192			`rIMM1 <= 16'h0;`
193			`// End of automatics`
194			`end else if (dena) begin`
195			`rFIM1 <= #1 rFIM0;`
196			`rFIM0 <= #1 fIMM & !hzd_bpc;`
197
198			`rIMM1 <= #1 rIMM0;`
199			`rIMM0 <= #1 wIMM;`
200			`end`
201
202			`wire fBRKI = (opc_of == 6'o56) & (ra_of[4:0] == 5'hD);`
203			`reg [2:0] rINT;`
204
205			`assign fINT = brk_if[0] & (gpha ^ rINT[2]) & !rFIM1;`
206			`//assign fXCE = brk_if[1];`
207			`assign fXCE = \|{exc_ill, exc_iwb, exc_dwb};`
208			`// & ((gpha & !rFIM1) \| (!gpha & rFIM0));`
209
210			`// Distribute interrupts over the phases.`
211			`always @(posedge gclk)`
212			`if (grst) begin`
213			`/AUTORESET/`
214			`// Beginning of autoreset for uninitialized flops`
215			`rINT <= 3'h0;`
216			`// End of automatics`
217			`end else if (dena) begin`
218			`rINT <= #1 {rINT[1:0],rINT[0] ^ fBRKI};`
219			`end`
220
221			`// operand latch`
222			`reg wrb_ex;`
223			`reg fwd_ex;`
224			`reg [2:0] mux_mx;`
225
226			`wire opb_fwd, opa_fwd, opd_fwd;`
227
228			`assign mux_opb = {wOPC[3], opb_fwd};`
229			`assign opb_fwd = ((wRB ^ rd_ex) == 5'd0) & // RB forwarding needed`
230			`fwd_ex & wrb_ex;`
231
232			`assign mux_opa = {(fBRU\|fBCC), opa_fwd};`
233			`assign opa_fwd = ((wRA ^ rd_ex) == 5'd0) & // RA forwarding needed`
234			`fwd_ex & wrb_ex;`
235
236			`assign mux_opd = {fBCC, opd_fwd};`
237			`assign opd_fwd = (( ((wRA ^ rd_ex) == 5'd0) & fBCC) \| // RA forwarding`
238			`( ((wRD ^ rd_ex) == 5'd0) & fSTR)) & // RD forwarding`
239			`fwd_ex & wrb_ex;`
240
241			`always @(posedge gclk)`
242			`if (grst) begin`
243			`/AUTORESET/`
244			`// Beginning of autoreset for uninitialized flops`
245			`fwd_ex <= 1'h0;`
246			`mux_ex <= 3'h0;`
247			`mux_mx <= 3'h0;`
248			`rd_ex <= 5'h0;`
249			`wrb_ex <= 1'h0;`
250			`// End of automatics`
251			`end else if (dena) begin`
252			`wrb_ex <= #1 \|rd_of & \|mux_of; // FIXME: check mux`
253			`fwd_ex <= #1 \|mux_of; // FIXME: check mux`
254
255			`mux_mx <= #1 mux_ex;`
256			`mux_ex <= #1 mux_of;`
257			`rd_ex <= #1 rd_of;`
258			`end`
259
260			`always @(posedge gclk)`
261			`if (grst) begin`
262			`/AUTORESET/`
263			`// Beginning of autoreset for uninitialized flops`
264			`opa_of <= 32'h0;`
265			`opb_of <= 32'h0;`
266			`opd_of <= 32'h0;`
267			`// End of automatics`
268
269			`end else if (dena) begin`
270
271			`case (mux_opd)`
272			`2'o2: opd_of <= #1 opa_if; // BCC`
273			`2'o1: opd_of <= #1 alu_ex; // FWD`
274			`2'o0: opd_of <= #1 opd_if; // SXX`
275			`2'o3: opd_of <= #1 alu_ex; // FWD`
276			`endcase // case (mux_opd)`
277
278			`case (mux_opb)`
279			`2'o0: opb_of <= #1 opb_if;`
280			`2'o1: opb_of <= #1 alu_ex;`
281			`2'o2: opb_of <= #1 imm_if;`
282			`2'o3: opb_of <= #1 imm_if;`
283			`endcase // case (mux_opb)`
284
285			`case (mux_opa)`
286			`2'o0: opa_of <= #1 opa_if;`
287			`2'o1: opa_of <= #1 alu_ex;`
288			`2'o2: opa_of <= #1 {rpc_if, 2'o0};`
289			`2'o3: opa_of <= #1 {rpc_if, 2'o0};`
290			`endcase // case (mux_opa)`
291
292			`end // if (dena)`
293
294			`// Hazard Detection`
295			`//wire wFMUL = (mux_ex == MUX_MUL);`
296			`//wire wFBSF = (mux_ex == MUX_BSF);`
297			`//wire wFMEM = (mux_ex == MUX_MEM);`
298			`//wire wFMOV = (mux_ex == MUX_SFR);`
299
300			`assign hzd_fwd = (opd_fwd \| opa_fwd \| opb_fwd) & mux_ex[2];`
301			`//(wFMUL \| wFBSF \| wFMEM \| wFMOV);`
302			`assign hzd_bpc = (bra_ex[1] & !bra_ex[0]);`
303
304			`endmodule // aeMB2_ctrl`