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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [verilog/] [src/] [aeMB2_dparam.v] - Blame information for rev 16

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1 16 alirezamon
/* $Id: aeMB2_dparam.v,v 1.1 2008-04-26 17:57:43 sybreon Exp $
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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** This file is part of AEMB.
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
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** Public License for more details.
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**
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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*/
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/**
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 * @file aeMB2_dparam.v
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 * @brief On-chip dual-port asynchronous SRAM.
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 * This will be implemented as distributed RAM with one read/write
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   port and one read-only port.
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 */
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// 32x64 = 77
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// 64x32 = 146
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`timescale  1ns/1ps
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module aeMB2_dparam (/*AUTOARG*/
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   // Outputs
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   dat_o, xdat_o,
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   // Inputs
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   adr_i, dat_i, wre_i, xadr_i, xdat_i, xwre_i, clk_i, ena_i
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   ) ;
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   parameter AW = 5; // 32
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   parameter DW = 2; // x2
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   // PORT A - READ/WRITE
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   output [DW-1:0] dat_o;
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   input [AW-1:0]  adr_i;
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   input [DW-1:0]  dat_i;
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   input           wre_i;
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   // PORT X - READ ONLY
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   output [DW-1:0] xdat_o;
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   input [AW-1:0]  xadr_i;
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   input [DW-1:0]  xdat_i;
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   input           xwre_i;
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   // SYSCON
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   input           clk_i,
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                   ena_i;
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   /*AUTOREG*/
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   reg [DW-1:0]    rRAM [(1<<AW)-1:0];
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   always @(posedge clk_i)
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     if (wre_i) rRAM[adr_i] <= #1 dat_i;
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   assign          dat_o = rRAM[adr_i];
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   assign          xdat_o = rRAM[xadr_i];
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   // --- SIMULATION ONLY ------------------------------------
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   // synopsys translate_off
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   integer         i;
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   initial begin
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      for (i=0; i<(1<<AW); i=i+1)
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        begin
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           rRAM[i] <= {(DW){1'b0}};
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end
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   end
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   // synopsys translate_on
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endmodule // aeMB2_dparam
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/*
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 $Log: not supported by cvs2svn $
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 Revision 1.1  2008/04/20 16:33:39  sybreon
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 Initial import.
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*/

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