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alirezamon |
/* $Id: aeMB2_edk62.v,v 1.8 2008-05-01 08:32:58 sybreon Exp $
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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** This file is part of AEMB.
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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**
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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*/
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/**
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* Top Level Core
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* @file aeMB2_edk62.v
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* This implements an EDK 6.2 software compatible core. It implements
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all the software instructions except for division and cache writes.
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*/
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`timescale 1ns/1ps
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module aeMB2_edk62 (/*AUTOARG*/
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// Outputs
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xwb_wre_o, xwb_tag_o, xwb_stb_o, xwb_sel_o, xwb_dat_o, xwb_cyc_o,
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xwb_adr_o, iwb_wre_o, iwb_tag_o, iwb_stb_o, iwb_sel_o, iwb_cyc_o,
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iwb_adr_o, dwb_wre_o, dwb_tag_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
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dwb_cyc_o, dwb_adr_o,
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// Inputs
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xwb_dat_i, xwb_ack_i, sys_rst_i, sys_int_i, sys_ena_i, sys_clk_i,
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iwb_dat_i, iwb_ack_i, dwb_dat_i, dwb_ack_i
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);
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// BUS WIDTHS
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parameter AEMB_IWB = 32; ///< INST bus width
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parameter AEMB_DWB = 32; ///< DATA bus width
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parameter AEMB_XWB = 7; ///< XCEL bus width
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// CACHE PARAMETERS
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parameter AEMB_ICH = 11; ///< instruction cache size
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parameter AEMB_IDX = 6; ///< cache index size
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// OPTIONAL HARDWARE
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parameter AEMB_BSF = 1; ///< optional barrel shift
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parameter AEMB_MUL = 1; ///< optional multiplier
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parameter AEMB_DIV = 0; ///< optional divider (future)
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parameter AEMB_FPU = 0; ///< optional floating point unit (future)
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// DEPRECATED PARAMETERS
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localparam AEMB_XSL = 1; ///< implement XSL bus
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localparam AEMB_HTX = 1; ///< hardware thread extension
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [AEMB_DWB-1:2] dwb_adr_o; // From memif0 of aeMB2_memif.v
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output dwb_cyc_o; // From memif0 of aeMB2_memif.v
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output [31:0] dwb_dat_o; // From memif0 of aeMB2_memif.v
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output [3:0] dwb_sel_o; // From memif0 of aeMB2_memif.v
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output dwb_stb_o; // From memif0 of aeMB2_memif.v
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output dwb_tag_o; // From memif0 of aeMB2_memif.v
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output dwb_wre_o; // From memif0 of aeMB2_memif.v
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output [AEMB_IWB-1:2] iwb_adr_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_cyc_o; // From iwbif0 of aeMB2_iwbif.v
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output [3:0] iwb_sel_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_stb_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_tag_o; // From iwbif0 of aeMB2_iwbif.v
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output iwb_wre_o; // From iwbif0 of aeMB2_iwbif.v
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output [AEMB_XWB-1:2] xwb_adr_o; // From memif0 of aeMB2_memif.v
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output xwb_cyc_o; // From memif0 of aeMB2_memif.v
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output [31:0] xwb_dat_o; // From memif0 of aeMB2_memif.v
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output [3:0] xwb_sel_o; // From memif0 of aeMB2_memif.v
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output xwb_stb_o; // From memif0 of aeMB2_memif.v
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output xwb_tag_o; // From memif0 of aeMB2_memif.v
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output xwb_wre_o; // From memif0 of aeMB2_memif.v
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// End of automatics
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input dwb_ack_i; // To memif0 of aeMB2_memif.v
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input [31:0] dwb_dat_i; // To memif0 of aeMB2_memif.v
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input iwb_ack_i; // To iche0 of aeMB2_iche.v, ...
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input [31:0] iwb_dat_i; // To iche0 of aeMB2_iche.v, ...
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input sys_clk_i; // To pip0 of aeMB2_pipe.v
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input sys_ena_i; // To pip0 of aeMB2_pipe.v
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input sys_int_i; // To pip0 of aeMB2_pipe.v
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input sys_rst_i; // To pip0 of aeMB2_pipe.v
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input xwb_ack_i; // To memif0 of aeMB2_memif.v
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input [31:0] xwb_dat_i; // To memif0 of aeMB2_memif.v
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [31:0] alu_ex; // From exec0 of aeMB2_exec.v
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wire [31:0] alu_mx; // From exec0 of aeMB2_exec.v
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wire [31:2] bpc_ex; // From exec0 of aeMB2_exec.v
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wire [1:0] bra_ex; // From brcc0 of aeMB2_brcc.v
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wire [1:0] brk_if; // From pip0 of aeMB2_pipe.v
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wire [31:0] bsf_mx; // From exec0 of aeMB2_exec.v
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wire dena; // From pip0 of aeMB2_pipe.v
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wire dwb_fb; // From memif0 of aeMB2_memif.v
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wire [31:0] dwb_mx; // From memif0 of aeMB2_memif.v
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wire fet_fb; // From iwbif0 of aeMB2_iwbif.v
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wire gclk; // From pip0 of aeMB2_pipe.v
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wire gpha; // From pip0 of aeMB2_pipe.v
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wire grst; // From pip0 of aeMB2_pipe.v
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wire hzd_bpc; // From ctrl0 of aeMB2_ctrl.v
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wire hzd_fwd; // From ctrl0 of aeMB2_ctrl.v
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wire [AEMB_IWB-1:2] ich_adr; // From iwbif0 of aeMB2_iwbif.v
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wire [31:0] ich_dat; // From iche0 of aeMB2_iche.v
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wire ich_fb; // From iche0 of aeMB2_iche.v
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wire ich_hit; // From iche0 of aeMB2_iche.v
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wire iena; // From pip0 of aeMB2_pipe.v
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wire [15:0] imm_of; // From ctrl0 of aeMB2_ctrl.v
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wire [31:2] mem_ex; // From exec0 of aeMB2_exec.v
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wire [7:0] msr_ex; // From exec0 of aeMB2_exec.v
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wire [31:0] mul_mx; // From exec0 of aeMB2_exec.v
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wire [2:0] mux_ex; // From ctrl0 of aeMB2_ctrl.v
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wire [2:0] mux_of; // From ctrl0 of aeMB2_ctrl.v
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wire [31:0] opa_if; // From regs0 of aeMB2_regs.v
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wire [31:0] opa_of; // From ctrl0 of aeMB2_ctrl.v
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wire [31:0] opb_if; // From regs0 of aeMB2_regs.v
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wire [31:0] opb_of; // From ctrl0 of aeMB2_ctrl.v
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wire [5:0] opc_of; // From ctrl0 of aeMB2_ctrl.v
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wire [31:0] opd_if; // From regs0 of aeMB2_regs.v
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wire [31:0] opd_of; // From ctrl0 of aeMB2_ctrl.v
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wire [4:0] ra_of; // From ctrl0 of aeMB2_ctrl.v
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wire [4:0] rd_ex; // From ctrl0 of aeMB2_ctrl.v
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wire [4:0] rd_of; // From ctrl0 of aeMB2_ctrl.v
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wire [31:2] rpc_if; // From iwbif0 of aeMB2_iwbif.v
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wire [31:2] rpc_mx; // From iwbif0 of aeMB2_iwbif.v
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wire [3:0] sel_mx; // From memif0 of aeMB2_memif.v
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wire [31:0] sfr_mx; // From exec0 of aeMB2_exec.v
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wire xwb_fb; // From memif0 of aeMB2_memif.v
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wire [31:0] xwb_mx; // From memif0 of aeMB2_memif.v
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// End of automatics
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/*AUTOREG*/
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aeMB2_pipe
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pip0
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(/*AUTOINST*/
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// Outputs
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.brk_if (brk_if[1:0]),
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.gpha (gpha),
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.gclk (gclk),
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.grst (grst),
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.dena (dena),
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.iena (iena),
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// Inputs
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.bra_ex (bra_ex[1:0]),
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.dwb_fb (dwb_fb),
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.xwb_fb (xwb_fb),
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.ich_fb (ich_fb),
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.fet_fb (fet_fb),
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.msr_ex (msr_ex[3:0]),
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.sys_clk_i (sys_clk_i),
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.sys_int_i (sys_int_i),
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.sys_rst_i (sys_rst_i),
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.sys_ena_i (sys_ena_i));
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aeMB2_iche
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#(/*AUTOINSTPARAM*/
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// Parameters
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.AEMB_IWB (AEMB_IWB),
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.AEMB_ICH (AEMB_ICH),
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.AEMB_IDX (AEMB_IDX),
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.AEMB_HTX (AEMB_HTX))
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iche0
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(/*AUTOINST*/
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// Outputs
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.ich_dat (ich_dat[31:0]),
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.ich_hit (ich_hit),
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.ich_fb (ich_fb),
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// Inputs
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.ich_adr (ich_adr[AEMB_IWB-1:2]),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.iwb_ack_i (iwb_ack_i),
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.gclk (gclk),
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.grst (grst),
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.iena (iena),
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.gpha (gpha));
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aeMB2_iwbif
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#(/*AUTOINSTPARAM*/
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// Parameters
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.AEMB_IWB (AEMB_IWB),
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.AEMB_HTX (AEMB_HTX))
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iwbif0
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(/*AUTOINST*/
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// Outputs
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.iwb_adr_o (iwb_adr_o[AEMB_IWB-1:2]),
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.iwb_stb_o (iwb_stb_o),
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.iwb_sel_o (iwb_sel_o[3:0]),
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.iwb_wre_o (iwb_wre_o),
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.iwb_cyc_o (iwb_cyc_o),
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.iwb_tag_o (iwb_tag_o),
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.ich_adr (ich_adr[AEMB_IWB-1:2]),
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.fet_fb (fet_fb),
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.rpc_if (rpc_if[31:2]),
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.rpc_mx (rpc_mx[31:2]),
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// Inputs
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.iwb_ack_i (iwb_ack_i),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.ich_hit (ich_hit),
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.msr_ex (msr_ex[7:5]),
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.hzd_bpc (hzd_bpc),
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.hzd_fwd (hzd_fwd),
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.bra_ex (bra_ex[1:0]),
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.bpc_ex (bpc_ex[31:2]),
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.gclk (gclk),
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.grst (grst),
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.dena (dena),
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.iena (iena),
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.gpha (gpha));
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aeMB2_ctrl
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#(/*AUTOINSTPARAM*/
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// Parameters
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.AEMB_HTX (AEMB_HTX))
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ctrl0
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(/*AUTOINST*/
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// Outputs
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.opa_of (opa_of[31:0]),
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.opb_of (opb_of[31:0]),
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.opd_of (opd_of[31:0]),
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.opc_of (opc_of[5:0]),
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.ra_of (ra_of[4:0]),
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.rd_of (rd_of[4:0]),
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.imm_of (imm_of[15:0]),
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.rd_ex (rd_ex[4:0]),
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.mux_of (mux_of[2:0]),
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.mux_ex (mux_ex[2:0]),
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.hzd_bpc (hzd_bpc),
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.hzd_fwd (hzd_fwd),
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// Inputs
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.opa_if (opa_if[31:0]),
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.opb_if (opb_if[31:0]),
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.opd_if (opd_if[31:0]),
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.brk_if (brk_if[1:0]),
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.bra_ex (bra_ex[1:0]),
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| 244 |
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.rpc_if (rpc_if[31:2]),
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| 245 |
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.alu_ex (alu_ex[31:0]),
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.ich_dat (ich_dat[31:0]),
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.gclk (gclk),
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.grst (grst),
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.dena (dena),
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.iena (iena),
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.gpha (gpha));
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aeMB2_brcc
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#(/*AUTOINSTPARAM*/
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// Parameters
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.AEMB_HTX (AEMB_HTX))
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brcc0
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(/*AUTOINST*/
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// Outputs
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.bra_ex (bra_ex[1:0]),
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// Inputs
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.opd_of (opd_of[31:0]),
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.ra_of (ra_of[4:0]),
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.rd_of (rd_of[4:0]),
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.opc_of (opc_of[5:0]),
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.gclk (gclk),
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.grst (grst),
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.dena (dena),
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.iena (iena),
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.gpha (gpha));
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aeMB2_exec
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#(/*AUTOINSTPARAM*/
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// Parameters
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|
|
.AEMB_IWB (AEMB_IWB),
|
| 276 |
|
|
.AEMB_DWB (AEMB_DWB),
|
| 277 |
|
|
.AEMB_MUL (AEMB_MUL),
|
| 278 |
|
|
.AEMB_BSF (AEMB_BSF),
|
| 279 |
|
|
.AEMB_HTX (AEMB_HTX))
|
| 280 |
|
|
exec0
|
| 281 |
|
|
(/*AUTOINST*/
|
| 282 |
|
|
// Outputs
|
| 283 |
|
|
.alu_ex (alu_ex[31:0]),
|
| 284 |
|
|
.alu_mx (alu_mx[31:0]),
|
| 285 |
|
|
.bpc_ex (bpc_ex[31:2]),
|
| 286 |
|
|
.bsf_mx (bsf_mx[31:0]),
|
| 287 |
|
|
.mem_ex (mem_ex[31:2]),
|
| 288 |
|
|
.msr_ex (msr_ex[7:0]),
|
| 289 |
|
|
.mul_mx (mul_mx[31:0]),
|
| 290 |
|
|
.sfr_mx (sfr_mx[31:0]),
|
| 291 |
|
|
// Inputs
|
| 292 |
|
|
.dena (dena),
|
| 293 |
|
|
.gclk (gclk),
|
| 294 |
|
|
.gpha (gpha),
|
| 295 |
|
|
.grst (grst),
|
| 296 |
|
|
.imm_of (imm_of[15:0]),
|
| 297 |
|
|
.opa_of (opa_of[31:0]),
|
| 298 |
|
|
.opb_of (opb_of[31:0]),
|
| 299 |
|
|
.opc_of (opc_of[5:0]),
|
| 300 |
|
|
.opd_of (opd_of[31:0]),
|
| 301 |
|
|
.ra_of (ra_of[4:0]),
|
| 302 |
|
|
.rd_of (rd_of[4:0]));
|
| 303 |
|
|
|
| 304 |
|
|
aeMB2_memif
|
| 305 |
|
|
#(/*AUTOINSTPARAM*/
|
| 306 |
|
|
// Parameters
|
| 307 |
|
|
.AEMB_DWB (AEMB_DWB),
|
| 308 |
|
|
.AEMB_XWB (AEMB_XWB),
|
| 309 |
|
|
.AEMB_XSL (AEMB_XSL))
|
| 310 |
|
|
memif0
|
| 311 |
|
|
(/*AUTOINST*/
|
| 312 |
|
|
// Outputs
|
| 313 |
|
|
.dwb_adr_o (dwb_adr_o[AEMB_DWB-1:2]),
|
| 314 |
|
|
.dwb_cyc_o (dwb_cyc_o),
|
| 315 |
|
|
.dwb_dat_o (dwb_dat_o[31:0]),
|
| 316 |
|
|
.dwb_fb (dwb_fb),
|
| 317 |
|
|
.dwb_mx (dwb_mx[31:0]),
|
| 318 |
|
|
.dwb_sel_o (dwb_sel_o[3:0]),
|
| 319 |
|
|
.dwb_stb_o (dwb_stb_o),
|
| 320 |
|
|
.dwb_tag_o (dwb_tag_o),
|
| 321 |
|
|
.dwb_wre_o (dwb_wre_o),
|
| 322 |
|
|
.sel_mx (sel_mx[3:0]),
|
| 323 |
|
|
.xwb_adr_o (xwb_adr_o[AEMB_XWB-1:2]),
|
| 324 |
|
|
.xwb_cyc_o (xwb_cyc_o),
|
| 325 |
|
|
.xwb_dat_o (xwb_dat_o[31:0]),
|
| 326 |
|
|
.xwb_fb (xwb_fb),
|
| 327 |
|
|
.xwb_mx (xwb_mx[31:0]),
|
| 328 |
|
|
.xwb_sel_o (xwb_sel_o[3:0]),
|
| 329 |
|
|
.xwb_stb_o (xwb_stb_o),
|
| 330 |
|
|
.xwb_tag_o (xwb_tag_o),
|
| 331 |
|
|
.xwb_wre_o (xwb_wre_o),
|
| 332 |
|
|
// Inputs
|
| 333 |
|
|
.dena (dena),
|
| 334 |
|
|
.dwb_ack_i (dwb_ack_i),
|
| 335 |
|
|
.dwb_dat_i (dwb_dat_i[31:0]),
|
| 336 |
|
|
.gclk (gclk),
|
| 337 |
|
|
.gpha (gpha),
|
| 338 |
|
|
.grst (grst),
|
| 339 |
|
|
.imm_of (imm_of[15:0]),
|
| 340 |
|
|
.mem_ex (mem_ex[AEMB_DWB-1:2]),
|
| 341 |
|
|
.msr_ex (msr_ex[7:0]),
|
| 342 |
|
|
.opa_of (opa_of[31:0]),
|
| 343 |
|
|
.opb_of (opb_of[1:0]),
|
| 344 |
|
|
.opc_of (opc_of[5:0]),
|
| 345 |
|
|
.opd_of (opd_of[31:0]),
|
| 346 |
|
|
.sfr_mx (sfr_mx[7:5]),
|
| 347 |
|
|
.xwb_ack_i (xwb_ack_i),
|
| 348 |
|
|
.xwb_dat_i (xwb_dat_i[31:0]));
|
| 349 |
|
|
|
| 350 |
|
|
aeMB2_regs
|
| 351 |
|
|
#(/*AUTOINSTPARAM*/
|
| 352 |
|
|
// Parameters
|
| 353 |
|
|
.AEMB_HTX (AEMB_HTX))
|
| 354 |
|
|
regs0
|
| 355 |
|
|
(/*AUTOINST*/
|
| 356 |
|
|
// Outputs
|
| 357 |
|
|
.opa_if (opa_if[31:0]),
|
| 358 |
|
|
.opb_if (opb_if[31:0]),
|
| 359 |
|
|
.opd_if (opd_if[31:0]),
|
| 360 |
|
|
// Inputs
|
| 361 |
|
|
.alu_mx (alu_mx[31:0]),
|
| 362 |
|
|
.bsf_mx (bsf_mx[31:0]),
|
| 363 |
|
|
.dena (dena),
|
| 364 |
|
|
.dwb_mx (dwb_mx[31:0]),
|
| 365 |
|
|
.gclk (gclk),
|
| 366 |
|
|
.gpha (gpha),
|
| 367 |
|
|
.grst (grst),
|
| 368 |
|
|
.ich_dat (ich_dat[31:0]),
|
| 369 |
|
|
.mul_mx (mul_mx[31:0]),
|
| 370 |
|
|
.mux_ex (mux_ex[2:0]),
|
| 371 |
|
|
.mux_of (mux_of[2:0]),
|
| 372 |
|
|
.rd_ex (rd_ex[4:0]),
|
| 373 |
|
|
.rd_of (rd_of[4:0]),
|
| 374 |
|
|
.rpc_mx (rpc_mx[31:2]),
|
| 375 |
|
|
.sel_mx (sel_mx[3:0]),
|
| 376 |
|
|
.sfr_mx (sfr_mx[31:0]),
|
| 377 |
|
|
.xwb_mx (xwb_mx[31:0]));
|
| 378 |
|
|
|
| 379 |
|
|
endmodule // aeMB2_edk62
|
| 380 |
|
|
|
| 381 |
|
|
/*
|
| 382 |
|
|
$Log: not supported by cvs2svn $
|
| 383 |
|
|
Revision 1.7 2008/04/27 19:52:46 sybreon
|
| 384 |
|
|
added iwb_tag_o signal tied to MSR_ICE.
|
| 385 |
|
|
|
| 386 |
|
|
Revision 1.6 2008/04/26 17:57:43 sybreon
|
| 387 |
|
|
Minor performance improvements.
|
| 388 |
|
|
|
| 389 |
|
|
Revision 1.5 2008/04/26 01:11:30 sybreon
|
| 390 |
|
|
Fixed minor typos.
|
| 391 |
|
|
|
| 392 |
|
|
Revision 1.4 2008/04/26 01:09:05 sybreon
|
| 393 |
|
|
Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
|
| 394 |
|
|
|
| 395 |
|
|
Revision 1.3 2008/04/21 12:11:38 sybreon
|
| 396 |
|
|
Passes arithmetic tests with single thread.
|
| 397 |
|
|
|
| 398 |
|
|
Revision 1.2 2008/04/20 16:34:32 sybreon
|
| 399 |
|
|
Basic version with some features left out.
|
| 400 |
|
|
|
| 401 |
|
|
Revision 1.1 2008/04/18 00:21:52 sybreon
|
| 402 |
|
|
Initial import.
|
| 403 |
|
|
*/
|
