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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [verilog/] [src/] [aeMB2_pipe.v] - Blame information for rev 16

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1 16 alirezamon 
/* $Id: aeMB2_pipe.v,v 1.4 2008-05-01 08:32:58 sybreon Exp $
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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** This file is part of AEMB.
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
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** Public License for more details.
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**
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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*/
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/**
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 * System signal controller
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 * @file aeMB2_pipe.v
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 * Generates clock, reset, and enable signals. Hardware clock/reset
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   managers can be instantiated here.
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 */
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`timescale  1ns/1ps
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module aeMB2_pipe (/*AUTOARG*/
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   // Outputs
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   brk_if, gpha, gclk, grst, dena, iena,
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   // Inputs
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   bra_ex, dwb_fb, xwb_fb, ich_fb, fet_fb, msr_ex, exc_dwb, exc_iwb,
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   exc_ill, sys_clk_i, sys_int_i, sys_rst_i, sys_ena_i
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   );
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   parameter AEMB_HTX = 1;
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   output [1:0] brk_if;
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   input [1:0]   bra_ex;
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   input        dwb_fb;
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   input        xwb_fb;
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   input        ich_fb;
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   input        fet_fb;
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   input [9:0]   msr_ex;
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   output       gpha,
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                gclk,
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                grst,
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                dena,
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                iena;
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   input [1:0]   exc_dwb;
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   input        exc_iwb;
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   input        exc_ill;
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   input        sys_clk_i,
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                sys_int_i,
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                sys_rst_i,
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                sys_ena_i;
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   /*AUTOREG*/
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   // Beginning of automatic regs (for this module's undeclared outputs)
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   reg [1:0]             brk_if;
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   reg                  gpha;
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   // End of automatics
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   reg [1:0]             rst;
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   reg                  por;
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   reg                  fet;
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   reg                  hit;
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   // Instantiate clock/reset managers
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   assign               gclk = sys_clk_i;
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   assign               grst = !rst[1];
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   // run instruction side pipeline
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   assign               iena = ich_fb &
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                               xwb_fb &
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                               dwb_fb &
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                               sys_ena_i;
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   // run data side pipeline
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   assign               dena = iena;
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   // interrupt process - latches onto any interrupt until it is handled
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   reg                  int_lat; ///< interrupt latch
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   always @(posedge sys_clk_i)
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     if (sys_rst_i) begin
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        /*AUTORESET*/
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        // Beginning of autoreset for uninitialized flops
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        int_lat <= 1'h0;
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        // End of automatics
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     end else begin
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        int_lat <= #1 msr_ex[1] & (int_lat | sys_int_i);
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     end
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   // exception process - exceptions handled immediately
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   wire                 exc_lat; ///< exception latch
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   assign exc_lat = exc_ill | exc_dwb[1];
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   always @(posedge gclk)
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     if (grst) begin
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        /*AUTORESET*/
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        // Beginning of autoreset for uninitialized flops
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        brk_if <= 2'h0;
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        // End of automatics
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     end else if (dena) begin
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        brk_if[1] <= #1 exc_lat & msr_ex[8] & !msr_ex[9]; // HIGH PRIORITY - exception
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        brk_if[0] <= #1 !exc_lat & !msr_ex[9] & !msr_ex[3] & int_lat; // LOW PRIORITY - interrupt (not BIP/EIP)
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     end
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   // RESET DELAY
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   always @(posedge sys_clk_i)
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     if (sys_rst_i) begin
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        /*AUTORESET*/
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        // Beginning of autoreset for uninitialized flops
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        rst <= 2'h0;
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        // End of automatics
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     end else begin
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        rst <= #1 {rst[0], !sys_rst_i};
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     end
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   // PHASE TOGGLE
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   always @(posedge sys_clk_i)
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     if (sys_rst_i) begin
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        /*AUTORESET*/
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        // Beginning of autoreset for uninitialized flops
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        gpha <= 1'h0;
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        // End of automatics
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     end else if (dena | grst) begin
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        gpha <= #1 !gpha;
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     end
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endmodule // aeMB2_pipe
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