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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [verilog/] [src/] [aeMB2_xslif.v] - Blame information for rev 16

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1 16 alirezamon 
/* $Id: aeMB2_xslif.v,v 1.7 2008-04-27 16:41:46 sybreon Exp $
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**
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** AEMB2 EDK 6.2 COMPATIBLE CORE
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** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
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**
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** This file is part of AEMB.
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
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** Public License for more details.
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**
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
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*/
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/**
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 * Accelerator Interface
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 * @file aeMB2_xslif.v
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 * This sets up the Wishbone control signals for the XSL bus
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   interface. This is a non optional bus interface. Bus transactions
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   are independent of the pipeline.
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 */
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 `timescale  1ns/1ps
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module aeMB2_xslif (/*AUTOARG*/
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   // Outputs
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   xwb_adr_o, xwb_dat_o, xwb_sel_o, xwb_tag_o, xwb_stb_o, xwb_cyc_o,
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   xwb_wre_o, xwb_fb, xwb_mx,
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   // Inputs
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   xwb_dat_i, xwb_ack_i, imm_of, opc_of, opa_of, gclk, grst, dena,
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   gpha
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   );
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   parameter AEMB_XSL = 1; ///< implement XSEL bus (ignored)
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   parameter AEMB_XWB = 3; ///< XSEL bus width
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   // XWB control signals
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   output [AEMB_XWB-1:2] xwb_adr_o;
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   output [31:0]          xwb_dat_o;
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   output [3:0]   xwb_sel_o;
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   output                xwb_tag_o;
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   output                xwb_stb_o,
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                         xwb_cyc_o,
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                         xwb_wre_o;
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   input [31:0]   xwb_dat_i;
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   input                 xwb_ack_i;
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   // INTERNAL
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   output                xwb_fb;
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   output [31:0]          xwb_mx;
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   input [15:0]   imm_of;
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   input [5:0]            opc_of;
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   input [31:0]   opa_of;
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   // SYS signals
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   input                 gclk,
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                         grst,
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                         dena,
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                         gpha;
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   /*AUTOREG*/
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   // Beginning of automatic regs (for this module's undeclared outputs)
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   reg [AEMB_XWB-1:2]   xwb_adr_o;
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   reg [31:0]            xwb_dat_o;
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   reg [31:0]            xwb_mx;
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   reg                  xwb_stb_o;
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   reg                  xwb_tag_o;
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   reg                  xwb_wre_o;
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   // End of automatics
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   // FIXME: perform NGET/NPUT non-blocking operations
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   assign               xwb_fb = (xwb_stb_o ~^ xwb_ack_i);
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   // XSEL bus
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   reg [31:0]            xwb_lat;
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   always @(posedge gclk)
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     if (grst) begin
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        /*AUTORESET*/
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        // Beginning of autoreset for uninitialized flops
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        xwb_adr_o <= {(1+(AEMB_XWB-1)-(2)){1'b0}};
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        xwb_dat_o <= 32'h0;
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        xwb_mx <= 32'h0;
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        xwb_tag_o <= 1'h0;
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        xwb_wre_o <= 1'h0;
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        // End of automatics
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     end else if (dena) begin
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        xwb_adr_o <= #1 imm_of[11:0]; // FSLx
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        xwb_wre_o <= #1 imm_of[15]; // PUT
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        xwb_tag_o <= #1 imm_of[13]; // cGET/cPUT
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        xwb_dat_o <= #1 opa_of; // Latch output
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        xwb_mx <= #1 (xwb_ack_i) ?
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                  xwb_dat_i : // stalled from XWB
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                  xwb_lat; // Latch earlier
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     end // if (dena)
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   assign xwb_sel_o = 4'hF;
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   // Independent on pipeline
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   reg                  xBLK;
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   always @(posedge gclk)
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     if (grst) begin
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        /*AUTORESET*/
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        // Beginning of autoreset for uninitialized flops
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        xwb_lat <= 32'h0;
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        // End of automatics
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     end else if (xwb_ack_i) begin
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        xwb_lat <= #1 xwb_dat_i;
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     end
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   always @(posedge gclk)
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     if (grst) begin
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        /*AUTORESET*/
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        // Beginning of autoreset for uninitialized flops
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        xBLK <= 1'h0;
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        xwb_stb_o <= 1'h0;
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        // End of automatics
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     end else if (xwb_fb) begin
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        xBLK <= #1 imm_of[14]; // nGET/nPUT
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        xwb_stb_o <= #1 (dena) ? !opc_of[5] & opc_of[4] & opc_of[3] & opc_of[1] : // GET/PUT
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                     (xwb_stb_o & !xwb_ack_i);
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     end
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   assign xwb_cyc_o = xwb_stb_o;
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   //assign xwb_stb_o = (AEMB_XSL[0]) ? xSTB : 1'bX;
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endmodule // aeMB2_xslif
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/*
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 $Log: not supported by cvs2svn $
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 Revision 1.6  2008/04/27 16:04:12  sybreon
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 Fixed minor typos.
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 Revision 1.5  2008/04/26 17:57:43  sybreon
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 Minor performance improvements.
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 Revision 1.4  2008/04/26 01:09:06  sybreon
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 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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 Revision 1.3  2008/04/21 12:11:38  sybreon
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 Passes arithmetic tests with single thread.
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 Revision 1.2  2008/04/20 16:34:32  sybreon
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 Basic version with some features left out.
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 Revision 1.1  2008/04/18 00:21:52  sybreon
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 Initial import.
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*/

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