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alirezamon |
/* $Id: aeMB_xecu.v,v 1.12 2008-05-11 13:48:46 sybreon Exp $
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**
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** AEMB MAIN EXECUTION ALU
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** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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**
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** This file is part of AEMB.
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**
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** AEMB is free software: you can redistribute it and/or modify it
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** under the terms of the GNU Lesser General Public License as
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** published by the Free Software Foundation, either version 3 of the
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** License, or (at your option) any later version.
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**
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** AEMB is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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**
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** You should have received a copy of the GNU Lesser General Public
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** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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*/
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`timescale 1ns/1ps
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module aeMB_xecu (/*AUTOARG*/
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// Outputs
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dwb_adr_o, dwb_sel_o, fsl_adr_o, fsl_tag_o, rRESULT, rDWBSEL,
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rMSR_IE, rMSR_BIP,
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// Inputs
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rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY, rALT,
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rSTALL, rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena
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);
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parameter DW=32;
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parameter MUL=0;
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parameter BSF=0;
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// DATA WISHBONE
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output [DW-1:2] dwb_adr_o;
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output [3:0] dwb_sel_o;
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// FSL WISHBONE
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output [6:2] fsl_adr_o;
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output [1:0] fsl_tag_o;
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// INTERNAL
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output [31:0] rRESULT;
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output [3:0] rDWBSEL;
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output rMSR_IE;
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output rMSR_BIP;
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input [31:0] rREGA, rREGB;
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input [1:0] rMXSRC, rMXTGT;
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input [4:0] rRA, rRB;
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input [2:0] rMXALU;
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input rBRA, rDLY;
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input [10:0] rALT;
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input rSTALL;
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input [31:0] rSIMM;
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input [15:0] rIMM;
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input [5:0] rOPC;
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input [4:0] rRD;
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input [31:0] rDWBDI;
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input [31:2] rPC;
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// SYSTEM
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input gclk, grst, gena;
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reg rMSR_C, xMSR_C;
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reg rMSR_IE, xMSR_IE;
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reg rMSR_BE, xMSR_BE;
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reg rMSR_BIP, xMSR_BIP;
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wire fSKIP = rBRA & !rDLY;
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// --- OPERAND SELECT
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reg [31:0] rOPA, rOPB;
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always @(/*AUTOSENSE*/rDWBDI or rMXSRC or rPC or rREGA or rRESULT)
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case (rMXSRC)
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2'o0: rOPA <= rREGA;
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2'o1: rOPA <= rRESULT;
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2'o2: rOPA <= rDWBDI;
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2'o3: rOPA <= {rPC, 2'o0};
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endcase // case (rMXSRC)
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always @(/*AUTOSENSE*/rDWBDI or rMXTGT or rREGB or rRESULT or rSIMM)
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case (rMXTGT)
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2'o0: rOPB <= rREGB;
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2'o1: rOPB <= rRESULT;
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2'o2: rOPB <= rDWBDI;
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2'o3: rOPB <= rSIMM;
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endcase // case (rMXTGT)
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// --- ADD/SUB SELECTOR ----
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reg rRES_ADDC;
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reg [31:0] rRES_ADD;
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wire [31:0] wADD;
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wire wADC;
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wire fCCC = !rOPC[5] & rOPC[1]; // & !rOPC[4]
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wire fSUB = !rOPC[5] & rOPC[0]; // & !rOPC[4]
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wire fCMP = !rOPC[3] & rIMM[1]; // unsigned only
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wire wCMP = (fCMP) ? !wADC : wADD[31]; // cmpu adjust
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wire [31:0] wOPA = (fSUB) ? ~rOPA : rOPA;
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wire wOPC = (fCCC) ? rMSR_C : fSUB;
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assign {wADC, wADD} = (rOPB + wOPA) + wOPC; // add carry
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always @(/*AUTOSENSE*/wADC or wADD or wCMP) begin
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{rRES_ADDC, rRES_ADD} <= #1 {wADC, wCMP, wADD[30:0]}; // add with carry
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end
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// --- LOGIC SELECTOR --------------------------------------
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reg [31:0] rRES_LOG;
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always @(/*AUTOSENSE*/rOPA or rOPB or rOPC)
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case (rOPC[1:0])
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2'o0: rRES_LOG <= #1 rOPA | rOPB;
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2'o1: rRES_LOG <= #1 rOPA & rOPB;
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2'o2: rRES_LOG <= #1 rOPA ^ rOPB;
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2'o3: rRES_LOG <= #1 rOPA & ~rOPB;
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endcase // case (rOPC[1:0])
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// --- SHIFTER SELECTOR ------------------------------------
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reg [31:0] rRES_SFT;
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reg rRES_SFTC;
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always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA)
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case (rIMM[6:5])
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2'o0: {rRES_SFT, rRES_SFTC} <= #1 {rOPA[31],rOPA[31:0]};
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2'o1: {rRES_SFT, rRES_SFTC} <= #1 {rMSR_C,rOPA[31:0]};
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2'o2: {rRES_SFT, rRES_SFTC} <= #1 {1'b0,rOPA[31:0]};
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2'o3: {rRES_SFT, rRES_SFTC} <= #1 (rIMM[0]) ? { {(16){rOPA[15]}}, rOPA[15:0], rMSR_C} :
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{ {(24){rOPA[7]}}, rOPA[7:0], rMSR_C};
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endcase // case (rIMM[6:5])
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// --- MOVE SELECTOR ---------------------------------------
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wire [31:0] wMSR = {rMSR_C, 3'o0,
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20'h0ED32,
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4'h0, rMSR_BIP, rMSR_C, rMSR_IE, rMSR_BE};
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wire fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0];
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wire fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0];
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reg [31:0] rRES_MOV;
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always @(/*AUTOSENSE*/fMFPC or fMFSR or rOPA or rOPB or rPC or rRA
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or wMSR)
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rRES_MOV <= (fMFSR) ? wMSR :
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(fMFPC) ? rPC :
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(rRA[3]) ? rOPB :
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rOPA;
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// --- MULTIPLIER ------------------------------------------
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// TODO: 2 stage multiplier
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reg [31:0] rRES_MUL, rRES_MUL0, xRES_MUL;
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always @(/*AUTOSENSE*/rOPA or rOPB) begin
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xRES_MUL <= (rOPA * rOPB);
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end
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always @(posedge gclk)
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if (grst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rRES_MUL <= 32'h0;
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// End of automatics
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end else if (rSTALL) begin
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rRES_MUL <= #1 xRES_MUL;
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end
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// --- BARREL SHIFTER --------------------------------------
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reg [31:0] rRES_BSF;
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reg [31:0] xBSRL, xBSRA, xBSLL;
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// Infer a logical left barrel shifter.
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always @(/*AUTOSENSE*/rOPA or rOPB)
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xBSLL <= rOPA << rOPB[4:0];
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// Infer a logical right barrel shifter.
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always @(/*AUTOSENSE*/rOPA or rOPB)
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xBSRL <= rOPA >> rOPB[4:0];
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// Infer a arithmetic right barrel shifter.
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always @(/*AUTOSENSE*/rOPA or rOPB)
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case (rOPB[4:0])
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5'd00: xBSRA <= rOPA;
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5'd01: xBSRA <= {{(1){rOPA[31]}}, rOPA[31:1]};
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5'd02: xBSRA <= {{(2){rOPA[31]}}, rOPA[31:2]};
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5'd03: xBSRA <= {{(3){rOPA[31]}}, rOPA[31:3]};
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5'd04: xBSRA <= {{(4){rOPA[31]}}, rOPA[31:4]};
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5'd05: xBSRA <= {{(5){rOPA[31]}}, rOPA[31:5]};
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5'd06: xBSRA <= {{(6){rOPA[31]}}, rOPA[31:6]};
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5'd07: xBSRA <= {{(7){rOPA[31]}}, rOPA[31:7]};
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5'd08: xBSRA <= {{(8){rOPA[31]}}, rOPA[31:8]};
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5'd09: xBSRA <= {{(9){rOPA[31]}}, rOPA[31:9]};
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5'd10: xBSRA <= {{(10){rOPA[31]}}, rOPA[31:10]};
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5'd11: xBSRA <= {{(11){rOPA[31]}}, rOPA[31:11]};
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5'd12: xBSRA <= {{(12){rOPA[31]}}, rOPA[31:12]};
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5'd13: xBSRA <= {{(13){rOPA[31]}}, rOPA[31:13]};
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5'd14: xBSRA <= {{(14){rOPA[31]}}, rOPA[31:14]};
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5'd15: xBSRA <= {{(15){rOPA[31]}}, rOPA[31:15]};
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5'd16: xBSRA <= {{(16){rOPA[31]}}, rOPA[31:16]};
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5'd17: xBSRA <= {{(17){rOPA[31]}}, rOPA[31:17]};
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5'd18: xBSRA <= {{(18){rOPA[31]}}, rOPA[31:18]};
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5'd19: xBSRA <= {{(19){rOPA[31]}}, rOPA[31:19]};
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5'd20: xBSRA <= {{(20){rOPA[31]}}, rOPA[31:20]};
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5'd21: xBSRA <= {{(21){rOPA[31]}}, rOPA[31:21]};
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5'd22: xBSRA <= {{(22){rOPA[31]}}, rOPA[31:22]};
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5'd23: xBSRA <= {{(23){rOPA[31]}}, rOPA[31:23]};
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5'd24: xBSRA <= {{(24){rOPA[31]}}, rOPA[31:24]};
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5'd25: xBSRA <= {{(25){rOPA[31]}}, rOPA[31:25]};
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5'd26: xBSRA <= {{(26){rOPA[31]}}, rOPA[31:26]};
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5'd27: xBSRA <= {{(27){rOPA[31]}}, rOPA[31:27]};
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5'd28: xBSRA <= {{(28){rOPA[31]}}, rOPA[31:28]};
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5'd29: xBSRA <= {{(29){rOPA[31]}}, rOPA[31:29]};
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5'd30: xBSRA <= {{(30){rOPA[31]}}, rOPA[31:30]};
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5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]};
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endcase // case (rOPB[4:0])
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reg [31:0] rBSRL, rBSRA, rBSLL;
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always @(posedge gclk)
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if (grst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rBSLL <= 32'h0;
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rBSRA <= 32'h0;
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rBSRL <= 32'h0;
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// End of automatics
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end else if (rSTALL) begin
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rBSRL <= #1 xBSRL;
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rBSRA <= #1 xBSRA;
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rBSLL <= #1 xBSLL;
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end
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always @(/*AUTOSENSE*/rALT or rBSLL or rBSRA or rBSRL)
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case (rALT[10:9])
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2'd0: rRES_BSF <= rBSRL;
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2'd1: rRES_BSF <= rBSRA;
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2'd2: rRES_BSF <= rBSLL;
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default: rRES_BSF <= 32'hX;
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endcase // case (rALT[10:9])
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// --- MSR REGISTER -----------------
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// C
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wire fMTS = (rOPC == 6'o45) & rIMM[14] & !fSKIP;
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wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
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always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU
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or rOPA or rRES_ADDC or rRES_SFTC)
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//if (fSKIP | |rXCE) begin
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if (fSKIP) begin
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xMSR_C <= rMSR_C;
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end else
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case (rMXALU)
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3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C;
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3'o1: xMSR_C <= rMSR_C; // LOGIC
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3'o2: xMSR_C <= rRES_SFTC; // SHIFT
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3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C;
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3'o4: xMSR_C <= rMSR_C;
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3'o5: xMSR_C <= rMSR_C;
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default: xMSR_C <= 1'hX;
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endcase // case (rMXALU)
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// IE/BIP/BE
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wire fRTID = (rOPC == 6'o55) & rRD[0] & !fSKIP;
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wire fRTBD = (rOPC == 6'o55) & rRD[1] & !fSKIP;
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wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
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wire fINT = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);
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always @(/*AUTOSENSE*/fINT or fMTS or fRTID or rMSR_IE or rOPA)
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xMSR_IE <= (fINT) ? 1'b0 :
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(fRTID) ? 1'b1 :
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(fMTS) ? rOPA[1] :
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rMSR_IE;
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always @(/*AUTOSENSE*/fBRK or fMTS or fRTBD or rMSR_BIP or rOPA)
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xMSR_BIP <= (fBRK) ? 1'b1 :
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(fRTBD) ? 1'b0 :
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(fMTS) ? rOPA[3] :
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rMSR_BIP;
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always @(/*AUTOSENSE*/fMTS or rMSR_BE or rOPA)
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xMSR_BE <= (fMTS) ? rOPA[0] : rMSR_BE;
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// --- RESULT SELECTOR -------------------------------------------
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// Selects results from functional units.
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293 |
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|
reg [31:0] rRESULT, xRESULT;
|
294 |
|
|
|
295 |
|
|
// RESULT
|
296 |
|
|
always @(/*AUTOSENSE*/fSKIP or rMXALU or rRES_ADD or rRES_BSF
|
297 |
|
|
or rRES_LOG or rRES_MOV or rRES_MUL or rRES_SFT)
|
298 |
|
|
if (fSKIP)
|
299 |
|
|
/*AUTORESET*/
|
300 |
|
|
// Beginning of autoreset for uninitialized flops
|
301 |
|
|
xRESULT <= 32'h0;
|
302 |
|
|
// End of automatics
|
303 |
|
|
else
|
304 |
|
|
case (rMXALU)
|
305 |
|
|
3'o0: xRESULT <= rRES_ADD;
|
306 |
|
|
3'o1: xRESULT <= rRES_LOG;
|
307 |
|
|
3'o2: xRESULT <= rRES_SFT;
|
308 |
|
|
3'o3: xRESULT <= rRES_MOV;
|
309 |
|
|
3'o4: xRESULT <= (MUL) ? rRES_MUL : 32'hX;
|
310 |
|
|
3'o5: xRESULT <= (BSF) ? rRES_BSF : 32'hX;
|
311 |
|
|
default: xRESULT <= 32'hX;
|
312 |
|
|
endcase // case (rMXALU)
|
313 |
|
|
|
314 |
|
|
// --- DATA WISHBONE -----
|
315 |
|
|
|
316 |
|
|
reg [3:0] rDWBSEL, xDWBSEL;
|
317 |
|
|
assign dwb_adr_o = rRESULT[DW-1:2];
|
318 |
|
|
assign dwb_sel_o = rDWBSEL;
|
319 |
|
|
|
320 |
|
|
always @(/*AUTOSENSE*/rOPC or wADD)
|
321 |
|
|
case (rOPC[1:0])
|
322 |
|
|
2'o0: case (wADD[1:0]) // 8'bit
|
323 |
|
|
2'o0: xDWBSEL <= 4'h8;
|
324 |
|
|
2'o1: xDWBSEL <= 4'h4;
|
325 |
|
|
2'o2: xDWBSEL <= 4'h2;
|
326 |
|
|
2'o3: xDWBSEL <= 4'h1;
|
327 |
|
|
endcase // case (wADD[1:0])
|
328 |
|
|
2'o1: xDWBSEL <= (wADD[1]) ? 4'h3 : 4'hC; // 16'bit
|
329 |
|
|
2'o2: xDWBSEL <= 4'hF; // 32'bit
|
330 |
|
|
2'o3: xDWBSEL <= 4'h0; // FSL
|
331 |
|
|
endcase // case (rOPC[1:0])
|
332 |
|
|
|
333 |
|
|
// --- FSL WISHBONE --------------------
|
334 |
|
|
|
335 |
|
|
reg [14:2] rFSLADR, xFSLADR;
|
336 |
|
|
|
337 |
|
|
assign {fsl_adr_o, fsl_tag_o} = rFSLADR[8:2];
|
338 |
|
|
|
339 |
|
|
always @(/*AUTOSENSE*/rALT or rRB) begin
|
340 |
|
|
xFSLADR <= {rALT, rRB[3:2]};
|
341 |
|
|
end
|
342 |
|
|
|
343 |
|
|
// --- SYNC ---
|
344 |
|
|
|
345 |
|
|
always @(posedge gclk)
|
346 |
|
|
if (grst) begin
|
347 |
|
|
/*AUTORESET*/
|
348 |
|
|
// Beginning of autoreset for uninitialized flops
|
349 |
|
|
rDWBSEL <= 4'h0;
|
350 |
|
|
rFSLADR <= 13'h0;
|
351 |
|
|
rMSR_BE <= 1'h0;
|
352 |
|
|
rMSR_BIP <= 1'h0;
|
353 |
|
|
rMSR_C <= 1'h0;
|
354 |
|
|
rMSR_IE <= 1'h0;
|
355 |
|
|
rRESULT <= 32'h0;
|
356 |
|
|
// End of automatics
|
357 |
|
|
end else if (gena) begin // if (grst)
|
358 |
|
|
rRESULT <= #1 xRESULT;
|
359 |
|
|
rDWBSEL <= #1 xDWBSEL;
|
360 |
|
|
rMSR_C <= #1 xMSR_C;
|
361 |
|
|
rMSR_IE <= #1 xMSR_IE;
|
362 |
|
|
rMSR_BE <= #1 xMSR_BE;
|
363 |
|
|
rMSR_BIP <= #1 xMSR_BIP;
|
364 |
|
|
rFSLADR <= #1 xFSLADR;
|
365 |
|
|
end
|
366 |
|
|
|
367 |
|
|
endmodule // aeMB_xecu
|
368 |
|
|
|
369 |
|
|
/*
|
370 |
|
|
$Log: not supported by cvs2svn $
|
371 |
|
|
Revision 1.11 2008/01/19 15:57:36 sybreon
|
372 |
|
|
Fix MTS during interrupt vectoring bug (reported by M. Ettus).
|
373 |
|
|
|
374 |
|
|
Revision 1.10 2007/12/25 22:15:09 sybreon
|
375 |
|
|
Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
|
376 |
|
|
|
377 |
|
|
Revision 1.9 2007/11/30 16:42:51 sybreon
|
378 |
|
|
Minor code cleanup.
|
379 |
|
|
|
380 |
|
|
Revision 1.8 2007/11/16 21:52:03 sybreon
|
381 |
|
|
Added fsl_tag_o to FSL bus (tag either address or data).
|
382 |
|
|
|
383 |
|
|
Revision 1.7 2007/11/14 22:14:34 sybreon
|
384 |
|
|
Changed interrupt handling system (reported by M. Ettus).
|
385 |
|
|
|
386 |
|
|
Revision 1.6 2007/11/10 16:39:38 sybreon
|
387 |
|
|
Upgraded license to LGPLv3.
|
388 |
|
|
Significant performance optimisations.
|
389 |
|
|
|
390 |
|
|
Revision 1.5 2007/11/09 20:51:52 sybreon
|
391 |
|
|
Added GET/PUT support through a FSL bus.
|
392 |
|
|
|
393 |
|
|
Revision 1.4 2007/11/08 14:17:47 sybreon
|
394 |
|
|
Parameterised optional components.
|
395 |
|
|
|
396 |
|
|
Revision 1.3 2007/11/03 08:34:55 sybreon
|
397 |
|
|
Minor code cleanup.
|
398 |
|
|
|
399 |
|
|
Revision 1.2 2007/11/02 19:20:58 sybreon
|
400 |
|
|
Added better (beta) interrupt support.
|
401 |
|
|
Changed MSR_IE to disabled at reset as per MB docs.
|
402 |
|
|
|
403 |
|
|
Revision 1.1 2007/11/02 03:25:41 sybreon
|
404 |
|
|
New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
|
405 |
|
|
Fixed various minor data hazard bugs.
|
406 |
|
|
Code compatible with -O0/1/2/3/s generated code.
|
407 |
|
|
|
408 |
|
|
*/
|